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| author | Matt Ettus <matt@ettus.com> | 2009-10-01 00:21:24 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-10-01 00:21:24 -0700 |
| commit | 0a0655b56b84aa6557cdfaece206d0f5cf6ebeac (patch) | |
| tree | 355546561a3484426c20de7482560a01ff5f913e | |
| parent | ac31c35bea6cad3cca5ac3d45d86a91d07e80dd8 (diff) | |
| download | uhd-0a0655b56b84aa6557cdfaece206d0f5cf6ebeac.tar.gz uhd-0a0655b56b84aa6557cdfaece206d0f5cf6ebeac.tar.bz2 uhd-0a0655b56b84aa6557cdfaece206d0f5cf6ebeac.zip | |
fullchip sim now compiles again, after moving eth and models over to new simple_gemac
| -rw-r--r-- | models/miim_model.v | 14 | ||||
| -rw-r--r-- | models/phy_sim.v | 113 | ||||
| -rw-r--r-- | models/xlnx_glbl.v | 29 | ||||
| -rw-r--r-- | testbench/cmdfile | 18 | ||||
| -rw-r--r-- | top/single_u2_sim/single_u2_sim.v | 2 |
5 files changed, 159 insertions, 17 deletions
diff --git a/models/miim_model.v b/models/miim_model.v new file mode 100644 index 000000000..936d99a80 --- /dev/null +++ b/models/miim_model.v @@ -0,0 +1,14 @@ + +// Skeleton PHY interface simulator + +module miim_model(input mdc_i, + inout mdio, + input phy_resetn_i, + input phy_clk_i, + output phy_intn_o, + output [2:0] speed_o); + + assign phy_intn_o = 1; // No interrupts + assign speed_o = 3'b100; // 1G mode + +endmodule // miim_model diff --git a/models/phy_sim.v b/models/phy_sim.v new file mode 100644 index 000000000..b3de19b04 --- /dev/null +++ b/models/phy_sim.v @@ -0,0 +1,113 @@ +//////////////////////////////////////////////////////////////////////
+//// ////
+//// Phy_sim.v ////
+//// ////
+//// This file is part of the Ethernet IP core project ////
+//// http://www.opencores.org/projects.cgi/web/ethernet_tri_mode/////
+//// ////
+//// Author(s): ////
+//// - Jon Gao (gaojon@yahoo.com) ////
+//// ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2001 Authors ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer. ////
+//// ////
+//// This source file is free software; you can redistribute it ////
+//// and/or modify it under the terms of the GNU Lesser General ////
+//// Public License as published by the Free Software Foundation; ////
+//// either version 2.1 of the License, or (at your option) any ////
+//// later version. ////
+//// ////
+//// This source is distributed in the hope that it will be ////
+//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
+//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
+//// PURPOSE. See the GNU Lesser General Public License for more ////
+//// details. ////
+//// ////
+//// You should have received a copy of the GNU Lesser General ////
+//// Public License along with this source; if not, download it ////
+//// from http://www.opencores.org/lgpl.shtml ////
+//// ////
+//////////////////////////////////////////////////////////////////////
+//
+// CVS Revision History
+//
+// $Log: Phy_sim.v,v $
+// Revision 1.3 2006/11/17 17:53:07 maverickist
+// no message
+//
+// Revision 1.2 2006/01/19 14:07:50 maverickist
+// verification is complete.
+//
+// Revision 1.1.1.1 2005/12/13 01:51:44 Administrator
+// no message
+//
+
+`timescale 1ns/100ps
+
+module phy_sim(
+ input Gtx_clk, // Used only in GMII mode
+ output Rx_clk,
+ output Tx_clk, // Used only in MII mode
+ input Tx_er,
+ input Tx_en,
+ input [7:0] Txd,
+ output Rx_er,
+ output Rx_dv,
+ output [7:0] Rxd,
+ output Crs,
+ output Col,
+ input [2:0] Speed,
+ input Done
+);
+
+//////////////////////////////////////////////////////////////////////
+// this file used to simulate Phy.
+// generate clk and loop the Tx data to Rx data
+// full duplex mode can be verified on loop mode.
+//////////////////////////////////////////////////////////////////////
+//////////////////////////////////////////////////////////////////////
+// internal signals
+//////////////////////////////////////////////////////////////////////
+reg Clk_25m; // Used for 100 Mbps mode
+reg Clk_2_5m; // Used for 10 Mbps mode
+
+//wire Rx_clk;
+//wire Tx_clk; // Used only in MII mode
+
+ initial
+ begin
+ #10;
+ while ( !Done )
+ begin
+ #20 Clk_25m = 0;
+ #20 Clk_25m = 1;
+ end
+ end
+
+ initial
+ begin
+ #10;
+ while ( !Done )
+ begin
+ #200 Clk_2_5m = 0;
+ #200 Clk_2_5m = 1;
+ end
+ end
+
+ assign Rx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
+ assign Tx_clk = Speed[2] ? Gtx_clk : Speed[1] ? Clk_25m : Speed[0] ? Clk_2_5m : 0;
+
+ assign Rx_dv = Tx_en;
+ assign Rxd = Txd;
+ assign Rx_er = Tx_er;
+ assign Crs = Tx_en;
+ assign Col = 0;
+
+endmodule
diff --git a/models/xlnx_glbl.v b/models/xlnx_glbl.v new file mode 100644 index 000000000..662a60e35 --- /dev/null +++ b/models/xlnx_glbl.v @@ -0,0 +1,29 @@ +module xlnx_glbl
+(
+ GSR,
+ GTS
+);
+
+ //--------------------------------------------------------------------------
+ // Parameters
+ //--------------------------------------------------------------------------
+
+ //--------------------------------------------------------------------------
+ // IO declarations
+ //--------------------------------------------------------------------------
+
+ output GSR;
+ output GTS;
+
+ //--------------------------------------------------------------------------
+ // Local declarations
+ //--------------------------------------------------------------------------
+
+ //--------------------------------------------------------------------------
+ // Internal declarations
+ //--------------------------------------------------------------------------
+
+ assign GSR = 0;
+ assign GTS = 0;
+
+endmodule
diff --git a/testbench/cmdfile b/testbench/cmdfile index ed251665c..8083eb92a 100644 --- a/testbench/cmdfile +++ b/testbench/cmdfile @@ -9,6 +9,8 @@ -y ../timing -y ../coregen -y ../extram +-y ../simple_gemac +-y ../simple_gemac/miim # Models -y ../models @@ -18,24 +20,8 @@ -y ../opencores/8b10b -y ../opencores/spi/rtl/verilog +incdir+../opencores/spi/rtl/verilog --y ../opencores/wb_conbus/rtl/verilog -+incdir+../opencores/wb_conbus/rtl/verilog -y ../opencores/i2c/rtl/verilog +incdir+../opencores/i2c/rtl/verilog -y ../opencores/aemb/rtl/verilog -y ../opencores/simple_pic/rtl -# Ethernet -+incdir+../eth/rtl/verilog --y ../eth/rtl/verilog --y ../eth/rtl/verilog/MAC_tx --y ../eth/rtl/verilog/MAC_rx --y ../eth/rtl/verilog/miim --y ../eth/rtl/verilog/TECH --y ../eth/rtl/verilog/TECH/xilinx --y ../eth/rtl/verilog/RMON --y ../eth --y ../eth/bench/verilog - -# Ethernet Models --y ../eth/bench/verilog diff --git a/top/single_u2_sim/single_u2_sim.v b/top/single_u2_sim/single_u2_sim.v index 016815ff7..2a7b24849 100644 --- a/top/single_u2_sim/single_u2_sim.v +++ b/top/single_u2_sim/single_u2_sim.v @@ -178,7 +178,7 @@ module single_u2_sim(); .adc_b(adc_b),.adc_ovf_b(adc_ovf_b),.adc_on_b(adc_on_b),.adc_oe_b(adc_oe_b) ); wire [2:0] speed; - Phy_sim phy_model + phy_sim phy_model (.Gtx_clk(GMII_GTX_CLK), . Rx_clk(GMII_RX_CLK), .Tx_clk(GMII_TX_CLK), .Tx_er(GMII_TX_ER), .Tx_en(GMII_TX_EN), .Txd(GMII_TXD), .Rx_er(GMII_RX_ER), .Rx_dv(GMII_RX_DV), .Rxd(GMII_RXD), |