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| author | Matt Ettus <matt@ettus.com> | 2011-07-08 09:46:29 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-07-19 13:48:20 -0700 |
| commit | dd6d11c2255c646a48ff0c866b74c80869d94eac (patch) | |
| tree | 2d3ae0fe54c1107fef8246ec86f45d61f5d18df4 | |
| parent | aa23e88769c572ab50ecc0460301790a03574729 (diff) | |
| download | uhd-dd6d11c2255c646a48ff0c866b74c80869d94eac.tar.gz uhd-dd6d11c2255c646a48ff0c866b74c80869d94eac.tar.bz2 uhd-dd6d11c2255c646a48ff0c866b74c80869d94eac.zip | |
dsp: reset the interpolator when the rate changes, to prevent oscillation
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_tx.v | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/usrp2/sdr_lib/dsp_core_tx.v b/usrp2/sdr_lib/dsp_core_tx.v index f02c63b42..4e0163e0a 100644 --- a/usrp2/sdr_lib/dsp_core_tx.v +++ b/usrp2/sdr_lib/dsp_core_tx.v @@ -36,7 +36,8 @@ module dsp_core_tx wire [7:0] interp_rate; wire [3:0] dacmux_a, dacmux_b; wire enable_hb1, enable_hb2; - + wire rate_change; + setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); @@ -47,7 +48,7 @@ module dsp_core_tx setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed()); + .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed(rate_change)); // Strobes are all now delayed by 1 cycle for timing reasons wire strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre; @@ -56,13 +57,13 @@ module dsp_core_tx reg strobe_hb2 = 1; cic_strober #(.WIDTH(8)) - cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + cic_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate), .strobe_fast(1),.strobe_slow(strobe_cic_pre) ); cic_strober #(.WIDTH(2)) - hb2_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb2 ? 2 : 1), + hb2_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb2 ? 2 : 1), .strobe_fast(strobe_cic_pre),.strobe_slow(strobe_hb2_pre) ); cic_strober #(.WIDTH(2)) - hb1_strober(.clock(clk),.reset(rst),.enable(run),.rate(enable_hb1 ? 2 : 1), + hb1_strober(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(enable_hb1 ? 2 : 1), .strobe_fast(strobe_hb2_pre),.strobe_slow(strobe_hb1_pre) ); always @(posedge clk) strobe_hb1 <= strobe_hb1_pre; @@ -104,12 +105,12 @@ module dsp_core_tx .output_rate(interp_rate),.stb_out(strobe_cic),.data_out(hb2_q)); cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_i(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + cic_interp_i(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate), .strobe_in(strobe_cic),.strobe_out(1), .signal_in(hb2_i),.signal_out(i_interp)); cic_interp #(.bw(18),.N(4),.log2_of_max_rate(7)) - cic_interp_q(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate), + cic_interp_q(.clock(clk),.reset(rst),.enable(run & ~rate_change),.rate(interp_rate), .strobe_in(strobe_cic),.strobe_out(1), .signal_in(hb2_q),.signal_out(q_interp)); |