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| author | Josh Blum <josh@joshknows.com> | 2011-08-15 15:27:50 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-15 15:37:52 -0700 |
| commit | cb1c39a62595909a1da24237c09b137fde5c83b2 (patch) | |
| tree | 87d990502b3ef9c485d8b2197daeccd5585538f8 | |
| parent | edbdb0bf36619a0176da9b1cf6179212fef621a4 (diff) | |
| download | uhd-cb1c39a62595909a1da24237c09b137fde5c83b2.tar.gz uhd-cb1c39a62595909a1da24237c09b137fde5c83b2.tar.bz2 uhd-cb1c39a62595909a1da24237c09b137fde5c83b2.zip | |
connect unused BRAM inputs to 1s to save routing logic
| -rw-r--r-- | usrp2/control_lib/bootram.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/control_lib/bootram.v b/usrp2/control_lib/bootram.v index 249a09814..fb7bd46c8 100644 --- a/usrp2/control_lib/bootram.v +++ b/usrp2/control_lib/bootram.v @@ -82,7 +82,7 @@ module bootram .DOPA(), // Port A 4-bit Parity Output .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input .CLKA(clk), // Port A 1-bit Clock - .DIA(32'd0), // Port A 32-bit Data Input + .DIA(32'hffffffff), // Port A 32-bit Data Input .DIPA(4'd0), // Port A 4-bit parity Input .ENA(1'b1), // Port A 1-bit RAM Enable Input .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input |