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authorJosh Blum <josh@joshknows.com>2012-05-10 20:33:43 -0700
committerJosh Blum <josh@joshknows.com>2012-05-10 20:33:43 -0700
commit9786c2bd7ba90f8a5abe29b19ba69a30f153f1b4 (patch)
tree94d29428c212881d7d0d1200d9fc9d0f908b7362
parentcb313ea980ea1078735b6e009bc3e69d1ae0dbf6 (diff)
parentdb1d63ecaa76f4975b79499119419b5baff10a99 (diff)
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Merge branch 'maint'
Conflicts: usrp2/top/E1x0/u1e_core.v
-rw-r--r--usrp2/gpmc/cross_clock_reader.v14
-rw-r--r--usrp2/top/E1x0/u1e_core.v2
2 files changed, 9 insertions, 7 deletions
diff --git a/usrp2/gpmc/cross_clock_reader.v b/usrp2/gpmc/cross_clock_reader.v
index a30e0385f..a8366badc 100644
--- a/usrp2/gpmc/cross_clock_reader.v
+++ b/usrp2/gpmc/cross_clock_reader.v
@@ -1,5 +1,5 @@
//
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
@@ -26,17 +26,19 @@ module cross_clock_reader
output reg [WIDTH-1:0] out
);
- reg [WIDTH-1:0] shadow;
+ reg [WIDTH-1:0] shadow0, shadow1;
always @(posedge clk) begin
if (rst) begin
out <= DEFAULT;
- shadow <= DEFAULT;
+ shadow0 <= DEFAULT;
+ shadow1 <= DEFAULT;
end
- else if (shadow == in) begin
- out <= shadow;
+ else if (shadow0 == shadow1) begin
+ out <= shadow1;
end
- shadow <= in;
+ shadow0 <= in;
+ shadow1 <= shadow0;
end
endmodule //cross_clock_reader
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index d4af8c0df..77be1bfb0 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -454,7 +454,7 @@ module u1e_core
// Readback mux 32 -- Slave #7
//compatibility number -> increment when the fpga has been sufficiently altered
- localparam compat_num = {16'd10, 16'd0}; //major, minor
+ localparam compat_num = {16'd10, 16'd1}; //major, minor
wire [31:0] reg_test32;