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| author | Josh Blum <josh@joshknows.com> | 2013-04-02 18:50:56 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2013-04-02 18:50:56 -0700 |
| commit | 4a860d7471a55700c41671922c157d243fea6247 (patch) | |
| tree | 84dc57aa9c9193d3c2f282c61c062c9423f5458e | |
| parent | 31b23a19017b7cba7e7563133e0e09dec30fc89e (diff) | |
| parent | 36c11bb9f8244d16dc357323a2c8137f7096586b (diff) | |
| download | uhd-4a860d7471a55700c41671922c157d243fea6247.tar.gz uhd-4a860d7471a55700c41671922c157d243fea6247.tar.bz2 uhd-4a860d7471a55700c41671922c157d243fea6247.zip | |
Merge branch 'maint'
| -rw-r--r-- | fpga/usrp2/top/E1x0/Makefile.E110 | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/fpga/usrp2/top/E1x0/Makefile.E110 b/fpga/usrp2/top/E1x0/Makefile.E110 index c2d3e39e6..e5be8d2fa 100644 --- a/fpga/usrp2/top/E1x0/Makefile.E110 +++ b/fpga/usrp2/top/E1x0/Makefile.E110 @@ -50,6 +50,7 @@ simulator "ISE Simulator (VHDL/Verilog)" \ TOP_SRCS = \ ../B100/u1plus_core.v \ E1x0.v \ +E1x0.ucf \ timing.ucf SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \ |