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| author | Matt Ettus <matt@ettus.com> | 2010-08-25 17:57:06 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-08-25 17:57:06 -0700 | 
| commit | 9fa6105a49f41e39321438086b00ab12d8437828 (patch) | |
| tree | db17d96e34417eb6919353e3b568e8dcd8442252 | |
| parent | 7c057ae28c7dda5f60944fdf79c2bafa081b9bfe (diff) | |
| download | uhd-9fa6105a49f41e39321438086b00ab12d8437828.tar.gz uhd-9fa6105a49f41e39321438086b00ab12d8437828.tar.bz2 uhd-9fa6105a49f41e39321438086b00ab12d8437828.zip | |
clean up DAC inversion and swapping to match schematics
| -rw-r--r-- | usrp2/top/u2_rev3/u2_rev3.v | 9 | 
1 files changed, 6 insertions, 3 deletions
| diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v index d5b382c19..4daa66212 100644 --- a/usrp2/top/u2_rev3/u2_rev3.v +++ b/usrp2/top/u2_rev3/u2_rev3.v @@ -203,9 +203,10 @@ module u2_rev3     reg [13:0] 	 adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;     reg 		 adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, adc_ovf_b_reg2; +    // ADC A and B are swapped in schematic to facilitate clean layout     always @(posedge dsp_clk)       begin -	adc_a_reg1 <= adc_b;    // I and Q on RX are swapped in layout +	adc_a_reg1 <= adc_b;  	adc_b_reg1 <= adc_a;  	adc_ovf_a_reg1 <= adc_ovf_b;  	adc_ovf_b_reg1 <= adc_ovf_a; @@ -327,8 +328,10 @@ module u2_rev3       end     wire [15:0] dac_a_int, dac_b_int; -   always @(negedge dsp_clk) dac_a <= dac_a_int; -   always @(negedge dsp_clk) dac_b <= dac_b_int; +   // DAC A and B are swapped in schematic to facilitate clean layout +   // DAC A is also inverted in schematic to facilitate clean layout +   always @(negedge dsp_clk) dac_a <= ~dac_b_int; +   always @(negedge dsp_clk) dac_b <= dac_a_int;     /*     OFDDRRSE OFDDRRSE_serdes_inst  | 
