quad uart instead of single, for the extra on board serial ports

4 files changed, 82 insertions, 10 deletions

diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
index ad491b83d..666ac344c 100644
--- a/usrp2/control_lib/Makefile.srcs
+++ b/usrp2/control_lib/Makefile.srcs
@@ -30,6 +30,7 @@ srl.v \
 system_control.v \
 wb_1master.v \
 wb_readback_mux.v \
+quad_uart.v \
 simple_uart.v \
 simple_uart_tx.v \
 simple_uart_rx.v \
diff --git a/usrp2/control_lib/quad_uart.v b/usrp2/control_lib/quad_uart.v
new file mode 100644
index 000000000..afa6fae1d
--- /dev/null
+++ b/usrp2/control_lib/quad_uart.v
@@ -0,0 +1,71 @@
+
+module quad_uart
+  #(parameter TXDEPTH = 1,
+    parameter RXDEPTH = 1)
+    (input clk_i, input rst_i,
+     input we_i, input stb_i, input cyc_i, output reg ack_o,
+     input [4:0] adr_i, input [31:0] dat_i, output reg [31:0] dat_o,
+     output [3:0] rx_int_o, output [3:0] tx_int_o, 
+     output [3:0] tx_o, input [3:0] rx_i, output [3:0] baud_o
+     );
+   
+   // Register Map
+   localparam SUART_CLKDIV = 0;
+   localparam SUART_TXLEVEL = 1;
+   localparam SUART_RXLEVEL = 2;
+   localparam SUART_TXCHAR = 3;
+   localparam SUART_RXCHAR = 4;
+   
+   wire       wb_acc = cyc_i & stb_i;            // WISHBONE access
+   wire       wb_wr  = wb_acc & we_i;            // WISHBONE write access
+   
+   reg [15:0] clkdiv[0:3];
+   wire [7:0] rx_char[0:3];
+   wire  [3:0] tx_fifo_full, rx_fifo_empty;   
+   wire [7:0] tx_fifo_level[0:3], rx_fifo_level[0:3];
+
+   always @(posedge clk_i)
+     if (rst_i)
+       ack_o 			    <= 1'b0;
+     else
+       ack_o 			    <= wb_acc & ~ack_o;
+
+   integer    i;
+   always @(posedge clk_i)
+     if (rst_i)
+       for(i=0;i<4;i=i+1)
+	 clkdiv[i] <= 0;
+     else if (wb_wr)
+       case(adr_i[2:0])
+	 SUART_CLKDIV : clkdiv[adr_i[4:3]] <= dat_i[15:0];
+       endcase // case(adr_i)
+   
+   always @(posedge clk_i)
+     case (adr_i[2:0])
+       SUART_TXLEVEL : dat_o <= tx_fifo_level[adr_i[4:3]];
+       SUART_RXLEVEL : dat_o <= rx_fifo_level[adr_i[4:3]];
+       SUART_RXCHAR : dat_o <= rx_char[adr_i[4:3]];
+     endcase // case(adr_i)
+
+   genvar     j;
+   generate
+      for(j=0;j<4;j=j+1)
+	begin : gen_uarts
+	   simple_uart_tx #(.DEPTH(TXDEPTH)) simple_uart_tx
+	    (.clk(clk_i),.rst(rst_i),
+	     .fifo_in(dat_i[7:0]),.fifo_write(ack_o && wb_wr && (adr_i[2:0] == SUART_TXCHAR) && (adr_i[4:3]==j)),
+	     .fifo_level(tx_fifo_level[j]),.fifo_full(tx_fifo_full[j]),
+	     .clkdiv(clkdiv[j]),.baudclk(baud_o[j]),.tx(tx_o[j]));
+	   
+	   simple_uart_rx #(.DEPTH(RXDEPTH)) simple_uart_rx
+	     (.clk(clk_i),.rst(rst_i),
+	      .fifo_out(rx_char[j]),.fifo_read(ack_o && ~wb_wr && (adr_i[2:0] == SUART_RXCHAR) && (adr_i[4:3]==j)),
+	      .fifo_level(rx_fifo_level[j]),.fifo_empty(rx_fifo_empty[j]),
+	      .clkdiv(clkdiv[j]),.rx(rx_i[j]));
+	end // block: gen_uarts
+   endgenerate
+   
+   assign     tx_int_o 	= ~tx_fifo_full;  // Interrupt for those that have space
+   assign     rx_int_o 	= ~rx_fifo_empty; // Interrupt for those that have data
+   
+endmodule // quad_uart
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index d894631ac..a0ba4d4cc 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -381,8 +381,8 @@ module u2plus
 		     .RAM_WEn           (RAM_WEn),
 		     .RAM_OEn           (RAM_OEn),
 		     .RAM_LDn           (RAM_LDn), 
-		     .uart_tx_o         (TXD[1]),
-		     .uart_rx_i         (RXD[1]),
+		     .uart_tx_o         (TXD[3:1]),
+		     .uart_rx_i         ({1'b1,RXD[3:1]}),
 		     .uart_baud_o       (),
 		     .sim_mode          (1'b0),
 		     .clock_divider     (2),
@@ -395,6 +395,5 @@ module u2plus
 
    assign RAM_ZZ = 1;
    assign RAM_BWn = 4'b1111;
-   assign TXD[3:2] = 2'b11;
    
 endmodule // u2plus
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index 6092f1ba3..79318aa27 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -120,9 +120,9 @@ module u2plus_core
    output RAM_LDn,
    
    // Debug stuff
-   output uart_tx_o, 
-   input uart_rx_i,
-   output uart_baud_o,
+   output [3:0] uart_tx_o, 
+   input [3:0] uart_rx_i,
+   output [3:0] uart_baud_o,
    input sim_mode,
    input [3:0] clock_divider,
    input button,
@@ -156,7 +156,8 @@ module u2plus_core
 
    wire [31:0] 	status, status_b0, status_b1, status_b2, status_b3, status_b4, status_b5, status_b6, status_b7;
    wire 	bus_error, spi_int, i2c_int, pps_int, onetime_int, periodic_int, buffer_int;
-   wire 	proc_int, overrun, underrun, uart_tx_int, uart_rx_int;
+   wire 	proc_int, overrun, underrun;
+   wire [3:0] 	uart_tx_int, uart_rx_int;
 
    wire [31:0] 	debug_gpio_0, debug_gpio_1;
    wire [31:0] 	atr_lines;
@@ -642,8 +643,8 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_
    // Interrupt Controller, Slave #8
 
    assign irq= {{8'b0},
-		{8'b0},
-		{2'b0, button, periodic_int, clk_status, serdes_link_up, uart_tx_int, uart_rx_int},
+		{uart_tx_int[3:0], uart_rx_int[3:0]},
+		{2'b0, button, periodic_int, clk_status, serdes_link_up, 2'b00},
 		{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,onetime_int,buffer_int}};
    
    pic pic(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[4:2]),
@@ -670,7 +671,7 @@ defparam bootram.RAM2.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_
    simple_uart #(.TXDEPTH(3),.RXDEPTH(3)) uart  // depth of 3 is 128 entries
      (.clk_i(wb_clk),.rst_i(wb_rst),
       .we_i(sa_we),.stb_i(sa_stb),.cyc_i(sa_cyc),.ack_o(sa_ack),
-      .adr_i(sa_adr[4:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
+      .adr_i(sa_adr[6:2]),.dat_i(sa_dat_o),.dat_o(sa_dat_i),
       .rx_int_o(uart_rx_int),.tx_int_o(uart_tx_int),
       .tx_o(uart_tx_o),.rx_i(uart_rx_i),.baud_o(uart_baud_o));