skeleton files copied over from a dead branch

9 files changed, 1728 insertions, 374 deletions

diff --git a/usrp2/top/safe_u2plus/.gitignore b/usrp2/top/safe_u2plus/.gitignore
new file mode 100644
index 000000000..a96f0be92
--- /dev/null
+++ b/usrp2/top/safe_u2plus/.gitignore
@@ -0,0 +1,2 @@
+build*
+*impact*
diff --git a/usrp2/top/safe_u2plus/Makefile b/usrp2/top/safe_u2plus/Makefile
new file mode 100644
index 000000000..62a02ff40
--- /dev/null
+++ b/usrp2/top/safe_u2plus/Makefile
@@ -0,0 +1,246 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := safe_u2plus
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2plus/capture_ddrlvds.v \
+top/safe_u2plus/u2plus.ucf \
+top/safe_u2plus/safe_u2plus.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/safe_u2plus/safe_u2plus.v b/usrp2/top/safe_u2plus/safe_u2plus.v
new file mode 100644
index 000000000..38b276000
--- /dev/null
+++ b/usrp2/top/safe_u2plus/safe_u2plus.v
@@ -0,0 +1,362 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+
+module safe_u2plus
+  (
+   input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   
+   // ADC
+   //input ADC_clkout_p, //input ADC_clkout_n,
+   //input ADCA_12_p, //input ADCA_12_n,
+   //input ADCA_10_p, //input ADCA_10_n,
+   //input ADCA_8_p, //input ADCA_8_n,
+   //input ADCA_6_p, //input ADCA_6_n,
+   //input ADCA_4_p, //input ADCA_4_n,
+   //input ADCA_2_p, //input ADCA_2_n,
+   //input ADCA_0_p, //input ADCA_0_n,
+   //input ADCB_12_p, //input ADCB_12_n,
+   //input ADCB_10_p, //input ADCB_10_n,
+   //input ADCB_8_p, //input ADCB_8_n,
+   //input ADCB_6_p, //input ADCB_6_n,
+   //input ADCB_4_p, //input ADCB_4_n,
+   //input ADCB_2_p, //input ADCB_2_n,
+   //input ADCB_0_p, //input ADCB_0_n,
+   
+   // DAC
+   //output [15:0] DACA,
+   //output [15:0] DACB,
+   //input DAC_LOCK,     // unused for now
+   
+   // DB IO Pins
+   //inout [15:0] io_tx,
+   //inout [15:0] io_rx,
+
+   // Misc, debug
+   output [5:1] leds,  // LED4 is shared w/INIT_B
+   //input FPGA_RESET,
+   //output [1:0] debug_clk,
+   //output [31:0] debug,
+   //output [3:1] TXD, //input [3:1] RXD, // UARTs
+   ////input [3:0] dipsw,  // Forgot DIP Switches...
+   
+   // Clock Gen Control
+   //output [1:0] clk_en,
+   //output [1:0] clk_sel,
+   //input CLK_FUNC,        // FIXME is an //input to control the 9510
+   //input CLK_STATUS,
+
+   //inout SCL, //inout SDA,   // I2C
+
+   // PPS
+   //input PPS_IN, //input PPS2_IN,
+
+   // SPI
+   //output SEN_CLK, //output SCLK_CLK, //output MOSI_CLK, //input MISO_CLK,
+   //output SEN_DAC, //output SCLK_DAC, //output MOSI_DAC, //input MISO_DAC,
+   //output SEN_ADC, //output SCLK_ADC, //output MOSI_ADC,
+   //output SEN_TX_DB, //output SCLK_TX_DB, //output MOSI_TX_DB, //input MISO_TX_DB,
+   //output SEN_TX_DAC, //output SCLK_TX_DAC, //output MOSI_TX_DAC,
+   //output SEN_TX_ADC, //output SCLK_TX_ADC, //output MOSI_TX_ADC, //input MISO_TX_ADC,
+   //output SEN_RX_DB, //output SCLK_RX_DB, //output MOSI_RX_DB, //input MISO_RX_DB,
+   //output SEN_RX_DAC, //output SCLK_RX_DAC, //output MOSI_RX_DAC,
+   //output SEN_RX_ADC, //output SCLK_RX_ADC, //output MOSI_RX_ADC, //input MISO_RX_ADC,
+
+   // GigE PHY
+   //input CLK_TO_MAC,
+
+   //output reg [7:0] GMII_TXD,
+   //output reg GMII_TX_EN,
+   //output reg GMII_TX_ER,
+   //output GMII_GTX_CLK,
+   //input GMII_TX_CLK,  // 100mbps clk
+
+   //input GMII_RX_CLK,
+   //input [7:0] GMII_RXD,
+   //input GMII_RX_DV,
+   //input GMII_RX_ER,
+   //input GMII_COL,
+   //input GMII_CRS,
+
+   //input PHY_INTn,   // open drain
+   //inout MDIO,
+   //output MDC,
+   //output PHY_RESETn,
+   output ETH_LED
+   
+   //input POR,
+   
+   // Expansion
+   //input exp_time_in_p, //input exp_time_in_n, // Diff
+   //output exp_time_out_p, //output exp_time_out_n, // Diff 
+   //input exp_user_in_p, //input exp_user_in_n, // Diff
+   //output exp_user_out_p, //output exp_user_out_n, // Diff 
+   
+   // SERDES
+   //output ser_enable,
+   //output ser_prbsen,
+   //output ser_loopen,
+   //output ser_rx_en,
+   
+   //output ser_tx_clk,
+   //output reg [15:0] ser_t,
+   //output reg ser_tklsb,
+   //output reg ser_tkmsb,
+
+   //input ser_rx_clk,
+   //input [15:0] ser_r,
+   //input ser_rklsb,
+   //input ser_rkmsb,
+
+   // SRAM
+   //inout [35:0] RAM_D,
+   //output [20:0] RAM_A,
+   //output [3:0] RAM_BWn,
+   //output RAM_ZZ,
+   //output RAM_LDn,
+   //output RAM_OEn,
+   //output RAM_WEn,
+   //output RAM_CENn,
+   //output RAM_CLK,
+   
+   // SPI Flash
+   //output flash_cs,
+   //output flash_clk,
+   //output flash_mosi,
+   //input flash_miso
+   );
+
+   // FPGA-specific pins connections
+   wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
+
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
+   defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
+
+   reg [31:0] 	ctr;
+
+   always @(posedge clk_fpga)
+     ctr <= ctr + 1;
+
+   assign {leds,ETH_LED} = ~ctr[29:24];
+   
+
+/*   
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD  = "LVDS_25";
+
+   wire 	dcm_rst 		    = 0;
+
+   wire [13:0] 	adc_a, adc_b;
+
+   capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds
+     (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), 
+      .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p},
+	     {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), 
+      .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n},
+	     {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), 
+      .out({adc_a,adc_b}));
+   
+   // Handle Clocks
+   DCM DCM_INST (.CLKFB(dsp_clk), 
+                 .CLKIN(clk_fpga), 
+                 .DSSEN(0), 
+                 .PSCLK(0), 
+                 .PSEN(0), 
+                 .PSINCDEC(0), 
+                 .RST(dcm_rst), 
+                 .CLKDV(clk_div), 
+                 .CLKFX(), 
+                 .CLKFX180(), 
+                 .CLK0(dcm_out), 
+                 .CLK2X(), 
+                 .CLK2X180(), 
+                 .CLK90(), 
+                 .CLK180(), 
+                 .CLK270(), 
+                 .LOCKED(LOCKED_OUT), 
+                 .PSDONE(), 
+                 .STATUS());
+   defparam DCM_INST.CLK_FEEDBACK = "1X";
+   defparam DCM_INST.CLKDV_DIVIDE = 2.0;
+   defparam DCM_INST.CLKFX_DIVIDE = 1;
+   defparam DCM_INST.CLKFX_MULTIPLY = 4;
+   defparam DCM_INST.CLKIN_DIVIDE_BY_2 = "FALSE";
+   defparam DCM_INST.CLKIN_PERIOD = 10.000;
+   defparam DCM_INST.CLKOUT_PHASE_SHIFT = "NONE";
+   defparam DCM_INST.DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";
+   defparam DCM_INST.DFS_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DLL_FREQUENCY_MODE = "LOW";
+   defparam DCM_INST.DUTY_CYCLE_CORRECTION = "TRUE";
+   defparam DCM_INST.FACTORY_JF = 16'h8080;
+   defparam DCM_INST.PHASE_SHIFT = 0;
+   defparam DCM_INST.STARTUP_WAIT = "FALSE";
+
+   BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
+   BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));
+
+   // I2C -- Don't use external transistors for open drain, the FPGA implements this
+   IOBUF scl_pin(.O(scl_pad_i), .IO(SCL), .I(scl_pad_o), .T(scl_pad_oen_o));
+   IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+   // LEDs are active low outputs
+   wire [4:0] leds_int;
+   assign     leds = ~leds_int;  // drive low to turn on leds
+   
+   // SPI
+   wire       miso, mosi, sclk;
+
+   assign 	{SCLK_CLK,MOSI_CLK} 	   = ~SEN_CLK ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_DAC,MOSI_DAC} 	   = ~SEN_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_ADC,MOSI_ADC} 	   = ~SEN_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DB,MOSI_TX_DB}    = ~SEN_TX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DAC,MOSI_TX_DAC}  = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_ADC,MOSI_TX_ADC}  = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DB,MOSI_RX_DB}    = ~SEN_RX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DAC,MOSI_RX_DAC}  = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_ADC,MOSI_RX_ADC}  = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0;
+   
+   assign 	miso 			   = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) |
+					     (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) |
+					     (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC);
+   
+   wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0] 	GMII_TXD_unreg;
+   wire 	GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+	GMII_TX_EN <= GMII_TX_EN_unreg;
+	GMII_TX_ER <= GMII_TX_ER_unreg;
+	GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_gmii_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+	ser_tklsb <= ser_tklsb_unreg;
+	ser_tkmsb <= ser_tkmsb_unreg;
+	ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg 	      ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+	ser_r_int <= ser_r;
+	ser_rklsb_int <= ser_rklsb;
+	ser_rkmsb_int <= ser_rkmsb;
+     end
+   
+   u2_core u2_core(.dsp_clk           (dsp_clk),
+		     .wb_clk            (wb_clk),
+		     .clock_ready       (clock_ready),
+		     .clk_to_mac	(clk_to_mac),
+		     .pps_in		(pps_in),
+		     .leds		(leds_int),
+		     .debug		(debug[31:0]),
+		     .debug_clk		(debug_clk[1:0]),
+		     .exp_pps_in	(exp_time_in),
+		     .exp_pps_out	(exp_time_out),
+		     .GMII_COL		(GMII_COL),
+		     .GMII_CRS		(GMII_CRS),
+		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
+		     .GMII_TX_EN	(GMII_TX_EN_unreg),
+		     .GMII_TX_ER	(GMII_TX_ER_unreg),
+		     .GMII_GTX_CLK	(GMII_GTX_CLK_int),
+		     .GMII_TX_CLK	(GMII_TX_CLK),
+		     .GMII_RXD		(GMII_RXD[7:0]),
+		     .GMII_RX_CLK	(GMII_RX_CLK),
+		     .GMII_RX_DV	(GMII_RX_DV),
+		     .GMII_RX_ER	(GMII_RX_ER),
+		     .MDIO		(MDIO),
+		     .MDC		(MDC),
+		     .PHY_INTn		(PHY_INTn),
+		     .PHY_RESETn	(PHY_RESETn),
+		     .ser_enable	(ser_enable),
+		     .ser_prbsen	(ser_prbsen),
+		     .ser_loopen	(ser_loopen),
+		     .ser_rx_en		(ser_rx_en),
+		     .ser_tx_clk	(ser_tx_clk_int),
+		     .ser_t		(ser_t_unreg[15:0]),
+		     .ser_tklsb		(ser_tklsb_unreg),
+		     .ser_tkmsb		(ser_tkmsb_unreg),
+		     .ser_rx_clk	(ser_rx_clk),
+		     .ser_r		(ser_r_int[15:0]),
+		     .ser_rklsb		(ser_rklsb_int),
+		     .ser_rkmsb		(ser_rkmsb_int),
+		     .cpld_start        (cpld_start),
+		     .cpld_mode         (cpld_mode),
+		     .cpld_done         (cpld_done),
+		     .cpld_din          (cpld_din),
+		     .cpld_clk          (cpld_clk),
+		     .cpld_detached     (cpld_detached),
+		     .adc_a		(adc_a[13:0]),
+		     .adc_ovf_a		(adc_ovf_a),
+		     .adc_on_a		(adc_on_a),
+		     .adc_oe_a		(adc_oe_a),
+		     .adc_b		(adc_b[13:0]),
+		     .adc_ovf_b		(adc_ovf_b),
+		     .adc_on_b		(adc_on_b),
+		     .adc_oe_b		(adc_oe_b),
+		     .dac_a		(DACA[15:0]),
+		     .dac_b		(DACB[15:0]),
+		     .scl_pad_i		(scl_pad_i),
+		     .scl_pad_o		(scl_pad_o),
+		     .scl_pad_oen_o	(scl_pad_oen_o),
+		     .sda_pad_i		(sda_pad_i),
+		     .sda_pad_o		(sda_pad_o),
+		     .sda_pad_oen_o	(sda_pad_oen_o),
+		     .clk_en		(clk_en[1:0]),
+		     .clk_sel		(clk_sel[1:0]),
+		     .clk_func		(clk_func),
+		     .clk_status	(clk_status),
+		     .sclk		(sclk_int),
+		     .mosi		(mosi),
+		     .miso		(miso),
+		     .sen_clk		(sen_clk),
+		     .sen_dac		(sen_dac),
+		     .sen_tx_db		(sen_tx_db),
+		     .sen_tx_adc	(sen_tx_adc),
+		     .sen_tx_dac	(sen_tx_dac),
+		     .sen_rx_db		(sen_rx_db),
+		     .sen_rx_adc	(sen_rx_adc),
+		     .sen_rx_dac	(sen_rx_dac),
+		     .io_tx		(io_tx[15:0]),
+		     .io_rx		(io_rx[15:0]),
+		     .RAM_D             (RAM_D),
+		     .RAM_A             (RAM_A),
+		     .RAM_CE1n          (RAM_CE1n),
+		     .RAM_CENn          (RAM_CENn),
+		     .RAM_CLK           (RAM_CLK),
+		     .RAM_WEn           (RAM_WEn),
+		     .RAM_OEn           (RAM_OEn),
+		     .RAM_LDn           (RAM_LDn), 
+		     .uart_tx_o         (uart_tx_o),
+		     .uart_rx_i         (uart_rx_i),
+		     .uart_baud_o       (),
+		     .sim_mode          (1'b0),
+		     .clock_divider     (2)
+		     );
+*/   
+endmodule // safe_u2plus
diff --git a/usrp2/top/safe_u2plus/u2plus.ucf b/usrp2/top/safe_u2plus/u2plus.ucf
new file mode 100755
index 000000000..0a9460d86
--- /dev/null
+++ b/usrp2/top/safe_u2plus/u2plus.ucf
@@ -0,0 +1,401 @@
+## Main 100 MHz Clock
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+
+## ADC
+#NET "ADC_clkout_p"  LOC = "P1"  ;
+#NET "ADC_clkout_n"  LOC = "P2"  ;
+#NET "ADCA_12_p"  LOC = "Y1"  ;
+#NET "ADCA_12_n"  LOC = "Y2"  ;
+#NET "ADCA_10_p"  LOC = "W3"  ;
+#NET "ADCA_10_n"  LOC = "W4"  ;
+#NET "ADCA_8_p"  LOC = "T7"  ;
+#NET "ADCA_8_n"  LOC = "U6"  ;
+#NET "ADCA_6_p"  LOC = "U5"  ;
+#NET "ADCA_6_n"  LOC = "V5"  ;
+#NET "ADCA_4_p"  LOC = "T10"  ;
+#NET "ADCA_4_n"  LOC = "T9"  ;
+#NET "ADCA_2_p"  LOC = "V1"  ;
+#NET "ADCA_2_n"  LOC = "V2"  ;
+#NET "ADCA_0_p"  LOC = "R8"  ;
+#NET "ADCA_0_n"  LOC = "R7"  ;
+#NET "ADCB_2_p"  LOC = "U7"  ;
+#NET "ADCB_2_n"  LOC = "U8"  ;
+#NET "ADCB_0_p"  LOC = "AA2"  ;
+#NET "ADCB_0_n"  LOC = "AA3"  ;
+#NET "ADCB_4_p"  LOC = "AE1"  ;
+#NET "ADCB_4_n"  LOC = "AE2"  ;
+#NET "ADCB_6_p"  LOC = "W1"  ;
+#NET "ADCB_6_n"  LOC = "W2"  ;
+#NET "ADCB_8_p"  LOC = "U3"  ;
+#NET "ADCB_8_n"  LOC = "V4"  ;
+#NET "ADCB_10_p"  LOC = "J1"  ;
+#NET "ADCB_10_n"  LOC = "K1"  ;
+#NET "ADCB_12_p"  LOC = "J3"  ;
+#NET "ADCB_12_n"  LOC = "J2"  ;
+
+## DAC
+#NET "DAC_LOCK"  LOC = "P4"  ;
+#NET "DACA<0>"  LOC = "P8"  ;
+#NET "DACA<1>"  LOC = "P9"  ;
+#NET "DACA<2>"  LOC = "R5"  ;
+#NET "DACA<3>"  LOC = "R6"  ;
+#NET "DACA<4>"  LOC = "P7"  ;
+#NET "DACA<5>"  LOC = "P6"  ;
+#NET "DACA<6>"  LOC = "T3"  ;
+#NET "DACA<7>"  LOC = "T4"  ;
+#NET "DACA<8>"  LOC = "R3"  ;
+#NET "DACA<9>"  LOC = "R4"  ;
+#NET "DACA<10>"  LOC = "R2"  ;
+#NET "DACA<11>"  LOC = "N1"  ;
+#NET "DACA<12>"  LOC = "N2"  ;
+#NET "DACA<13>"  LOC = "N5"  ;
+#NET "DACA<14>"  LOC = "N4"  ;
+#NET "DACA<15>"  LOC = "M2"  ;
+#NET "DACB<0>"  LOC = "M5"  ;
+#NET "DACB<1>"  LOC = "M6"  ;
+#NET "DACB<2>"  LOC = "M4"  ;
+#NET "DACB<3>"  LOC = "M3"  ;
+#NET "DACB<4>"  LOC = "M8"  ;
+#NET "DACB<5>"  LOC = "M7"  ;
+#NET "DACB<6>"  LOC = "L4"  ;
+#NET "DACB<7>"  LOC = "L3"  ;
+#NET "DACB<8>"  LOC = "K3"  ;
+#NET "DACB<9>"  LOC = "K2"  ;
+#NET "DACB<10>"  LOC = "K5"  ;
+#NET "DACB<11>"  LOC = "K4"  ;
+#NET "DACB<12>"  LOC = "M10"  ;
+#NET "DACB<13>"  LOC = "M9"  ;
+#NET "DACB<14>"  LOC = "J5"  ;
+#NET "DACB<15>"  LOC = "J4"  ;
+
+## TX DB GPIO
+#NET "io_tx<15>"  LOC = "K6"  ;
+#NET "io_tx<14>"  LOC = "L7"  ;
+#NET "io_tx<13>"  LOC = "H2"  ;
+#NET "io_tx<12>"  LOC = "H1"  ;
+#NET "io_tx<11>"  LOC = "L10"  ;
+#NET "io_tx<10>"  LOC = "L9"  ;
+#NET "io_tx<9>"  LOC = "G3"  ;
+#NET "io_tx<8>"  LOC = "F3"  ;
+#NET "io_tx<7>"  LOC = "K7"  ;
+#NET "io_tx<6>"  LOC = "J6"  ;
+#NET "io_tx<5>"  LOC = "E1"  ;
+#NET "io_tx<4>"  LOC = "F2"  ;
+#NET "io_tx<3>"  LOC = "J7"  ;
+#NET "io_tx<2>"  LOC = "H6"  ;
+#NET "io_tx<1>"  LOC = "F5"  ;
+#NET "io_tx<0>"  LOC = "G4"  ;
+
+## RX DB GPIO
+#NET "io_rx<15>"  LOC = "AD1"  ;
+#NET "io_rx<14>"  LOC = "AD2"  ;
+#NET "io_rx<13>"  LOC = "AC2"  ;
+#NET "io_rx<12>"  LOC = "AC3"  ;
+#NET "io_rx<11>"  LOC = "W7"  ;
+#NET "io_rx<10>"  LOC = "W6"  ;
+#NET "io_rx<9>"  LOC = "U9"  ;
+#NET "io_rx<8>"  LOC = "V8"  ;
+#NET "io_rx<7>"  LOC = "AB1"  ;
+#NET "io_rx<6>"  LOC = "AC1"  ;
+#NET "io_rx<5>"  LOC = "V7"  ;
+#NET "io_rx<4>"  LOC = "V6"  ;
+#NET "io_rx<3>"  LOC = "Y5"  ;
+#NET "io_rx<2>"  LOC = "R10"  ;
+#NET "io_rx<1>"  LOC = "R1"  ;
+#NET "io_rx<0>"  LOC = "M1"  ;
+
+## MISC
+NET "leds<5>"  LOC = "AF25"  ;
+NET "leds<4>"  LOC = "AE25"  ;
+NET "leds<3>"  LOC = "AF23"  ;
+NET "leds<2>"  LOC = "AE23"  ;
+NET "leds<1>"  LOC = "AB18"  ;
+#NET "FPGA_RESET"  LOC = "K24"  ;
+
+## Debug
+#NET "debug_clk<0>"  LOC = "AA10"  ;
+#NET "debug_clk<1>"  LOC = "AD11"  ;
+#NET "debug<0>"  LOC = "AC19"  ;
+#NET "debug<1>"  LOC = "AF20"  ;
+#NET "debug<2>"  LOC = "AE20"  ;
+#NET "debug<3>"  LOC = "AC16"  ;
+#NET "debug<4>"  LOC = "AB16"  ;
+#NET "debug<5>"  LOC = "AF19"  ;
+#NET "debug<6>"  LOC = "AE19"  ;
+#NET "debug<7>"  LOC = "V15"  ;
+#NET "debug<8>"  LOC = "U15"  ;
+#NET "debug<9>"  LOC = "AE17"  ;
+#NET "debug<10>"  LOC = "AD17"  ;
+#NET "debug<11>"  LOC = "V14"  ;
+#NET "debug<12>"  LOC = "W15"  ;
+#NET "debug<13>"  LOC = "AC15"  ;
+#NET "debug<14>"  LOC = "AD14"  ;
+#NET "debug<15>"  LOC = "AC14"  ;
+#NET "debug<16>"  LOC = "AC11"  ;
+#NET "debug<17>"  LOC = "AB12"  ;
+#NET "debug<18>"  LOC = "AC12"  ;
+#NET "debug<19>"  LOC = "V13"  ;
+#NET "debug<20>"  LOC = "W13"  ;
+#NET "debug<21>"  LOC = "AE8"  ;
+#NET "debug<22>"  LOC = "AF8"  ;
+#NET "debug<23>"  LOC = "V12"  ;
+#NET "debug<24>"  LOC = "W12"  ;
+#NET "debug<25>"  LOC = "AB9"  ;
+#NET "debug<26>"  LOC = "AC9"  ;
+#NET "debug<27>"  LOC = "AC8"  ;
+#NET "debug<28>"  LOC = "AB7"  ;
+#NET "debug<29>"  LOC = "V11"  ;
+#NET "debug<30>"  LOC = "U11"  ;
+#NET "debug<31>"  LOC = "Y10"  ;
+
+## UARTS
+#NET "TXD<3>"  LOC = "AD20"  ;
+#NET "TXD<2>"  LOC = "AC20"  ;
+#NET "TXD<1>"  LOC = "AD19"  ;
+#NET "RXD<3>"  LOC = "AF17"  ;
+#NET "RXD<2>"  LOC = "AF15"  ;
+#NET "RXD<1>"  LOC = "AD12"  ;
+
+## AD9510
+#NET "CLK_STATUS"  LOC = "AD22"  ;
+#NET "CLK_FUNC"  LOC = "AC21"  ;
+#NET "clk_sel<0>"  LOC = "AE21"  ;
+#NET "clk_sel<1>"  LOC = "AD21"  ;
+#NET "clk_en<1>"  LOC = "AA17"  ;
+#NET "clk_en<0>"  LOC = "Y17"  ;
+
+## I2C
+#NET "SDA"  LOC = "V16"  ;
+#NET "SCL"  LOC = "U16"  ;
+
+## Timing
+#NET "PPS_IN"  LOC = "AB6"  ;
+#NET "PPS2_IN"  LOC = "AA20"  ;
+
+## SPI
+#NET "SEN_CLK"  LOC = "AA18"  ;
+#NET "MOSI_CLK"  LOC = "W17"  ;
+#NET "SCLK_CLK"  LOC = "V17"  ;
+#NET "MISO_CLK"  LOC = "AC10"  ;
+
+#NET "SEN_DAC"  LOC = "AE7"  ;
+#NET "SCLK_DAC"  LOC = "AF5"  ;
+#NET "MOSI_DAC"  LOC = "AE6"  ;
+#NET "MISO_DAC"  LOC = "Y3"  ;
+
+#NET "SCLK_ADC"  LOC = "B1"  ;
+#NET "MOSI_ADC"  LOC = "J8"  ;
+#NET "SEN_ADC"  LOC = "J9"  ;
+
+#NET "MOSI_TX_ADC"  LOC = "V10"  ;
+#NET "SEN_TX_ADC"  LOC = "W10"  ;
+#NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+#NET "MISO_TX_ADC"  LOC = "G1"  ;
+
+#NET "MOSI_TX_DAC"  LOC = "AD6"  ;
+#NET "SEN_TX_DAC"  LOC = "AE4"  ;
+#NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+
+#NET "SCLK_TX_DB"  LOC = "AE3"  ;
+#NET "MOSI_TX_DB"  LOC = "AF3"  ;
+#NET "SEN_TX_DB"  LOC = "W9"  ;
+#NET "MISO_TX_DB"  LOC = "AA5"  ;
+
+#NET "MOSI_RX_ADC"  LOC = "E3"  ;
+#NET "SCLK_RX_ADC"  LOC = "F4"  ;
+#NET "SEN_RX_ADC"  LOC = "D3"  ;
+#NET "MISO_RX_ADC"  LOC = "C1"  ;
+
+#NET "SCLK_RX_DAC"  LOC = "E4"  ;
+#NET "SEN_RX_DAC"  LOC = "K9"  ;
+#NET "MOSI_RX_DAC"  LOC = "K8"  ;
+
+#NET "SCLK_RX_DB"  LOC = "G6"  ;
+#NET "MOSI_RX_DB"  LOC = "H7"  ;
+#NET "SEN_RX_DB"  LOC = "B2"  ;
+#NET "MISO_RX_DB"  LOC = "H4"  ;
+
+## ETH PHY
+#NET "CLK_TO_MAC"  LOC = "P26"  ;
+
+#NET "GMII_TXD<7>"  LOC = "G21"  ;
+#NET "GMII_TXD<6>"  LOC = "C26"  ;
+#NET "GMII_TXD<5>"  LOC = "C25"  ;
+#NET "GMII_TXD<4>"  LOC = "J21"  ;
+#NET "GMII_TXD<3>"  LOC = "H21"  ;
+#NET "GMII_TXD<2>"  LOC = "D25"  ;
+#NET "GMII_TXD<1>"  LOC = "D24"  ;
+#NET "GMII_TXD<0>"  LOC = "E26"  ;
+#NET "GMII_TX_EN"  LOC = "D26"  ;
+#NET "GMII_TX_ER"  LOC = "J19"  ;
+#NET "GMII_GTX_CLK"  LOC = "J20"  ;
+#NET "GMII_TX_CLK"  LOC = "P25"  ;
+
+#NET "GMII_RX_CLK"  LOC = "P21"  ;
+#NET "GMII_RXD<7>"  LOC = "G22"  ;
+#NET "GMII_RXD<6>"  LOC = "K19"  ;
+#NET "GMII_RXD<5>"  LOC = "K18"  ;
+#NET "GMII_RXD<4>"  LOC = "E24"  ;
+#NET "GMII_RXD<3>"  LOC = "F23"  ;
+#NET "GMII_RXD<2>"  LOC = "L18"  ;
+#NET "GMII_RXD<1>"  LOC = "L17"  ;
+#NET "GMII_RXD<0>"  LOC = "F25"  ;
+#NET "GMII_RX_DV"  LOC = "F24"  ;
+#NET "GMII_RX_ER"  LOC = "L20"  ;
+#NET "GMII_CRS"  LOC = "K20"  ;
+#NET "GMII_COL"  LOC = "G23"  ;
+
+#NET "PHY_INTn"  LOC = "L22"  ;
+#NET "MDIO"  LOC = "K21"  ;
+#NET "MDC"  LOC = "J23"  ;
+#NET "PHY_RESETn"  LOC = "J22"  ;
+NET "ETH_LED"  LOC = "H20"  ;
+
+## MIMO Interface
+#NET "exp_time_out_p"  LOC = "Y14"  ;
+#NET "exp_time_out_n"  LOC = "AA14"  ;
+#NET "exp_time_in_p"  LOC = "N18"  ;
+#NET "exp_time_in_n"  LOC = "N17"  ;
+#NET "exp_user_out_p"  LOC = "AF14"  ;
+#NET "exp_user_out_n"  LOC = "AE14"  ;
+#NET "exp_user_in_p"  LOC = "L24"  ;
+#NET "exp_user_in_n"  LOC = "M23"  ;
+
+## SERDES
+#NET "ser_enable"  LOC = "R20"  ;
+#NET "ser_prbsen"  LOC = "U23"  ;
+#NET "ser_loopen"  LOC = "R19"  ;
+#NET "ser_rx_en"  LOC = "Y21"  ;
+#NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+#NET "ser_t<15>"  LOC = "V23"  ;
+#NET "ser_t<14>"  LOC = "U22"  ;
+#NET "ser_t<13>"  LOC = "V24"  ;
+#NET "ser_t<12>"  LOC = "V25"  ;
+#NET "ser_t<11>"  LOC = "W23"  ;
+#NET "ser_t<10>"  LOC = "V22"  ;
+#NET "ser_t<9>"  LOC = "T18"  ;
+#NET "ser_t<8>"  LOC = "T17"  ;
+#NET "ser_t<7>"  LOC = "Y24"  ;
+#NET "ser_t<6>"  LOC = "Y25"  ;
+#NET "ser_t<5>"  LOC = "U21"  ;
+#NET "ser_t<4>"  LOC = "T20"  ;
+#NET "ser_t<3>"  LOC = "Y22"  ;
+#NET "ser_t<2>"  LOC = "Y23"  ;
+#NET "ser_t<1>"  LOC = "U19"  ;
+#NET "ser_t<0>"  LOC = "U18"  ;
+#NET "ser_tkmsb"  LOC = "AA24"  ;
+#NET "ser_tklsb"  LOC = "AA25"  ;
+#NET "ser_rx_clk"  LOC = "P18"  ;
+#NET "ser_r<15>"  LOC = "V21"  ;
+#NET "ser_r<14>"  LOC = "U20"  ;
+#NET "ser_r<13>"  LOC = "AA22"  ;
+#NET "ser_r<12>"  LOC = "AA23"  ;
+#NET "ser_r<11>"  LOC = "V18"  ;
+#NET "ser_r<10>"  LOC = "V19"  ;
+#NET "ser_r<9>"  LOC = "AB23"  ;
+#NET "ser_r<8>"  LOC = "AC26"  ;
+#NET "ser_r<7>"  LOC = "AB26"  ;
+#NET "ser_r<6>"  LOC = "AD26"  ;
+#NET "ser_r<5>"  LOC = "AC25"  ;
+#NET "ser_r<4>"  LOC = "W20"  ;
+#NET "ser_r<3>"  LOC = "W21"  ;
+#NET "ser_r<2>"  LOC = "AC23"  ;
+#NET "ser_r<1>"  LOC = "AC24"  ;
+#NET "ser_r<0>"  LOC = "AE26"  ;
+#NET "ser_rkmsb"  LOC = "AD25"  ;
+#NET "ser_rklsb"  LOC = "Y20"  ;
+
+## SRAM
+#NET "RAM_D<35>"  LOC = "K16"  ;
+#NET "RAM_D<34>"  LOC = "D20"  ;
+#NET "RAM_D<33>"  LOC = "C20"  ;
+#NET "RAM_D<32>"  LOC = "E21"  ;
+#NET "RAM_D<31>"  LOC = "D21"  ;
+#NET "RAM_D<30>"  LOC = "C21"  ;
+#NET "RAM_D<29>"  LOC = "B21"  ;
+#NET "RAM_D<28>"  LOC = "H17"  ;
+#NET "RAM_D<27>"  LOC = "G17"  ;
+#NET "RAM_D<26>"  LOC = "B23"  ;
+#NET "RAM_D<25>"  LOC = "A22"  ;
+#NET "RAM_D<24>"  LOC = "D23"  ;
+#NET "RAM_D<23>"  LOC = "C23"  ;
+#NET "RAM_D<22>"  LOC = "D22"  ;
+#NET "RAM_D<21>"  LOC = "C22"  ;
+#NET "RAM_D<20>"  LOC = "F19"  ;
+#NET "RAM_D<19>"  LOC = "G20"  ;
+#NET "RAM_D<18>"  LOC = "F20"  ;
+#NET "RAM_D<17>"  LOC = "F7"  ;
+#NET "RAM_D<16>"  LOC = "E7"  ;
+#NET "RAM_D<15>"  LOC = "G9"  ;
+#NET "RAM_D<14>"  LOC = "H9"  ;
+#NET "RAM_D<13>"  LOC = "G10"  ;
+#NET "RAM_D<12>"  LOC = "H10"  ;
+#NET "RAM_D<11>"  LOC = "A4"  ;
+#NET "RAM_D<10>"  LOC = "B4"  ;
+#NET "RAM_D<9>"  LOC = "C5"  ;
+#NET "RAM_D<8>"  LOC = "D6"  ;
+#NET "RAM_D<7>"  LOC = "J11"  ;
+#NET "RAM_D<6>"  LOC = "K11"  ;
+#NET "RAM_D<5>"  LOC = "B7"  ;
+#NET "RAM_D<4>"  LOC = "C7"  ;
+#NET "RAM_D<3>"  LOC = "B6"  ;
+#NET "RAM_D<2>"  LOC = "C6"  ;
+#NET "RAM_D<1>"  LOC = "C8"  ;
+#NET "RAM_D<0>"  LOC = "D8"  ;
+#NET "RAM_A<0>"  LOC = "C11"  ;
+#NET "RAM_A<1>"  LOC = "E12"  ;
+#NET "RAM_A<2>"  LOC = "F12"  ;
+#NET "RAM_A<3>"  LOC = "D13"  ;
+#NET "RAM_A<4>"  LOC = "C12"  ;
+#NET "RAM_A<5>"  LOC = "A12"  ;
+#NET "RAM_A<6>"  LOC = "B12"  ;
+#NET "RAM_A<7>"  LOC = "E14"  ;
+#NET "RAM_A<8>"  LOC = "F14"  ;
+#NET "RAM_A<9>"  LOC = "B15"  ;
+#NET "RAM_A<10>"  LOC = "A15"  ;
+#NET "RAM_A<11>"  LOC = "D16"  ;
+#NET "RAM_A<12>"  LOC = "C15"  ;
+#NET "RAM_A<13>"  LOC = "D17"  ;
+#NET "RAM_A<14>"  LOC = "C16"  ;
+#NET "RAM_A<15>"  LOC = "F15"  ;
+#NET "RAM_A<16>"  LOC = "C17"  ;
+#NET "RAM_A<17>"  LOC = "B17"  ;
+#NET "RAM_A<18>"  LOC = "B18"  ;
+#NET "RAM_A<19>"  LOC = "A18"  ;
+#NET "RAM_A<20>"  LOC = "D18"  ;
+#NET "RAM_BWn<3>"  LOC = "D9"  ;
+#NET "RAM_BWn<2>"  LOC = "A9"  ;
+#NET "RAM_BWn<1>"  LOC = "B9"  ;
+#NET "RAM_BWn<0>"  LOC = "G12"  ;
+#NET "RAM_ZZ"  LOC = "J12"  ;
+#NET "RAM_LDn"  LOC = "H12"  ;
+#NET "RAM_OEn"  LOC = "C10"  ;
+#NET "RAM_WEn"  LOC = "D10"  ;
+#NET "RAM_CENn"  LOC = "B10"  ;
+#NET "RAM_CLK"  LOC = "A10"  ;
+
+## SPI Flash
+#NET "flash_miso"  LOC = "AF24"  ;
+#NET "flash_clk"  LOC = "AE24"  ;
+#NET "flash_mosi"  LOC = "AB15"  ;
+#NET "flash_cs"  LOC = "AA7"  ;
+
+## MISC FPGA, unused for now
+##NET "PROG_B"  LOC = "A2"  ;
+##NET "PUDC_B"  LOC = "G8"  ;
+##NET "DONE"  LOC = "AB21"  ;
+##NET "INIT_B"  LOC = "AA15"  ;
+
+
+##NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
+##NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
+##NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
+##NET "unnamed_net16"  LOC = "Y7"  ;     # M2
+##NET "unnamed_net15"  LOC = "AC4"  ;    # M1
+##NET "unnamed_net14"  LOC = "AD4"  ;    # M0
+##NET "unnamed_net13"  LOC = "D4"  ;     # TMS
+##NET "unnamed_net12"  LOC = "E23"  ;    # TDO
+##NET "unnamed_net11"  LOC = "G7"  ;     # TDI
+##NET "unnamed_net10"  LOC = "A25"  ;    # TCK
+##NET "unnamed_net20"  LOC = "V20"  ;    # SUSPEND
diff --git a/usrp2/top/u2plus/.gitignore b/usrp2/top/u2plus/.gitignore
new file mode 100644
index 000000000..1b2211df0
--- /dev/null
+++ b/usrp2/top/u2plus/.gitignore
@@ -0,0 +1 @@
+build*
diff --git a/usrp2/top/u2plus/Makefile b/usrp2/top/u2plus/Makefile
new file mode 100644
index 000000000..305b5b9e3
--- /dev/null
+++ b/usrp2/top/u2plus/Makefile
@@ -0,0 +1,246 @@
+#
+# Copyright 2008 Ettus Research LLC
+# 
+# This file is part of GNU Radio
+# 
+# GNU Radio is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3, or (at your option)
+# any later version.
+# 
+# GNU Radio is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+# 
+# You should have received a copy of the GNU General Public License
+# along with GNU Radio; see the file COPYING.  If not, write to
+# the Free Software Foundation, Inc., 51 Franklin Street,
+# Boston, MA 02110-1301, USA.
+# 
+
+##################################################
+# xtclsh Shell and tcl Script Path
+##################################################
+#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
+XTCLSH := xtclsh
+ISE_HELPER := ../tcl/ise_helper.tcl
+
+##################################################
+# Project Setup
+##################################################
+BUILD_DIR := build/
+export TOP_MODULE := u2plus
+export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+##################################################
+# Project Properties
+##################################################
+export PROJECT_PROPERTIES := \
+family "Spartan-3A DSP" \
+device xc3sd3400a \
+package fg676 \
+speed -5 \
+top_level_module_type "HDL" \
+synthesis_tool "XST (VHDL/Verilog)" \
+simulator "ISE Simulator (VHDL/Verilog)" \
+"Preferred Language" "Verilog" \
+"Enable Message Filtering" FALSE \
+"Display Incremental Messages" FALSE 
+
+##################################################
+# Sources
+##################################################
+export SOURCE_ROOT := ../../../
+export SOURCES := \
+control_lib/CRC16_D16.v \
+control_lib/atr_controller.v \
+control_lib/bin2gray.v \
+control_lib/dcache.v \
+control_lib/decoder_3_8.v \
+control_lib/dpram32.v \
+control_lib/gray2bin.v \
+control_lib/gray_send.v \
+control_lib/icache.v \
+control_lib/mux4.v \
+control_lib/mux8.v \
+control_lib/nsgpio.v \
+control_lib/ram_2port.v \
+control_lib/ram_harv_cache.v \
+control_lib/ram_loader.v \
+control_lib/setting_reg.v \
+control_lib/settings_bus.v \
+control_lib/srl.v \
+control_lib/system_control.v \
+control_lib/wb_1master.v \
+control_lib/wb_readback_mux.v \
+control_lib/simple_uart.v \
+control_lib/simple_uart_tx.v \
+control_lib/simple_uart_rx.v \
+control_lib/oneshot_2clk.v \
+control_lib/sd_spi.v \
+control_lib/sd_spi_wb.v \
+control_lib/wb_bridge_16_32.v \
+control_lib/reset_sync.v \
+simple_gemac/simple_gemac_wrapper.v \
+simple_gemac/simple_gemac.v \
+simple_gemac/simple_gemac_wb.v \
+simple_gemac/simple_gemac_tx.v \
+simple_gemac/simple_gemac_rx.v \
+simple_gemac/crc.v \
+simple_gemac/delay_line.v \
+simple_gemac/flow_ctrl_tx.v \
+simple_gemac/flow_ctrl_rx.v \
+simple_gemac/address_filter.v \
+simple_gemac/ll8_to_txmac.v \
+simple_gemac/rxmac_to_ll8.v \
+simple_gemac/miim/eth_miim.v \
+simple_gemac/miim/eth_clockgen.v \
+simple_gemac/miim/eth_outputcontrol.v \
+simple_gemac/miim/eth_shiftreg.v \
+control_lib/newfifo/buffer_int.v \
+control_lib/newfifo/buffer_pool.v \
+control_lib/newfifo/fifo_2clock.v \
+control_lib/newfifo/fifo_2clock_cascade.v \
+control_lib/newfifo/ll8_shortfifo.v \
+control_lib/newfifo/ll8_to_fifo36.v \
+control_lib/newfifo/fifo_short.v \
+control_lib/newfifo/fifo_long.v \
+control_lib/newfifo/fifo_cascade.v \
+control_lib/newfifo/fifo36_to_ll8.v \
+control_lib/longfifo.v \
+control_lib/shortfifo.v \
+control_lib/medfifo.v \
+coregen/fifo_xlnx_2Kx36_2clk.v \
+coregen/fifo_xlnx_2Kx36_2clk.xco \
+coregen/fifo_xlnx_512x36_2clk.v \
+coregen/fifo_xlnx_512x36_2clk.xco \
+coregen/fifo_xlnx_64x36_2clk.v \
+coregen/fifo_xlnx_64x36_2clk.xco \
+extram/wb_zbt16_b.v \
+opencores/8b10b/decode_8b10b.v \
+opencores/8b10b/encode_8b10b.v \
+opencores/aemb/rtl/verilog/aeMB_bpcu.v \
+opencores/aemb/rtl/verilog/aeMB_core_BE.v \
+opencores/aemb/rtl/verilog/aeMB_ctrl.v \
+opencores/aemb/rtl/verilog/aeMB_edk32.v \
+opencores/aemb/rtl/verilog/aeMB_ibuf.v \
+opencores/aemb/rtl/verilog/aeMB_regf.v \
+opencores/aemb/rtl/verilog/aeMB_xecu.v \
+opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+opencores/i2c/rtl/verilog/i2c_master_defines.v \
+opencores/i2c/rtl/verilog/i2c_master_top.v \
+opencores/i2c/rtl/verilog/timescale.v \
+opencores/simple_pic/rtl/simple_pic.v \
+opencores/spi/rtl/verilog/spi_clgen.v \
+opencores/spi/rtl/verilog/spi_defines.v \
+opencores/spi/rtl/verilog/spi_shift.v \
+opencores/spi/rtl/verilog/spi_top.v \
+opencores/spi/rtl/verilog/timescale.v \
+sdr_lib/acc.v \
+sdr_lib/add2.v \
+sdr_lib/add2_and_round.v \
+sdr_lib/add2_and_round_reg.v \
+sdr_lib/add2_reg.v \
+sdr_lib/cic_dec_shifter.v \
+sdr_lib/cic_decim.v \
+sdr_lib/cic_int_shifter.v \
+sdr_lib/cic_interp.v \
+sdr_lib/cic_strober.v \
+sdr_lib/clip.v \
+sdr_lib/clip_reg.v \
+sdr_lib/cordic.v \
+sdr_lib/cordic_z24.v \
+sdr_lib/cordic_stage.v \
+sdr_lib/dsp_core_rx.v \
+sdr_lib/dsp_core_tx.v \
+sdr_lib/hb_dec.v \
+sdr_lib/hb_interp.v \
+sdr_lib/round.v \
+sdr_lib/round_reg.v \
+sdr_lib/rx_control.v \
+sdr_lib/rx_dcoffset.v \
+sdr_lib/sign_extend.v \
+sdr_lib/small_hb_dec.v \
+sdr_lib/small_hb_int.v \
+sdr_lib/tx_control.v \
+serdes/serdes.v \
+serdes/serdes_fc_rx.v \
+serdes/serdes_fc_tx.v \
+serdes/serdes_rx.v \
+serdes/serdes_tx.v \
+timing/time_receiver.v \
+timing/time_sender.v \
+timing/time_sync.v \
+timing/timer.v \
+top/u2_core/u2_core.v \
+top/u2plus/capture_ddrlvds.v \
+top/u2plus/u2plus.ucf \
+top/u2plus/u2plus.v 
+
+##################################################
+# Process Properties
+##################################################
+export SYNTHESIZE_PROPERTIES := \
+"Number of Clock Buffers" 6 \
+"Pack I/O Registers into IOBs" Yes \
+"Optimization Effort" High \
+"Optimize Instantiated Primitives" TRUE \
+"Register Balancing" Yes \
+"Use Clock Enable" Auto \
+"Use Synchronous Reset" Auto \
+"Use Synchronous Set" Auto
+
+export TRANSLATE_PROPERTIES := \
+"Macro Search Path" "$(shell pwd)/../../coregen/"
+
+export MAP_PROPERTIES := \
+"Allow Logic Optimization Across Hierarchy" TRUE \
+"Map to Input Functions" 4 \
+"Optimization Strategy (Cover Mode)" Speed \
+"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
+"Perform Timing-Driven Packing and Placement" TRUE \
+"Map Effort Level" High \
+"Extra Effort" Normal \
+"Combinatorial Logic Optimization" TRUE \
+"Register Duplication" TRUE
+
+export PLACE_ROUTE_PROPERTIES := \
+"Place & Route Effort Level (Overall)" High 
+
+export STATIC_TIMING_PROPERTIES := \
+"Number of Paths in Error/Verbose Report" 10 \
+"Report Type" "Error Report"
+
+export GEN_PROG_FILE_PROPERTIES := \
+"Configuration Rate" 6 \
+"Create Binary Configuration File" TRUE \
+"Done (Output Events)" 5 \
+"Enable Bitstream Compression" TRUE \
+"Enable Outputs (Output Events)" 6 
+
+export SIM_MODEL_PROPERTIES := ""
+
+##################################################
+# Make Options
+##################################################
+all:
+	@echo make proj, check, synth, bin, or clean
+
+proj:
+	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
+
+check:
+	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
+
+synth:
+	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
+
+bin:
+	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
+
+clean:
+	rm -rf $(BUILD_DIR)
+
+
diff --git a/usrp2/top/u2plus/capture_ddrlvds.v b/usrp2/top/u2plus/capture_ddrlvds.v
new file mode 100644
index 000000000..b9f53ff8c
--- /dev/null
+++ b/usrp2/top/u2plus/capture_ddrlvds.v
@@ -0,0 +1,39 @@
+
+
+module capture_ddrlvds
+  #(parameter WIDTH=7)
+   (input clk,
+    input ssclk_p,
+    input ssclk_n,
+    input [WIDTH-1:0] in_p,
+    input [WIDTH-1:0] in_n,
+    output reg [(2*WIDTH)-1:0] out);
+
+   wire [WIDTH-1:0] 	   ddr_dat;
+   wire 		   ssclk_regional;
+   wire 		   ssclk_io;
+   wire 		   ssclk;
+   wire [(2*WIDTH)-1:0]    out_pre1;
+   reg [(2*WIDTH)-1:0] 	   out_pre2;
+   
+   IBUFGDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) clkbuf (.O(ssclk), .I(ssclk_p), .IB(ssclk_n));
+   
+   genvar 	       i;
+   generate
+      for(i = 0; i < WIDTH; i = i + 1)
+	begin : gen_lvds_pins
+	   IBUFDS #(.IOSTANDARD("LVDS_25"),.DIFF_TERM("TRUE")) ibufds 
+	      (.O(ddr_dat[i]), .I(in_p[i]), .IB(in_n[i]) );
+	   IDDR2 #(.DDR_ALIGNMENT("C1")) iddr2
+	     (.Q0(out_pre1[2*i]), .Q1(out_pre1[(2*i)+1]), .C0(ssclk), .C1(~ssclk),
+	      .CE(1'b1), .D(ddr_dat[i]), .R(1'b0), .S(1'b0));
+	end
+   endgenerate
+
+   always @(negedge clk)
+     out_pre2 <= out_pre1;
+
+   always @(posedge clk)
+     out      <= out_pre2;
+   
+endmodule // capture_ddrlvds
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 091eb2005..31404dda9 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -1,157 +1,137 @@
-NET "DAC_LOCK"  LOC = "P4"  ;
+## Main 100 MHz Clock
+NET "CLK_FPGA_P"  LOC = "AA13"  ;
+NET "CLK_FPGA_N"  LOC = "Y13"  ;
+
+## ADC
 NET "ADC_clkout_p"  LOC = "P1"  ;
 NET "ADC_clkout_n"  LOC = "P2"  ;
-NET "io_rx<15>"  LOC = "AD1"  ;
-NET "io_rx<14>"  LOC = "AD2"  ;
-NET "io_rx<13>"  LOC = "AC2"  ;
-NET "io_rx<12>"  LOC = "AC3"  ;
-NET "io_rx<11>"  LOC = "W7"  ;
-NET "io_rx<10>"  LOC = "W6"  ;
-NET "io_rx<09>"  LOC = "U9"  ;
-NET "io_rx<08>"  LOC = "V8"  ;
-NET "io_rx<07>"  LOC = "AB1"  ;
-NET "io_rx<06>"  LOC = "AC1"  ;
-NET "io_rx<05>"  LOC = "V7"  ;
-NET "io_rx<04>"  LOC = "V6"  ;
-NET "io_rx<03>"  LOC = "Y5"  ;
-NET "ADCB_2_3_p"  LOC = "U7"  ;
-NET "ADCB_2_3_n"  LOC = "U8"  ;
-NET "ADCB_0_1_p"  LOC = "AA2"  ;
-NET "ADCB_0_1_n"  LOC = "AA3"  ;
-NET "ADCA_12_13_p"  LOC = "Y1"  ;
-NET "ADCA_12_13_n"  LOC = "Y2"  ;
-NET "ADCA_10_11_p"  LOC = "W3"  ;
-NET "ADCA_10_11_n"  LOC = "W4"  ;
-NET "ADCA_8_9_p"  LOC = "T7"  ;
-NET "ADCA_8_9_n"  LOC = "U6"  ;
-NET "ADCA_6_7_p"  LOC = "U5"  ;
-NET "ADCA_6_7_n"  LOC = "V5"  ;
-NET "ADCA_4_5_p"  LOC = "T10"  ;
-NET "ADCA_4_5_n"  LOC = "T9"  ;
-NET "ADCA_2_3_p"  LOC = "V1"  ;
-NET "ADCA_2_3_n"  LOC = "V2"  ;
-NET "ADCA_0_1_p"  LOC = "R8"  ;
-NET "ADCA_0_1_n"  LOC = "R7"  ;
-NET "TX00_A"  LOC = "P8"  ;
-NET "TX01_A"  LOC = "P9"  ;
-NET "TX02_A"  LOC = "R5"  ;
-NET "TX03_A"  LOC = "R6"  ;
-NET "TX04_A"  LOC = "P7"  ;
-NET "TX05_A"  LOC = "P6"  ;
-NET "TX06_A"  LOC = "T3"  ;
-NET "TX07_A"  LOC = "T4"  ;
-NET "TX08_A"  LOC = "R3"  ;
-NET "TX09_A"  LOC = "R4"  ;
-NET "TX10_A"  LOC = "R2"  ;
-NET "TX11_A"  LOC = "N1"  ;
-NET "TX12_A"  LOC = "N2"  ;
-NET "TX13_A"  LOC = "N5"  ;
-NET "TX14_A"  LOC = "N4"  ;
-NET "TX15_A"  LOC = "M2"  ;
-NET "TX00_B"  LOC = "M5"  ;
-NET "TX01_B"  LOC = "M6"  ;
-NET "TX02_B"  LOC = "M4"  ;
-NET "TX03_B"  LOC = "M3"  ;
-NET "TX04_B"  LOC = "M8"  ;
-NET "TX05_B"  LOC = "M7"  ;
-NET "TX06_B"  LOC = "L4"  ;
-NET "TX07_B"  LOC = "L3"  ;
-NET "TX08_B"  LOC = "K3"  ;
-NET "TX09_B"  LOC = "K2"  ;
-NET "TX10_B"  LOC = "K5"  ;
-NET "TX11_B"  LOC = "K4"  ;
-NET "TX12_B"  LOC = "M10"  ;
-NET "TX13_B"  LOC = "M9"  ;
-NET "TX14_B"  LOC = "J5"  ;
-NET "TX15_B"  LOC = "J4"  ;
+NET "ADCA_12_p"  LOC = "Y1"  ;
+NET "ADCA_12_n"  LOC = "Y2"  ;
+NET "ADCA_10_p"  LOC = "W3"  ;
+NET "ADCA_10_n"  LOC = "W4"  ;
+NET "ADCA_8_p"  LOC = "T7"  ;
+NET "ADCA_8_n"  LOC = "U6"  ;
+NET "ADCA_6_p"  LOC = "U5"  ;
+NET "ADCA_6_n"  LOC = "V5"  ;
+NET "ADCA_4_p"  LOC = "T10"  ;
+NET "ADCA_4_n"  LOC = "T9"  ;
+NET "ADCA_2_p"  LOC = "V1"  ;
+NET "ADCA_2_n"  LOC = "V2"  ;
+NET "ADCA_0_p"  LOC = "R8"  ;
+NET "ADCA_0_n"  LOC = "R7"  ;
+NET "ADCB_2_p"  LOC = "U7"  ;
+NET "ADCB_2_n"  LOC = "U8"  ;
+NET "ADCB_0_p"  LOC = "AA2"  ;
+NET "ADCB_0_n"  LOC = "AA3"  ;
+NET "ADCB_4_p"  LOC = "AE1"  ;
+NET "ADCB_4_n"  LOC = "AE2"  ;
+NET "ADCB_6_p"  LOC = "W1"  ;
+NET "ADCB_6_n"  LOC = "W2"  ;
+NET "ADCB_8_p"  LOC = "U3"  ;
+NET "ADCB_8_n"  LOC = "V4"  ;
+NET "ADCB_10_p"  LOC = "J1"  ;
+NET "ADCB_10_n"  LOC = "K1"  ;
+NET "ADCB_12_p"  LOC = "J3"  ;
+NET "ADCB_12_n"  LOC = "J2"  ;
+
+## DAC
+NET "DAC_LOCK"  LOC = "P4"  ;
+NET "DACA<0>"  LOC = "P8"  ;
+NET "DACA<1>"  LOC = "P9"  ;
+NET "DACA<2>"  LOC = "R5"  ;
+NET "DACA<3>"  LOC = "R6"  ;
+NET "DACA<4>"  LOC = "P7"  ;
+NET "DACA<5>"  LOC = "P6"  ;
+NET "DACA<6>"  LOC = "T3"  ;
+NET "DACA<7>"  LOC = "T4"  ;
+NET "DACA<8>"  LOC = "R3"  ;
+NET "DACA<9>"  LOC = "R4"  ;
+NET "DACA<10>"  LOC = "R2"  ;
+NET "DACA<11>"  LOC = "N1"  ;
+NET "DACA<12>"  LOC = "N2"  ;
+NET "DACA<13>"  LOC = "N5"  ;
+NET "DACA<14>"  LOC = "N4"  ;
+NET "DACA<15>"  LOC = "M2"  ;
+NET "DACB<0>"  LOC = "M5"  ;
+NET "DACB<1>"  LOC = "M6"  ;
+NET "DACB<2>"  LOC = "M4"  ;
+NET "DACB<3>"  LOC = "M3"  ;
+NET "DACB<4>"  LOC = "M8"  ;
+NET "DACB<5>"  LOC = "M7"  ;
+NET "DACB<6>"  LOC = "L4"  ;
+NET "DACB<7>"  LOC = "L3"  ;
+NET "DACB<8>"  LOC = "K3"  ;
+NET "DACB<9>"  LOC = "K2"  ;
+NET "DACB<10>"  LOC = "K5"  ;
+NET "DACB<11>"  LOC = "K4"  ;
+NET "DACB<12>"  LOC = "M10"  ;
+NET "DACB<13>"  LOC = "M9"  ;
+NET "DACB<14>"  LOC = "J5"  ;
+NET "DACB<15>"  LOC = "J4"  ;
+
+## TX DB GPIO
 NET "io_tx<15>"  LOC = "K6"  ;
 NET "io_tx<14>"  LOC = "L7"  ;
 NET "io_tx<13>"  LOC = "H2"  ;
 NET "io_tx<12>"  LOC = "H1"  ;
 NET "io_tx<11>"  LOC = "L10"  ;
 NET "io_tx<10>"  LOC = "L9"  ;
-NET "io_tx<09>"  LOC = "G3"  ;
-NET "io_tx<08>"  LOC = "F3"  ;
-NET "io_tx<07>"  LOC = "K7"  ;
-NET "io_tx<06>"  LOC = "J6"  ;
-NET "io_tx<05>"  LOC = "E1"  ;
-NET "io_tx<04>"  LOC = "F2"  ;
-NET "io_tx<03>"  LOC = "J7"  ;
-NET "io_tx<02>"  LOC = "H6"  ;
-NET "io_tx<01>"  LOC = "F5"  ;
-NET "io_tx<00>"  LOC = "G4"  ;
-NET "MOSI_RX_ADC"  LOC = "E3"  ;
-NET "SCLK_RX_ADC"  LOC = "F4"  ;
-NET "SEN_RX_ADC"  LOC = "D3"  ;
-NET "SCLK_RX_DAC"  LOC = "E4"  ;
-NET "SEN_RX_DAC"  LOC = "K9"  ;
-NET "MOSI_RX_DAC"  LOC = "K8"  ;
-NET "SCLK_RX_DB"  LOC = "G6"  ;
-NET "MOSI_RX_DB"  LOC = "H7"  ;
-NET "SEN_RX_DB"  LOC = "B2"  ;
-NET "SCLK_ADC"  LOC = "B1"  ;
-NET "MOSI_ADC"  LOC = "J8"  ;
-NET "SEN_ADC"  LOC = "J9"  ;
-NET "ADCB_4_5_p"  LOC = "AE1"  ;
-NET "ADCB_4_5_n"  LOC = "AE2"  ;
-NET "ADCB_6_7_p"  LOC = "W1"  ;
-NET "ADCB_6_7_n"  LOC = "W2"  ;
-NET "ADCB_8_9_p"  LOC = "U3"  ;
-NET "ADCB_8_9_n"  LOC = "V4"  ;
-NET "ADCB_10_11_p"  LOC = "J1"  ;
-NET "ADCB_10_11_n"  LOC = "K1"  ;
-NET "ADCB_12_13_p"  LOC = "J3"  ;
-NET "ADCB_12_13_n"  LOC = "J2"  ;
-NET "MISO_RX_DB"  LOC = "H4"  ;
-NET "MISO_RX_ADC"  LOC = "C1"  ;
-NET "MISO_TX_DB"  LOC = "AA5"  ;
-NET "MISO_DAC"  LOC = "Y3"  ;
-NET "MISO_TX_ADC"  LOC = "G1"  ;
-NET "io_rx<02>"  LOC = "R10"  ;
-NET "io_rx<01>"  LOC = "R1"  ;
-NET "io_rx<00>"  LOC = "M1"  ;
-NET "exp_user_out_p"  LOC = "AF14"  ;
-NET "exp_user_out_n"  LOC = "AE14"  ;
-NET "exp_time_out_p"  LOC = "Y14"  ;
-NET "exp_time_out_n"  LOC = "AA14"  ;
-NET "CLK_FPGA_P"  LOC = "AA13"  ;
-NET "CLK_FPGA_N"  LOC = "Y13"  ;
+NET "io_tx<9>"  LOC = "G3"  ;
+NET "io_tx<8>"  LOC = "F3"  ;
+NET "io_tx<7>"  LOC = "K7"  ;
+NET "io_tx<6>"  LOC = "J6"  ;
+NET "io_tx<5>"  LOC = "E1"  ;
+NET "io_tx<4>"  LOC = "F2"  ;
+NET "io_tx<3>"  LOC = "J7"  ;
+NET "io_tx<2>"  LOC = "H6"  ;
+NET "io_tx<1>"  LOC = "F5"  ;
+NET "io_tx<0>"  LOC = "G4"  ;
+
+## RX DB GPIO
+NET "io_rx<15>"  LOC = "AD1"  ;
+NET "io_rx<14>"  LOC = "AD2"  ;
+NET "io_rx<13>"  LOC = "AC2"  ;
+NET "io_rx<12>"  LOC = "AC3"  ;
+NET "io_rx<11>"  LOC = "W7"  ;
+NET "io_rx<10>"  LOC = "W6"  ;
+NET "io_rx<9>"  LOC = "U9"  ;
+NET "io_rx<8>"  LOC = "V8"  ;
+NET "io_rx<7>"  LOC = "AB1"  ;
+NET "io_rx<6>"  LOC = "AC1"  ;
+NET "io_rx<5>"  LOC = "V7"  ;
+NET "io_rx<4>"  LOC = "V6"  ;
+NET "io_rx<3>"  LOC = "Y5"  ;
+NET "io_rx<2>"  LOC = "R10"  ;
+NET "io_rx<1>"  LOC = "R1"  ;
+NET "io_rx<0>"  LOC = "M1"  ;
+
+## MISC
 NET "leds<5>"  LOC = "AF25"  ;
 NET "leds<4>"  LOC = "AE25"  ;
 NET "leds<3>"  LOC = "AF23"  ;
 NET "leds<2>"  LOC = "AE23"  ;
 NET "leds<1>"  LOC = "AB18"  ;
-NET "SEN_CLK"  LOC = "AA18"  ;
-NET "MOSI_CLK"  LOC = "W17"  ;
-NET "SCLK_CLK"  LOC = "V17"  ;
-NET "CLK_STATUS"  LOC = "AD22"  ;
-NET "CLK_FUNC"  LOC = "AC21"  ;
-NET "clk_sel<0>"  LOC = "AE21"  ;
-NET "clk_sel<1>"  LOC = "AD21"  ;
-NET "clk_en<1>"  LOC = "AA17"  ;
-NET "clk_en<0>"  LOC = "Y17"  ;
-NET "SDA"  LOC = "V16"  ;
-NET "SCL"  LOC = "U16"  ;
-NET "TXD3"  LOC = "AD20"  ;
-NET "TXD2"  LOC = "AC20"  ;
-NET "TXD1"  LOC = "AD19"  ;
-NET "debug<00>"  LOC = "AC19"  ;
-NET "debug<01>"  LOC = "AF20"  ;
-NET "debug<02>"  LOC = "AE20"  ;
-NET "debug<03>"  LOC = "AC16"  ;
-NET "debug<04>"  LOC = "AB16"  ;
-NET "debug<05>"  LOC = "AF19"  ;
-NET "debug<06>"  LOC = "AE19"  ;
-NET "debug<07>"  LOC = "V15"  ;
-NET "debug<08>"  LOC = "U15"  ;
-NET "debug<09>"  LOC = "AE17"  ;
+NET "FPGA_RESET"  LOC = "K24"  ;
+
+## Debug
+NET "debug_clk<0>"  LOC = "AA10"  ;
+NET "debug_clk<1>"  LOC = "AD11"  ;
+NET "debug<0>"  LOC = "AC19"  ;
+NET "debug<1>"  LOC = "AF20"  ;
+NET "debug<2>"  LOC = "AE20"  ;
+NET "debug<3>"  LOC = "AC16"  ;
+NET "debug<4>"  LOC = "AB16"  ;
+NET "debug<5>"  LOC = "AF19"  ;
+NET "debug<6>"  LOC = "AE19"  ;
+NET "debug<7>"  LOC = "V15"  ;
+NET "debug<8>"  LOC = "U15"  ;
+NET "debug<9>"  LOC = "AE17"  ;
 NET "debug<10>"  LOC = "AD17"  ;
 NET "debug<11>"  LOC = "V14"  ;
 NET "debug<12>"  LOC = "W15"  ;
 NET "debug<13>"  LOC = "AC15"  ;
 NET "debug<14>"  LOC = "AD14"  ;
 NET "debug<15>"  LOC = "AC14"  ;
-NET "debug_clk<1>"  LOC = "AD11"  ;
 NET "debug<16>"  LOC = "AC11"  ;
 NET "debug<17>"  LOC = "AB12"  ;
 NET "debug<18>"  LOC = "AC12"  ;
@@ -168,103 +148,183 @@ NET "debug<28>"  LOC = "AB7"  ;
 NET "debug<29>"  LOC = "V11"  ;
 NET "debug<30>"  LOC = "U11"  ;
 NET "debug<31>"  LOC = "Y10"  ;
-NET "debug_clk<0>"  LOC = "AA10"  ;
+
+## UARTS
+NET "TXD<3>"  LOC = "AD20"  ;
+NET "TXD<2>"  LOC = "AC20"  ;
+NET "TXD<1>"  LOC = "AD19"  ;
+NET "RXD<3>"  LOC = "AF17"  ;
+NET "RXD<2>"  LOC = "AF15"  ;
+NET "RXD<1>"  LOC = "AD12"  ;
+
+## AD9510
+NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "CLK_FUNC"  LOC = "AC21"  ;
+NET "clk_sel<0>"  LOC = "AE21"  ;
+NET "clk_sel<1>"  LOC = "AD21"  ;
+NET "clk_en<1>"  LOC = "AA17"  ;
+NET "clk_en<0>"  LOC = "Y17"  ;
+
+## I2C
+NET "SDA"  LOC = "V16"  ;
+NET "SCL"  LOC = "U16"  ;
+
+## Timing
+NET "PPS_IN"  LOC = "AB6"  ;
+NET "PPS2_IN"  LOC = "AA20"  ;
+
+## SPI
+NET "SEN_CLK"  LOC = "AA18"  ;
+NET "MOSI_CLK"  LOC = "W17"  ;
+NET "SCLK_CLK"  LOC = "V17"  ;
+NET "MISO_CLK"  LOC = "AC10"  ;
+
 NET "SEN_DAC"  LOC = "AE7"  ;
 NET "SCLK_DAC"  LOC = "AF5"  ;
 NET "MOSI_DAC"  LOC = "AE6"  ;
+NET "MISO_DAC"  LOC = "Y3"  ;
+
+NET "SCLK_ADC"  LOC = "B1"  ;
+NET "MOSI_ADC"  LOC = "J8"  ;
+NET "SEN_ADC"  LOC = "J9"  ;
+
 NET "MOSI_TX_ADC"  LOC = "V10"  ;
 NET "SEN_TX_ADC"  LOC = "W10"  ;
 NET "SCLK_TX_ADC"  LOC = "AC6"  ;
+NET "MISO_TX_ADC"  LOC = "G1"  ;
+
 NET "MOSI_TX_DAC"  LOC = "AD6"  ;
 NET "SEN_TX_DAC"  LOC = "AE4"  ;
 NET "SCLK_TX_DAC"  LOC = "AF4"  ;
+
 NET "SCLK_TX_DB"  LOC = "AE3"  ;
 NET "MOSI_TX_DB"  LOC = "AF3"  ;
 NET "SEN_TX_DB"  LOC = "W9"  ;
-NET "RXD3"  LOC = "AF17"  ;
-NET "RXD2"  LOC = "AF15"  ;
-NET "RXD1"  LOC = "AD12"  ;
-NET "MISO_CLK"  LOC = "AC10"  ;
-NET "PPS_IN"  LOC = "AB6"  ;
-NET "PPS2_IN"  LOC = "AA20"  ;
-NET "ser_rx_clk"  LOC = "P18"  ;
-NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
+NET "MISO_TX_DB"  LOC = "AA5"  ;
+
+NET "MOSI_RX_ADC"  LOC = "E3"  ;
+NET "SCLK_RX_ADC"  LOC = "F4"  ;
+NET "SEN_RX_ADC"  LOC = "D3"  ;
+NET "MISO_RX_ADC"  LOC = "C1"  ;
+
+NET "SCLK_RX_DAC"  LOC = "E4"  ;
+NET "SEN_RX_DAC"  LOC = "K9"  ;
+NET "MOSI_RX_DAC"  LOC = "K8"  ;
+
+NET "SCLK_RX_DB"  LOC = "G6"  ;
+NET "MOSI_RX_DB"  LOC = "H7"  ;
+NET "SEN_RX_DB"  LOC = "B2"  ;
+NET "MISO_RX_DB"  LOC = "H4"  ;
+
+## ETH PHY
 NET "CLK_TO_MAC"  LOC = "P26"  ;
-NET "GMII_TX_CLK"  LOC = "P25"  ;
-NET "GMII_RX_CLK"  LOC = "P21"  ;
-NET "ETH_LED"  LOC = "H20"  ;
-NET "GMII_TXD7"  LOC = "G21"  ;
-NET "GMII_TXD6"  LOC = "C26"  ;
-NET "GMII_TXD5"  LOC = "C25"  ;
-NET "GMII_TXD4"  LOC = "J21"  ;
-NET "GMII_TXD3"  LOC = "H21"  ;
-NET "GMII_TXD2"  LOC = "D25"  ;
-NET "GMII_TXD1"  LOC = "D24"  ;
-NET "GMII_TXD0"  LOC = "E26"  ;
+
+NET "GMII_TXD<7>"  LOC = "G21"  ;
+NET "GMII_TXD<6>"  LOC = "C26"  ;
+NET "GMII_TXD<5>"  LOC = "C25"  ;
+NET "GMII_TXD<4>"  LOC = "J21"  ;
+NET "GMII_TXD<3>"  LOC = "H21"  ;
+NET "GMII_TXD<2>"  LOC = "D25"  ;
+NET "GMII_TXD<1>"  LOC = "D24"  ;
+NET "GMII_TXD<0>"  LOC = "E26"  ;
 NET "GMII_TX_EN"  LOC = "D26"  ;
 NET "GMII_TX_ER"  LOC = "J19"  ;
 NET "GMII_GTX_CLK"  LOC = "J20"  ;
-NET "GMII_RXD7"  LOC = "G22"  ;
-NET "GMII_RXD6"  LOC = "K19"  ;
-NET "GMII_RXD5"  LOC = "K18"  ;
-NET "GMII_RXD4"  LOC = "E24"  ;
-NET "GMII_RXD3"  LOC = "F23"  ;
-NET "GMII_RXD2"  LOC = "L18"  ;
-NET "GMII_RXD1"  LOC = "L17"  ;
-NET "GMII_RXD0"  LOC = "F25"  ;
+NET "GMII_TX_CLK"  LOC = "P25"  ;
+
+NET "GMII_RX_CLK"  LOC = "P21"  ;
+NET "GMII_RXD<7>"  LOC = "G22"  ;
+NET "GMII_RXD<6>"  LOC = "K19"  ;
+NET "GMII_RXD<5>"  LOC = "K18"  ;
+NET "GMII_RXD<4>"  LOC = "E24"  ;
+NET "GMII_RXD<3>"  LOC = "F23"  ;
+NET "GMII_RXD<2>"  LOC = "L18"  ;
+NET "GMII_RXD<1>"  LOC = "L17"  ;
+NET "GMII_RXD<0>"  LOC = "F25"  ;
 NET "GMII_RX_DV"  LOC = "F24"  ;
 NET "GMII_RX_ER"  LOC = "L20"  ;
 NET "GMII_CRS"  LOC = "K20"  ;
 NET "GMII_COL"  LOC = "G23"  ;
+
 NET "PHY_INTn"  LOC = "L22"  ;
 NET "MDIO"  LOC = "K21"  ;
 NET "MDC"  LOC = "J23"  ;
-NET "PHY_RESET"  LOC = "J22"  ;
+NET "PHY_RESETn"  LOC = "J22"  ;
+NET "ETH_LED"  LOC = "H20"  ;
+
+## MIMO Interface
+NET "exp_time_out_p"  LOC = "Y14"  ;
+NET "exp_time_out_n"  LOC = "AA14"  ;
 NET "exp_time_in_p"  LOC = "N18"  ;
 NET "exp_time_in_n"  LOC = "N17"  ;
+NET "exp_user_out_p"  LOC = "AF14"  ;
+NET "exp_user_out_n"  LOC = "AE14"  ;
 NET "exp_user_in_p"  LOC = "L24"  ;
 NET "exp_user_in_n"  LOC = "M23"  ;
+
+## SERDES
+NET "ser_enable"  LOC = "R20"  ;
 NET "ser_prbsen"  LOC = "U23"  ;
 NET "ser_loopen"  LOC = "R19"  ;
-NET "ser_enable"  LOC = "R20"  ;
+NET "ser_rx_en"  LOC = "Y21"  ;
+NET "ser_tx_clk"  LOC = "P23"  ;   # SERDES TX CLK
 NET "ser_t<15>"  LOC = "V23"  ;
 NET "ser_t<14>"  LOC = "U22"  ;
 NET "ser_t<13>"  LOC = "V24"  ;
 NET "ser_t<12>"  LOC = "V25"  ;
 NET "ser_t<11>"  LOC = "W23"  ;
 NET "ser_t<10>"  LOC = "V22"  ;
-NET "ser_t<09>"  LOC = "T18"  ;
-NET "ser_t<08>"  LOC = "T17"  ;
-NET "ser_t<07>"  LOC = "Y24"  ;
-NET "ser_t<06>"  LOC = "Y25"  ;
-NET "ser_t<05>"  LOC = "U21"  ;
-NET "ser_t<04>"  LOC = "T20"  ;
-NET "ser_t<03>"  LOC = "Y22"  ;
-NET "ser_t<02>"  LOC = "Y23"  ;
-NET "ser_t<01>"  LOC = "U19"  ;
-NET "ser_t<00>"  LOC = "U18"  ;
+NET "ser_t<9>"  LOC = "T18"  ;
+NET "ser_t<8>"  LOC = "T17"  ;
+NET "ser_t<7>"  LOC = "Y24"  ;
+NET "ser_t<6>"  LOC = "Y25"  ;
+NET "ser_t<5>"  LOC = "U21"  ;
+NET "ser_t<4>"  LOC = "T20"  ;
+NET "ser_t<3>"  LOC = "Y22"  ;
+NET "ser_t<2>"  LOC = "Y23"  ;
+NET "ser_t<1>"  LOC = "U19"  ;
+NET "ser_t<0>"  LOC = "U18"  ;
 NET "ser_tkmsb"  LOC = "AA24"  ;
 NET "ser_tklsb"  LOC = "AA25"  ;
+NET "ser_rx_clk"  LOC = "P18"  ;
 NET "ser_r<15>"  LOC = "V21"  ;
 NET "ser_r<14>"  LOC = "U20"  ;
 NET "ser_r<13>"  LOC = "AA22"  ;
 NET "ser_r<12>"  LOC = "AA23"  ;
 NET "ser_r<11>"  LOC = "V18"  ;
 NET "ser_r<10>"  LOC = "V19"  ;
-NET "ser_r<09>"  LOC = "AB23"  ;
-NET "ser_r<08>"  LOC = "AC26"  ;
-NET "ser_r<07>"  LOC = "AB26"  ;
-NET "ser_r<06>"  LOC = "AD26"  ;
-NET "ser_r<05>"  LOC = "AC25"  ;
-NET "ser_r<04>"  LOC = "W20"  ;
-NET "ser_r<03>"  LOC = "W21"  ;
-NET "ser_r<02>"  LOC = "AC23"  ;
-NET "ser_r<01>"  LOC = "AC24"  ;
-NET "ser_r<00>"  LOC = "AE26"  ;
+NET "ser_r<9>"  LOC = "AB23"  ;
+NET "ser_r<8>"  LOC = "AC26"  ;
+NET "ser_r<7>"  LOC = "AB26"  ;
+NET "ser_r<6>"  LOC = "AD26"  ;
+NET "ser_r<5>"  LOC = "AC25"  ;
+NET "ser_r<4>"  LOC = "W20"  ;
+NET "ser_r<3>"  LOC = "W21"  ;
+NET "ser_r<2>"  LOC = "AC23"  ;
+NET "ser_r<1>"  LOC = "AC24"  ;
+NET "ser_r<0>"  LOC = "AE26"  ;
 NET "ser_rkmsb"  LOC = "AD25"  ;
 NET "ser_rklsb"  LOC = "Y20"  ;
-NET "ser_rx_en"  LOC = "Y21"  ;
-NET "FPGA_RESET"  LOC = "K24"  ;
+
+## SRAM
+NET "RAM_D<35>"  LOC = "K16"  ;
+NET "RAM_D<34>"  LOC = "D20"  ;
+NET "RAM_D<33>"  LOC = "C20"  ;
+NET "RAM_D<32>"  LOC = "E21"  ;
+NET "RAM_D<31>"  LOC = "D21"  ;
+NET "RAM_D<30>"  LOC = "C21"  ;
+NET "RAM_D<29>"  LOC = "B21"  ;
+NET "RAM_D<28>"  LOC = "H17"  ;
+NET "RAM_D<27>"  LOC = "G17"  ;
+NET "RAM_D<26>"  LOC = "B23"  ;
+NET "RAM_D<25>"  LOC = "A22"  ;
+NET "RAM_D<24>"  LOC = "D23"  ;
+NET "RAM_D<23>"  LOC = "C23"  ;
+NET "RAM_D<22>"  LOC = "D22"  ;
+NET "RAM_D<21>"  LOC = "C22"  ;
+NET "RAM_D<20>"  LOC = "F19"  ;
+NET "RAM_D<19>"  LOC = "G20"  ;
+NET "RAM_D<18>"  LOC = "F20"  ;
 NET "RAM_D<17>"  LOC = "F7"  ;
 NET "RAM_D<16>"  LOC = "E7"  ;
 NET "RAM_D<15>"  LOC = "G9"  ;
@@ -273,36 +333,26 @@ NET "RAM_D<13>"  LOC = "G10"  ;
 NET "RAM_D<12>"  LOC = "H10"  ;
 NET "RAM_D<11>"  LOC = "A4"  ;
 NET "RAM_D<10>"  LOC = "B4"  ;
-NET "RAM_D<09>"  LOC = "C5"  ;
-NET "RAM_D<08>"  LOC = "D6"  ;
-NET "RAM_D<07>"  LOC = "J11"  ;
-NET "RAM_D<06>"  LOC = "K11"  ;
-NET "RAM_D<05>"  LOC = "B7"  ;
-NET "RAM_D<04>"  LOC = "C7"  ;
-NET "RAM_D<03>"  LOC = "B6"  ;
-NET "RAM_D<02>"  LOC = "C6"  ;
-NET "RAM_D<01>"  LOC = "C8"  ;
-NET "RAM_D<00>"  LOC = "D8"  ;
-NET "RAM_ZZ"  LOC = "J12"  ;
-NET "RAM_BWn<3>"  LOC = "D9"  ;
-NET "RAM_BWn<2>"  LOC = "A9"  ;
-NET "RAM_BWn<1>"  LOC = "B9"  ;
-NET "RAM_BWn<0>"  LOC = "G12"  ;
-NET "RAM_LDn"  LOC = "H12"  ;
-NET "RAM_OEn"  LOC = "C10"  ;
-NET "RAM_WEn"  LOC = "D10"  ;
-NET "RAM_CLK"  LOC = "A10"  ;
-NET "RAM_CENn"  LOC = "B10"  ;
-NET "RAM_A<00>"  LOC = "C11"  ;
-NET "RAM_A<01>"  LOC = "E12"  ;
-NET "RAM_A<02>"  LOC = "F12"  ;
-NET "RAM_A<03>"  LOC = "D13"  ;
-NET "RAM_A<04>"  LOC = "C12"  ;
-NET "RAM_A<05>"  LOC = "A12"  ;
-NET "RAM_A<06>"  LOC = "B12"  ;
-NET "RAM_A<07>"  LOC = "E14"  ;
-NET "RAM_A<08>"  LOC = "F14"  ;
-NET "RAM_A<09>"  LOC = "B15"  ;
+NET "RAM_D<9>"  LOC = "C5"  ;
+NET "RAM_D<8>"  LOC = "D6"  ;
+NET "RAM_D<7>"  LOC = "J11"  ;
+NET "RAM_D<6>"  LOC = "K11"  ;
+NET "RAM_D<5>"  LOC = "B7"  ;
+NET "RAM_D<4>"  LOC = "C7"  ;
+NET "RAM_D<3>"  LOC = "B6"  ;
+NET "RAM_D<2>"  LOC = "C6"  ;
+NET "RAM_D<1>"  LOC = "C8"  ;
+NET "RAM_D<0>"  LOC = "D8"  ;
+NET "RAM_A<0>"  LOC = "C11"  ;
+NET "RAM_A<1>"  LOC = "E12"  ;
+NET "RAM_A<2>"  LOC = "F12"  ;
+NET "RAM_A<3>"  LOC = "D13"  ;
+NET "RAM_A<4>"  LOC = "C12"  ;
+NET "RAM_A<5>"  LOC = "A12"  ;
+NET "RAM_A<6>"  LOC = "B12"  ;
+NET "RAM_A<7>"  LOC = "E14"  ;
+NET "RAM_A<8>"  LOC = "F14"  ;
+NET "RAM_A<9>"  LOC = "B15"  ;
 NET "RAM_A<10>"  LOC = "A15"  ;
 NET "RAM_A<11>"  LOC = "D16"  ;
 NET "RAM_A<12>"  LOC = "C15"  ;
@@ -314,41 +364,38 @@ NET "RAM_A<17>"  LOC = "B17"  ;
 NET "RAM_A<18>"  LOC = "B18"  ;
 NET "RAM_A<19>"  LOC = "A18"  ;
 NET "RAM_A<20>"  LOC = "D18"  ;
-NET "RAM_D<35>"  LOC = "K16"  ;
-NET "RAM_D<34>"  LOC = "D20"  ;
-NET "RAM_D<33>"  LOC = "C20"  ;
-NET "RAM_D<32>"  LOC = "E21"  ;
-NET "RAM_D<31>"  LOC = "D21"  ;
-NET "RAM_D<30>"  LOC = "C21"  ;
-NET "RAM_D<29>"  LOC = "B21"  ;
-NET "RAM_D<28>"  LOC = "H17"  ;
-NET "RAM_D<27>"  LOC = "G17"  ;
-NET "RAM_D<26>"  LOC = "B23"  ;
-NET "RAM_D<25>"  LOC = "A22"  ;
-NET "RAM_D<24>"  LOC = "D23"  ;
-NET "RAM_D<23>"  LOC = "C23"  ;
-NET "RAM_D<22>"  LOC = "D22"  ;
-NET "RAM_D<21>"  LOC = "C22"  ;
-NET "RAM_D<20>"  LOC = "F19"  ;
-NET "RAM_D<19>"  LOC = "G20"  ;
-NET "RAM_D<18>"  LOC = "F20"  ;
-#NET "unnamed_net20"  LOC = "V20"  ;  # SUSPEND
-NET "PROG_B"  LOC = "A2"  ;
-NET "PUDC_B"  LOC = "G8"  ;
-NET "DONE"  LOC = "AB21"  ;
+NET "RAM_BWn<3>"  LOC = "D9"  ;
+NET "RAM_BWn<2>"  LOC = "A9"  ;
+NET "RAM_BWn<1>"  LOC = "B9"  ;
+NET "RAM_BWn<0>"  LOC = "G12"  ;
+NET "RAM_ZZ"  LOC = "J12"  ;
+NET "RAM_LDn"  LOC = "H12"  ;
+NET "RAM_OEn"  LOC = "C10"  ;
+NET "RAM_WEn"  LOC = "D10"  ;
+NET "RAM_CENn"  LOC = "B10"  ;
+NET "RAM_CLK"  LOC = "A10"  ;
+
+## SPI Flash
 NET "flash_miso"  LOC = "AF24"  ;
 NET "flash_clk"  LOC = "AE24"  ;
-NET "INIT_B"  LOC = "AA15"  ;
 NET "flash_mosi"  LOC = "AB15"  ;
+NET "flash_cs"  LOC = "AA7"  ;
+
+## MISC FPGA, unused for now
+#NET "PROG_B"  LOC = "A2"  ;
+#NET "PUDC_B"  LOC = "G8"  ;
+#NET "DONE"  LOC = "AB21"  ;
+#NET "INIT_B"  LOC = "AA15"  ;
+
+
 #NET "unnamed_net19"  LOC = "AE9"  ;    # VS1
 #NET "unnamed_net18"  LOC = "AF9"  ;    # VS0
 #NET "unnamed_net17"  LOC = "AA12"  ;   # VS2
 #NET "unnamed_net16"  LOC = "Y7"  ;     # M2
-NET "flash_cs"  LOC = "AA7"  ;
 #NET "unnamed_net15"  LOC = "AC4"  ;    # M1
 #NET "unnamed_net14"  LOC = "AD4"  ;    # M0
 #NET "unnamed_net13"  LOC = "D4"  ;     # TMS
 #NET "unnamed_net12"  LOC = "E23"  ;    # TDO
 #NET "unnamed_net11"  LOC = "G7"  ;     # TDI
 #NET "unnamed_net10"  LOC = "A25"  ;    # TCK
-
+#NET "unnamed_net20"  LOC = "V20"  ;    # SUSPEND
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index e95445867..fef23af60 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -3,46 +3,93 @@
 
 module u2plus
   (
+   input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
+   
+   // ADC
+   input ADC_clkout_p, input ADC_clkout_n,
+   input ADCA_12_p, input ADCA_12_n,
+   input ADCA_10_p, input ADCA_10_n,
+   input ADCA_8_p, input ADCA_8_n,
+   input ADCA_6_p, input ADCA_6_n,
+   input ADCA_4_p, input ADCA_4_n,
+   input ADCA_2_p, input ADCA_2_n,
+   input ADCA_0_p, input ADCA_0_n,
+   input ADCB_12_p, input ADCB_12_n,
+   input ADCB_10_p, input ADCB_10_n,
+   input ADCB_8_p, input ADCB_8_n,
+   input ADCB_6_p, input ADCB_6_n,
+   input ADCB_4_p, input ADCB_4_n,
+   input ADCB_2_p, input ADCB_2_n,
+   input ADCB_0_p, input ADCB_0_n,
+   
+   // DAC
+   output [15:0] DACA,
+   output [15:0] DACB,
+   input DAC_LOCK,     // unused for now
+   
+   // DB IO Pins
+   inout [15:0] io_tx,
+   inout [15:0] io_rx,
+
    // Misc, debug
-   output [4:0] leds,  // LED4 is shared w/INIT_B
-   input [3:0] dipsw,
-   output [31:0] debug,
+   output [5:1] leds,  // LED4 is shared w/INIT_B
+   input FPGA_RESET,
    output [1:0] debug_clk,
-   output uart_tx_o,
-   input uart_rx_i,
-   
-   // Expansion
-   input exp_pps_in_p, // Diff
-   input exp_pps_in_n, // Diff
-   output exp_pps_out_p, // Diff 
-   output exp_pps_out_n, // Diff 
+   output [31:0] debug,
+   output [3:1] TXD, input [3:1] RXD, // UARTs
+   //input [3:0] dipsw,  // Forgot DIP Switches...
    
-   // GMII
-   //   GMII-CTRL
-   input GMII_COL,
-   input GMII_CRS,
+   // Clock Gen Control
+   output [1:0] clk_en,
+   output [1:0] clk_sel,
+   input CLK_FUNC,        // FIXME is an input to control the 9510
+   input CLK_STATUS,
+
+   inout SCL, inout SDA,   // I2C
+
+   // PPS
+   input PPS_IN, input PPS2_IN,
+
+   // SPI
+   output SEN_CLK, output SCLK_CLK, output MOSI_CLK, input MISO_CLK,
+   output SEN_DAC, output SCLK_DAC, output MOSI_DAC, input MISO_DAC,
+   output SEN_ADC, output SCLK_ADC, output MOSI_ADC,
+   output SEN_TX_DB, output SCLK_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,
+   output SEN_TX_DAC, output SCLK_TX_DAC, output MOSI_TX_DAC,
+   output SEN_TX_ADC, output SCLK_TX_ADC, output MOSI_TX_ADC, input MISO_TX_ADC,
+   output SEN_RX_DB, output SCLK_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,
+   output SEN_RX_DAC, output SCLK_RX_DAC, output MOSI_RX_DAC,
+   output SEN_RX_ADC, output SCLK_RX_ADC, output MOSI_RX_ADC, input MISO_RX_ADC,
+
+   // GigE PHY
+   input CLK_TO_MAC,
 
-   //   GMII-TX
    output reg [7:0] GMII_TXD,
    output reg GMII_TX_EN,
    output reg GMII_TX_ER,
    output GMII_GTX_CLK,
    input GMII_TX_CLK,  // 100mbps clk
 
-   //   GMII-RX
-   input [7:0] GMII_RXD,
    input GMII_RX_CLK,
+   input [7:0] GMII_RXD,
    input GMII_RX_DV,
    input GMII_RX_ER,
+   input GMII_COL,
+   input GMII_CRS,
 
-   //   GMII-Management
+   input PHY_INTn,   // open drain
    inout MDIO,
    output MDC,
-   input PHY_INTn,   // open drain
    output PHY_RESETn,
-   input PHY_CLK,   // possibly use on-board osc
-   input clk_to_mac,
-   output eth_led,
+   output ETH_LED,
+   
+   input POR,
+   
+   // Expansion
+   input exp_time_in_p, input exp_time_in_n, // Diff
+   output exp_time_out_p, output exp_time_out_n, // Diff 
+   input exp_user_in_p, input exp_user_in_n, // Diff
+   output exp_user_out_p, output exp_user_out_n, // Diff 
    
    // SERDES
    output ser_enable,
@@ -59,75 +106,18 @@ module u2plus
    input [15:0] ser_r,
    input ser_rklsb,
    input ser_rkmsb,
-   
-   // ADC
-   input [13:0] adc_a,
-   input adc_ovf_a,
-   output adc_oen_a,
-   output adc_pdn_a,
-   
-   input [13:0] adc_b,
-   input adc_ovf_b,
-   output adc_oen_b,
-   output adc_pdn_b,
-   
-   // DAC
-   output [15:0] dac_a,
-   output [15:0] dac_b,
-   input dac_lock,     // unused for now
-   
-   // I2C
-   inout SCL,
-   inout SDA,
 
-   // Clock Gen Control
-   output [1:0] clk_en,
-   output [1:0] clk_sel,
-   input clk_func,        // FIXME is an input to control the 9510
-   input clk_status,
-
-   // Clocks
-   input clk_fpga_p,  // Diff
-   input clk_fpga_n,  // Diff
-   input pps_in,
-   input POR,
+   // SRAM
+   inout [35:0] RAM_D,
+   output [20:0] RAM_A,
+   output [3:0] RAM_BWn,
+   output RAM_ZZ,
+   output RAM_LDn,
+   output RAM_OEn,
+   output RAM_WEn,
+   output RAM_CENn,
+   output RAM_CLK,
    
-   // AD9510 SPI
-   output sclk,
-   output sen_clk,
-   output sdi,
-   input sdo,
-
-   // TX side SPI -- tx_db, tx_adc, tx_dac, 9777
-   output sen_dac,
-   output sen_tx_db,
-   output sen_tx_adc,
-   output sen_tx_dac,
-   output mosi_tx,
-   input miso_dac,
-   input miso_tx_db,
-   input miso_tx_adc,
-   output sclk_tx,
-
-   // RX side SPI
-   output sen_rx_db,
-   output sclk_rx_db,
-   input sdo_rx_db,
-   output sdi_rx_db,
-
-   output sen_rx_adc,
-   output sclk_rx_adc,
-   input sdo_rx_adc,
-   output sdi_rx_adc,
-
-   output sen_rx_dac,
-   output sclk_rx_dac,
-   output sdi_rx_dac,
-
-   // DB IO Pins
-   inout [15:0] io_tx,
-   inout [15:0] io_rx,
-
    // SPI Flash
    output flash_cs,
    output flash_clk,
@@ -136,37 +126,49 @@ module u2plus
    );
 
    // FPGA-specific pins connections
-   wire 	aux_clk = PHY_CLK;
-
    wire 	clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
 
-   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(clk_fpga_p),.IB(clk_fpga_n));
+   IBUFGDS clk_fpga_pin (.O(clk_fpga),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
    defparam 	clk_fpga_pin.IOSTANDARD = "LVPECL_25";
    
-   wire 	exp_pps_in;
-   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
-   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
    
-   wire 	exp_pps_out;
-   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
-   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
-
-   reg [5:0] 	clock_ready_d;
-   always @(posedge aux_clk)
-     clock_ready_d[5:0] <= {clock_ready_d[4:0],clock_ready};
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD  = "LVDS_25";
 
-   wire 	dcm_rst = ~&clock_ready_d & |clock_ready_d;
-   wire 	clk_muxed = clock_ready ? clk_fpga : aux_clk;
+   wire 	exp_user_in;
+   IBUFDS exp_user_in_pin (.O(exp_user_in),.I(exp_user_in_p),.IB(exp_user_in_n));
+   defparam 	exp_user_in_pin.IOSTANDARD = "LVDS_25";
+   
+   wire 	exp_user_out;
+   OBUFDS exp_user_out_pin (.O(exp_user_out_p),.OB(exp_user_out_n),.I(exp_user_out));
+   defparam 	exp_user_out_pin.IOSTANDARD  = "LVDS_25";
 
-   wire 	adc_on_a, adc_on_b, adc_oe_a, adc_oe_b;
-   assign 	adc_oen_a = ~adc_oe_a;
-   assign 	adc_oen_b = ~adc_oe_b;
-   assign 	adc_pdn_a = ~adc_on_a; 	
-   assign 	adc_pdn_b = ~adc_on_b; 	
+   wire 	dcm_rst 		    = 0;
 
+   wire [13:0] 	adc_a, adc_b;
+`ifdef LVDS
+   capture_ddrlvds #(.WIDTH(14)) capture_ddrlvds
+     (.clk(dsp_clk), .ssclk_p(ADC_clkout_p), .ssclk_n(ADC_clkout_n), 
+      .in_p({{ADCA_12_p, ADCA_10_p, ADCA_8_p, ADCA_6_p, ADCA_4_p, ADCA_2_p, ADCA_0_p},
+	     {ADCB_12_p, ADCB_10_p, ADCB_8_p, ADCB_6_p, ADCB_4_p, ADCB_2_p, ADCB_0_p}}), 
+      .in_n({{ADCA_12_n, ADCA_10_n, ADCA_8_n, ADCA_6_n, ADCA_4_n, ADCA_2_n, ADCA_0_n},
+	     {ADCB_12_n, ADCB_10_n, ADCB_8_n, ADCB_6_n, ADCB_4_n, ADCB_2_n, ADCB_0_n}}), 
+      .out({adc_a,adc_b}));
+`else
+   assign adc_a = {ADCA_12_p,ADCA_12_n, ADCA_10_p,ADCA_10_n, ADCA_8_p,ADCA_8_n, ADCA_6_p,ADCA_6_n,
+		   ADCA_4_p,ADCA_4_n, ADCA_2_p,ADCA_2_n, ADCA_0_p,ADCA_0_n };
+   assign adc_b = {ADCB_12_p,ADCB_12_n, ADCB_10_p,ADCB_10_n, ADCB_8_p,ADCB_8_n, ADCB_6_p,ADCB_6_n,
+		   ADCB_4_p,ADCB_4_n, ADCB_2_p,ADCB_2_n, ADCB_0_p,ADCB_0_n };
+   
+`endif // !`ifdef LVDS
+   
    // Handle Clocks
    DCM DCM_INST (.CLKFB(dsp_clk), 
-                 .CLKIN(clk_muxed), 
+                 .CLKIN(clk_fpga), 
                  .DSSEN(0), 
                  .PSCLK(0), 
                  .PSEN(0), 
@@ -207,23 +209,26 @@ module u2plus
    IOBUF sda_pin(.O(sda_pad_i), .IO(SDA), .I(sda_pad_o), .T(sda_pad_oen_o));
 
    // LEDs are active low outputs
-   wire [4:0] leds_int;
-   assign     leds = ~leds_int;  // drive low to turn on leds
+   wire [5:0] leds_int;
+   assign     {leds,ETH_LED} = ~leds_int;  // drive low to turn on leds
    
    // SPI
-   wire 	miso, mosi, sclk_int;
-   assign 	{sclk,sdi} = (~sen_clk | ~sen_dac) ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_tx_db,sdi_tx_db} = ~sen_tx_db ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_tx_dac,sdi_tx_dac} = ~sen_tx_dac ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_tx_adc,sdi_tx_adc} = ~sen_tx_adc ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_rx_db,sdi_rx_db} = ~sen_rx_db ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_rx_dac,sdi_rx_dac} = ~sen_rx_dac ? {sclk_int,mosi} : 2'b0;
-   assign 	{sclk_rx_adc,sdi_rx_adc} = ~sen_rx_adc ? {sclk_int,mosi} : 2'b0;
-   
-   assign 	miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
-		(~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
-		(~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
+   wire       miso, mosi, sclk;
 
+   assign 	{SCLK_CLK,MOSI_CLK} 	   = ~SEN_CLK ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_DAC,MOSI_DAC} 	   = ~SEN_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_ADC,MOSI_ADC} 	   = ~SEN_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DB,MOSI_TX_DB}    = ~SEN_TX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_DAC,MOSI_TX_DAC}  = ~SEN_TX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_TX_ADC,MOSI_TX_ADC}  = ~SEN_TX_ADC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DB,MOSI_RX_DB}    = ~SEN_RX_DB ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_DAC,MOSI_RX_DAC}  = ~SEN_RX_DAC ? {sclk,mosi} : 2'B0;
+   assign 	{SCLK_RX_ADC,MOSI_RX_ADC}  = ~SEN_RX_ADC ? {sclk,mosi} : 2'B0;
+   
+   assign 	miso 			   = (~SEN_CLK & MISO_CLK) | (~SEN_DAC & MISO_DAC) |
+					     (~SEN_TX_DB & MISO_TX_DB) | (~SEN_TX_ADC & MISO_TX_ADC) |
+					     (~SEN_RX_DB & MISO_RX_DB) | (~SEN_RX_ADC & MISO_RX_ADC);
+   
    wire 	GMII_TX_EN_unreg, GMII_TX_ER_unreg;
    wire [7:0] 	GMII_TXD_unreg;
    wire 	GMII_GTX_CLK_int;
@@ -289,8 +294,8 @@ module u2plus
 		     .leds		(leds_int),
 		     .debug		(debug[31:0]),
 		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_pps_in),
-		     .exp_pps_out	(exp_pps_out),
+		     .exp_pps_in	(exp_time_in),
+		     .exp_pps_out	(exp_time_out),
 		     .GMII_COL		(GMII_COL),
 		     .GMII_CRS		(GMII_CRS),
 		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
@@ -306,7 +311,6 @@ module u2plus
 		     .MDC		(MDC),
 		     .PHY_INTn		(PHY_INTn),
 		     .PHY_RESETn	(PHY_RESETn),
-		     .PHY_CLK		(PHY_CLK),
 		     .ser_enable	(ser_enable),
 		     .ser_prbsen	(ser_prbsen),
 		     .ser_loopen	(ser_loopen),
@@ -333,8 +337,8 @@ module u2plus
 		     .adc_ovf_b		(adc_ovf_b),
 		     .adc_on_b		(adc_on_b),
 		     .adc_oe_b		(adc_oe_b),
-		     .dac_a		(dac_a[15:0]),
-		     .dac_b		(dac_b[15:0]),
+		     .dac_a		(DACA[15:0]),
+		     .dac_b		(DACB[15:0]),
 		     .scl_pad_i		(scl_pad_i),
 		     .scl_pad_o		(scl_pad_o),
 		     .scl_pad_oen_o	(scl_pad_oen_o),
@@ -367,11 +371,17 @@ module u2plus
 		     .RAM_OEn           (RAM_OEn),
 		     .RAM_LDn           (RAM_LDn), 
 		     .uart_tx_o         (uart_tx_o),
-		     //.uart_rx_i         (uart_rx_i),
-		     .uart_rx_i         (),
+		     .uart_rx_i         (uart_rx_i),
 		     .uart_baud_o       (),
 		     .sim_mode          (1'b0),
 		     .clock_divider     (2)
 		     );
+
+   assign RAM_ZZ = 1;
+   assign flash_clk = 0;
+   assign flash_cs = 1;
+   assign flash_mosi = 0;
+   assign RAM_BWn = 4'b1111;
+   assign TXD = 3'b111;
    
 endmodule // u2plus