dsp_core_tx now has setting reg base settable from u2_core. underrun bug in vrt fixed

3 files changed, 9 insertions, 10 deletions

diff --git a/sdr_lib/dsp_core_tx.v b/sdr_lib/dsp_core_tx.v
index 346d65ced..22d3d44a3 100644
--- a/sdr_lib/dsp_core_tx.v
+++ b/sdr_lib/dsp_core_tx.v
@@ -1,7 +1,6 @@
 
-`define DSP_CORE_TX_BASE 128
-
 module dsp_core_tx
+  #(parameter BASE=0)
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
@@ -22,19 +21,19 @@ module dsp_core_tx
    wire [3:0]  dacmux_a, dacmux_b;
    wire        enable_hb1, enable_hb2;
 
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
+   setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
 
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+1)) sr_1
+   setting_reg #(.my_addr(BASE+1)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
    
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
+   setting_reg #(.my_addr(BASE+2)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
 
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4
+   setting_reg #(.my_addr(BASE+4)) sr_4
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
 
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index 8551efca0..f9ac07a55 100644
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -618,7 +618,7 @@ module u2_core
    
    assign debug_vt = debug_vtc | debug_vtd;
    
-   dsp_core_tx dsp_core_tx
+   dsp_core_tx #(.BASE(SR_TX_DSP)) dsp_core_tx
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
@@ -729,8 +729,8 @@ module u2_core
  */
 
    assign debug = debug_vt;
-   assign debug_gpio_0 = tx_data;
-   assign debug_gpio_1 = sample_tx;
+   assign debug_gpio_0 = sample_tx;
+   assign debug_gpio_1 = 32'hDEAD_BEEF;
    
 endmodule // u2_core
 
diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v
index 689acd708..919ded4df 100644
--- a/vrt/vita_tx_control.v
+++ b/vrt/vita_tx_control.v
@@ -62,7 +62,7 @@ module vita_tx_control
 	   if(strobe)
 	     if(~sample_fifo_src_rdy_i)
 	       ibs_state <= IBS_UNDERRUN;
-	     else if(eob)
+	     else if(eop & eob)
 	       ibs_state <= IBS_IDLE;
 	     // else if(eop)  FIXME do we care if the packet ends?