Merge branch 'packet_router' into zpu

Conflicts:
	usrp2/top/u2_rev3/u2_core.v

15 files changed, 383 insertions, 303 deletions

diff --git a/usrp2/fifo/dsp_framer36.v b/usrp2/fifo/dsp_framer36.v
index fbdc9fbd7..34a05d91e 100644
--- a/usrp2/fifo/dsp_framer36.v
+++ b/usrp2/fifo/dsp_framer36.v
@@ -20,10 +20,10 @@ module dsp_framer36
     wire [BUF_SIZE-1:0] dsp_frm_addr_next = dsp_frm_addr + 1'b1;
 
     //DSP input stream ready in the following states
-    assign inp_ready =
-        (dsp_frm_state == DSP_FRM_STATE_WAIT_SOF)? 1'b1 : (
-        (dsp_frm_state == DSP_FRM_STATE_WAIT_EOF)? 1'b1 : (
-    1'b0));
+    assign inp_ready = (
+        dsp_frm_state == DSP_FRM_STATE_WAIT_SOF ||
+        dsp_frm_state == DSP_FRM_STATE_WAIT_EOF
+    )? 1'b1 : 1'b0;
 
     //DSP framer output data mux (header or BRAM):
     //The header is generated here from the count.
@@ -41,7 +41,7 @@ module dsp_framer36
     RAMB16_S36_S36 dsp_frm_buff(
         //port A = DSP input interface (writes to BRAM)
         .DOA(),.ADDRA(dsp_frm_addr),.CLKA(clk),.DIA(inp_data[31:0]),.DIPA(4'h0),
-        .ENA(inp_ready),.SSRA(0),.WEA(inp_ready),
+        .ENA(inp_ready & inp_valid),.SSRA(0),.WEA(inp_ready & inp_valid),
         //port B = DSP framer interface (reads from BRAM)
         .DOB(dsp_frm_data_bram),.ADDRB(dsp_frm_addr),.CLKB(clk),.DIB(36'b0),.DIPB(4'h0),
         .ENB(out_ready & out_valid),.SSRB(0),.WEB(1'b0)
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index 6cf022b11..9491d4346 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -88,9 +88,19 @@ module packet_router
         .out(my_ip_addr),.changed()
     );
 
+    //setting register to program the UDP ctrl ports
+    /*
+    wire [15:0] ctrl_udp_port, other_udp_port;
+    setting_reg #(.my_addr(CTRL_BASE+2)) sreg_ctrl_ports(
+        .clk(stream_clk),.rst(stream_rst),
+        .strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({other_udp_port, ctrl_udp_port}),.changed()
+    );
+    */
+
     //setting register to program the UDP data ports
     wire [15:0] dsp0_udp_port, dsp1_udp_port;
-    setting_reg #(.my_addr(CTRL_BASE+2)) sreg_udp_ports(
+    setting_reg #(.my_addr(CTRL_BASE+3)) sreg_data_ports(
         .clk(stream_clk),.rst(stream_rst),
         .strobe(set_stb),.addr(set_addr),.in(set_data),
         .out({dsp1_udp_port, dsp0_udp_port}),.changed()
@@ -99,7 +109,7 @@ module packet_router
     //setting register for CPU output handshake
     wire [31:0] _sreg_cpu_out_ctrl;
     wire cpu_out_hs_ctrl = _sreg_cpu_out_ctrl[0];
-    setting_reg #(.my_addr(CTRL_BASE+3)) sreg_cpu_out_ctrl(
+    setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_out_ctrl(
         .clk(stream_clk),.rst(stream_rst),
         .strobe(set_stb),.addr(set_addr),.in(set_data),
         .out(_sreg_cpu_out_ctrl),.changed()
@@ -109,7 +119,7 @@ module packet_router
     wire [31:0] _sreg_cpu_inp_ctrl;
     wire cpu_inp_hs_ctrl = _sreg_cpu_inp_ctrl[0];
     wire [BUF_SIZE-1:0] cpu_inp_line_count = _sreg_cpu_inp_ctrl[BUF_SIZE-1+16:0+16];
-    setting_reg #(.my_addr(CTRL_BASE+4)) sreg_cpu_inp_ctrl(
+    setting_reg #(.my_addr(CTRL_BASE+5)) sreg_cpu_inp_ctrl(
         .clk(stream_clk),.rst(stream_rst),
         .strobe(set_stb),.addr(set_addr),.in(set_data),
         .out(_sreg_cpu_inp_ctrl),.changed()
@@ -135,9 +145,9 @@ module packet_router
     ////////////////////////////////////////////////////////////////////
 
     //streaming signals from the crossbar to the combiner
-    wire [35:0] crs_inp_data;
-    wire        crs_inp_valid;
-    wire        crs_inp_ready;
+    wire [35:0] ext_inp_data;
+    wire        ext_inp_valid;
+    wire        ext_inp_ready;
 
     //dummy signals for valve/xbar below
     wire [35:0] _eth_inp_data;
@@ -155,7 +165,7 @@ module packet_router
         .data0_i(_eth_inp_data), .src0_rdy_i(_eth_inp_valid), .dst0_rdy_o(_eth_inp_ready),
         .data1_i(ser_inp_data), .src1_rdy_i(ser_inp_valid), .dst1_rdy_o(ser_inp_ready),
         .data0_o(com_inp_data), .src0_rdy_o(com_inp_valid), .dst0_rdy_i(com_inp_ready),
-        .data1_o(crs_inp_data), .src1_rdy_o(crs_inp_valid), .dst1_rdy_i(crs_inp_ready)
+        .data1_o(ext_inp_data), .src1_rdy_o(ext_inp_valid), .dst1_rdy_i(ext_inp_ready)
     );
 
     ////////////////////////////////////////////////////////////////////
@@ -169,9 +179,9 @@ module packet_router
     ////////////////////////////////////////////////////////////////////
 
     //streaming signals from the inspector to the crossbar
-    wire [35:0] crs_out_data;
-    wire        crs_out_valid;
-    wire        crs_out_ready;
+    wire [35:0] ext_out_data;
+    wire        ext_out_valid;
+    wire        ext_out_ready;
 
     //dummy signals for valve/xbar below
     wire [35:0] _eth_out_data;
@@ -181,7 +191,7 @@ module packet_router
     crossbar36 com_out_xbar (
         .clk(stream_clk), .reset(stream_rst), .clear(stream_clr), .cross(~master_mode_flag),
         .data0_i(com_out_data), .src0_rdy_i(com_out_valid), .dst0_rdy_o(com_out_ready),
-        .data1_i(crs_out_data), .src1_rdy_i(crs_out_valid), .dst1_rdy_o(crs_out_ready),
+        .data1_i(ext_out_data), .src1_rdy_i(ext_out_valid), .dst1_rdy_o(ext_out_ready),
         .data0_o(_eth_out_data), .src0_rdy_o(_eth_out_valid), .dst0_rdy_i(_eth_out_ready),
         .data1_o(ser_out_data), .src1_rdy_o(ser_out_valid), .dst1_rdy_i(ser_out_ready)
     );
@@ -196,8 +206,7 @@ module packet_router
     // Communication output source combiner (feeds UDP proto machine)
     //   - DSP framer
     //   - CPU input
-    //   - Error input
-    //   - Crossbar input
+    //   - ERR input
     ////////////////////////////////////////////////////////////////////
 
     //streaming signals from the dsp framer to the combiner
@@ -244,13 +253,10 @@ module packet_router
     assign cpu_out_line_count = cpu_out_addr;
     wire [BUF_SIZE-1:0] cpu_out_addr_next = cpu_out_addr + 1'b1;
 
-    wire cpu_out_reading = (
+    assign cpu_out_ready = (
         cpu_out_state == CPU_OUT_STATE_WAIT_SOF ||
         cpu_out_state == CPU_OUT_STATE_WAIT_EOF
     )? 1'b1 : 1'b0;
-
-    wire cpu_out_we = cpu_out_reading;
-    assign cpu_out_ready = cpu_out_reading;
     assign cpu_out_hs_stat = (cpu_out_state == CPU_OUT_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0;
 
     RAMB16_S36_S36 cpu_out_buff(
@@ -258,8 +264,8 @@ module packet_router
         .DOA(wb_dat_o),.ADDRA(wb_adr_i[BUF_SIZE+1:2]),.CLKA(wb_clk_i),.DIA(36'b0),.DIPA(4'h0),
         .ENA(wb_stb_i & (which_buf == 1'b0)),.SSRA(0),.WEA(wb_we_i),
         //port B = packet router interface to CPU (input only)
-        .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data),.DIPB(4'h0),
-        .ENB(cpu_out_we),.SSRB(0),.WEB(cpu_out_we)
+        .DOB(),.ADDRB(cpu_out_addr),.CLKB(stream_clk),.DIB(cpu_out_data[31:0]),.DIPB(4'h0),
+        .ENB(cpu_out_ready & cpu_out_valid),.SSRB(0),.WEB(cpu_out_ready & cpu_out_valid)
     );
 
     always @(posedge stream_clk)
@@ -319,6 +325,7 @@ module packet_router
         (cpu_inp_addr == cpu_inp_line_count_reg)? 4'b0010 : (
     4'b0000));
 
+    wire cpu_inp_enb = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? (cpu_inp_ready & cpu_inp_valid) : 1'b1;
     assign cpu_inp_valid = (cpu_inp_state == CPU_INP_STATE_UNLOAD)? 1'b1 : 1'b0;
     assign cpu_inp_hs_stat = (cpu_inp_state == CPU_INP_STATE_WAIT_CTRL_HI)? 1'b1 : 1'b0;
 
@@ -328,7 +335,7 @@ module packet_router
         .ENA(wb_stb_i & (which_buf == 1'b1)),.SSRA(0),.WEA(wb_we_i),
         //port B = packet router interface from CPU (output only)
         .DOB(cpu_inp_data[31:0]),.ADDRB(cpu_inp_addr),.CLKB(stream_clk),.DIB(36'b0),.DIPB(4'h0),
-        .ENB(cpu_inp_ready & cpu_inp_valid),.SSRB(0),.WEB(1'b0)
+        .ENB(cpu_inp_enb),.SSRB(0),.WEB(1'b0)
     );
 
     always @(posedge stream_clk)
@@ -369,37 +376,42 @@ module packet_router
 
     ////////////////////////////////////////////////////////////////////
     // Communication input inspector
-    //   - inspect com input and send it to CPU, DSP, or COM
+    //   - inspect com input and send it to DSP, EXT, CPU, or BOTH
     ////////////////////////////////////////////////////////////////////
     localparam COM_INSP_STATE_READ_COM_PRE = 0;
     localparam COM_INSP_STATE_READ_COM = 1;
     localparam COM_INSP_STATE_WRITE_REGS = 2;
     localparam COM_INSP_STATE_WRITE_LIVE = 3;
 
-    localparam COM_INSP_DEST_FP_THIS = 0;
-    localparam COM_INSP_DEST_FP_OTHER = 1;
-    localparam COM_INSP_DEST_SP_BOTH = 2;
+    localparam COM_INSP_DEST_DSP = 0;
+    localparam COM_INSP_DEST_EXT = 1;
+    localparam COM_INSP_DEST_CPU = 2;
+    localparam COM_INSP_DEST_BOF = 3;
 
     localparam COM_INSP_MAX_NUM_DREGS = 13; //padded_eth + ip + udp + seq + vrt_hdr
     localparam COM_INSP_DREGS_DSP_OFFSET = 11; //offset to start dsp at
 
     //output inspector interfaces
-    wire [35:0] com_insp_out_fp_this_data;
-    wire com_insp_out_fp_this_valid;
-    wire com_insp_out_fp_this_ready;
+    wire [35:0] com_insp_out_dsp_data;
+    wire        com_insp_out_dsp_valid;
+    wire        com_insp_out_dsp_ready;
+
+    wire [35:0] com_insp_out_ext_data;
+    wire        com_insp_out_ext_valid;
+    wire        com_insp_out_ext_ready;
 
-    wire [35:0] com_insp_out_fp_other_data;
-    wire com_insp_out_fp_other_valid;
-    wire com_insp_out_fp_other_ready;
+    wire [35:0] com_insp_out_cpu_data;
+    wire        com_insp_out_cpu_valid;
+    wire        com_insp_out_cpu_ready;
 
-    wire [35:0] com_insp_out_sp_both_data;
-    wire com_insp_out_sp_both_valid;
-    wire com_insp_out_sp_both_ready;
+    wire [35:0] com_insp_out_bof_data;
+    wire        com_insp_out_bof_valid;
+    wire        com_insp_out_bof_ready;
 
     //connect this fast-path signals directly to the DSP out
-    assign dsp_out_data = com_insp_out_fp_this_data;
-    assign dsp_out_valid = com_insp_out_fp_this_valid;
-    assign com_insp_out_fp_this_ready = dsp_out_ready;
+    assign dsp_out_data = com_insp_out_dsp_data;
+    assign dsp_out_valid = com_insp_out_dsp_valid;
+    assign com_insp_out_dsp_ready = dsp_out_ready;
 
     reg [1:0] com_insp_state;
     reg [1:0] com_insp_dest;
@@ -408,23 +420,19 @@ module packet_router
     wire com_insp_dreg_counter_done = (com_insp_dreg_count_next == COM_INSP_MAX_NUM_DREGS)? 1'b1 : 1'b0;
     reg [35:0] com_insp_dregs [COM_INSP_MAX_NUM_DREGS-1:0];
 
-    //Inspection logic:
-    wire com_inp_dregs_is_data = 1'b1
-        && (com_insp_dregs[3][15:0] == 16'h800)        //ethertype IPv4
-        && (com_insp_dregs[6][23:16] == 8'h11)         //protocol UDP
-        && (com_insp_dregs[9][15:0] == dsp0_udp_port)  //UDP data port
-        && (com_inp_data[15:0] != 16'h0)               //VRT packet size
-    ;
-
-    wire com_inp_dregs_my_ip_match = (my_ip_addr == com_insp_dregs[8][31:0])? 1'b1 : 1'b0;
-    wire com_inp_dregs_is_data_here = com_inp_dregs_is_data & com_inp_dregs_my_ip_match;
-    wire com_inp_dregs_is_data_there = com_inp_dregs_is_data & ~com_inp_dregs_my_ip_match;
+    //extract various packet components:
+    wire [47:0] com_insp_dregs_eth_dst_mac   = {com_insp_dregs[0][15:0], com_insp_dregs[1][31:0]};
+    wire [15:0] com_insp_dregs_eth_type      = com_insp_dregs[3][15:0];
+    wire [7:0]  com_insp_dregs_ipv4_proto    = com_insp_dregs[6][23:16];
+    wire [31:0] com_insp_dregs_ipv4_dst_addr = com_insp_dregs[8][31:0];
+    wire [15:0] com_insp_dregs_udp_dst_port  = com_insp_dregs[9][15:0];
+    wire [15:0] com_insp_dregs_vrt_size      = com_inp_data[15:0];
 
     //Inspector output flags special case:
     //Inject SOF into flags at first DSP line.
     wire [3:0] com_insp_out_flags = (
         (com_insp_dreg_count == COM_INSP_DREGS_DSP_OFFSET) &&
-        (com_insp_dest == COM_INSP_DEST_FP_THIS)
+        (com_insp_dest == COM_INSP_DEST_DSP)
     )? 4'b0001 : com_insp_dregs[com_insp_dreg_count][35:32];
 
     //The communication inspector ouput data and valid signals:
@@ -440,21 +448,24 @@ module packet_router
     //The communication inspector ouput ready signal:
     //Mux between the various destination ready signals.
     wire com_insp_out_ready =
-        (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_fp_this_ready  : (
-        (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_fp_other_ready : (
-        (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_sp_both_ready  : (
-    1'b0)));
+        (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_dsp_ready : (
+        (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_ext_ready : (
+        (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_cpu_ready : (
+        (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_bof_ready : (
+    1'b0))));
 
     //Always connected output data lines.
-    assign com_insp_out_fp_this_data = com_insp_out_data;
-    assign com_insp_out_fp_other_data = com_insp_out_data;
-    assign com_insp_out_sp_both_data = com_insp_out_data;
+    assign com_insp_out_dsp_data = com_insp_out_data;
+    assign com_insp_out_ext_data = com_insp_out_data;
+    assign com_insp_out_cpu_data = com_insp_out_data;
+    assign com_insp_out_bof_data = com_insp_out_data;
 
     //Destination output valid signals:
     //Comes from inspector valid when destination is selected, and otherwise low.
-    assign com_insp_out_fp_this_valid  = (com_insp_dest == COM_INSP_DEST_FP_THIS) ? com_insp_out_valid : 1'b0;
-    assign com_insp_out_fp_other_valid = (com_insp_dest == COM_INSP_DEST_FP_OTHER)? com_insp_out_valid : 1'b0;
-    assign com_insp_out_sp_both_valid  = (com_insp_dest == COM_INSP_DEST_SP_BOTH) ? com_insp_out_valid : 1'b0;
+    assign com_insp_out_dsp_valid = (com_insp_dest == COM_INSP_DEST_DSP)? com_insp_out_valid : 1'b0;
+    assign com_insp_out_ext_valid = (com_insp_dest == COM_INSP_DEST_EXT)? com_insp_out_valid : 1'b0;
+    assign com_insp_out_cpu_valid = (com_insp_dest == COM_INSP_DEST_CPU)? com_insp_out_valid : 1'b0;
+    assign com_insp_out_bof_valid = (com_insp_dest == COM_INSP_DEST_BOF)? com_insp_out_valid : 1'b0;
 
     //The communication inspector ouput ready signal:
     //Always ready when storing to data registers,
@@ -484,20 +495,38 @@ module packet_router
         COM_INSP_STATE_READ_COM: begin
             if (com_inp_ready & com_inp_valid) begin
                 com_insp_dregs[com_insp_dreg_count] <= com_inp_data;
-                if (com_inp_dregs_is_data_here & com_insp_dreg_counter_done) begin
-                    com_insp_dest <= COM_INSP_DEST_FP_THIS;
-                    com_insp_state <= COM_INSP_STATE_WRITE_REGS;
-                    com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
-                end
-                else if (com_inp_dregs_is_data_there & com_insp_dreg_counter_done) begin
-                    com_insp_dest <= COM_INSP_DEST_FP_OTHER;
-                    com_insp_state <= COM_INSP_STATE_WRITE_REGS;
-                    com_insp_dreg_count <= 0;
-                end
-                else if (com_inp_data[33] | com_insp_dreg_counter_done) begin
-                    com_insp_dest <= COM_INSP_DEST_SP_BOTH;
+                if (com_insp_dreg_counter_done | com_inp_data[33]) begin
                     com_insp_state <= COM_INSP_STATE_WRITE_REGS;
                     com_insp_dreg_count <= 0;
+
+                    //---------- begin inspection decision -----------//
+                    //bcast or EOF:
+                    if ((com_insp_dregs_eth_dst_mac == 48'hffffffffffff) || com_inp_data[33]) begin
+                        com_insp_dest <= COM_INSP_DEST_BOF;
+                    end
+
+                    //not IPv4/UDP:
+                    else if ((com_insp_dregs_eth_type != 16'h800) || (com_insp_dregs_ipv4_proto != 8'h11)) begin
+                        com_insp_dest <= COM_INSP_DEST_CPU;
+                    end
+
+                    //not my IP address:
+                    else if (com_insp_dregs_ipv4_dst_addr != my_ip_addr) begin
+                        com_insp_dest <= COM_INSP_DEST_EXT;
+                    end
+
+                    //UDP data port and VRT:
+                    else if ((com_insp_dregs_udp_dst_port == dsp0_udp_port) && (com_insp_dregs_vrt_size != 16'h0)) begin
+                        com_insp_dest <= COM_INSP_DEST_DSP;
+                        com_insp_dreg_count <= COM_INSP_DREGS_DSP_OFFSET;
+                    end
+
+                    //other:
+                    else begin
+                        com_insp_dest <= COM_INSP_DEST_CPU;
+                    end
+                    //---------- end inspection decision -------------//
+
                 end
                 else begin
                     com_insp_dreg_count <= com_insp_dreg_count_next;
@@ -531,28 +560,41 @@ module packet_router
     end
 
     ////////////////////////////////////////////////////////////////////
-    // Serdes crossbar output source
-    //   - combine slow-path data with fast-path other data
-    //   - slow-path data is duplicated to this and CPU out
+    // Splitter and output muxes for the bof packets
+    //   - split the bof packets into two streams
+    //   - mux split packets into cpu out and ext out
     ////////////////////////////////////////////////////////////////////
 
-    //dummy signals to join the the splitter and mux below
-    wire [35:0] _sp_split_to_mux_data;
-    wire        _sp_split_to_mux_valid;
-    wire        _sp_split_to_mux_ready;
+    //dummy signals to join the the splitter and muxes below
+    wire [35:0] _split_to_ext_data,  _split_to_cpu_data,  _cpu_out_data;
+    wire        _split_to_ext_valid, _split_to_cpu_valid, _cpu_out_valid;
+    wire        _split_to_ext_ready, _split_to_cpu_ready, _cpu_out_ready;
 
-    splitter36 crs_out_src0(
+    splitter36 bof_out_splitter(
         .clk(stream_clk), .rst(stream_rst), .clr(stream_clr),
-        .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready),
-        .out0_data(_sp_split_to_mux_data),    .out0_valid(_sp_split_to_mux_valid),    .out0_ready(_sp_split_to_mux_ready),
-        .out1_data(cpu_out_data),             .out1_valid(cpu_out_valid),             .out1_ready(cpu_out_ready)
+        .inp_data(com_insp_out_bof_data), .inp_valid(com_insp_out_bof_valid), .inp_ready(com_insp_out_bof_ready),
+        .out0_data(_split_to_ext_data),   .out0_valid(_split_to_ext_valid),   .out0_ready(_split_to_ext_ready),
+        .out1_data(_split_to_cpu_data),   .out1_valid(_split_to_cpu_valid),   .out1_ready(_split_to_cpu_ready)
+    );
+
+    fifo36_mux ext_out_mux(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(com_insp_out_ext_data), .src0_rdy_i(com_insp_out_ext_valid), .dst0_rdy_o(com_insp_out_ext_ready),
+        .data1_i(_split_to_ext_data),    .src1_rdy_i(_split_to_ext_valid),    .dst1_rdy_o(_split_to_ext_ready),
+        .data_o(ext_out_data),           .src_rdy_o(ext_out_valid),           .dst_rdy_i(ext_out_ready)
+    );
+
+    fifo36_mux cpu_out_mux(
+        .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
+        .data0_i(com_insp_out_cpu_data), .src0_rdy_i(com_insp_out_cpu_valid), .dst0_rdy_o(com_insp_out_cpu_ready),
+        .data1_i(_split_to_cpu_data),    .src1_rdy_i(_split_to_cpu_valid),    .dst1_rdy_o(_split_to_cpu_ready),
+        .data_o(_cpu_out_data),          .src_rdy_o(_cpu_out_valid),          .dst_rdy_i(_cpu_out_ready)
     );
 
-    fifo36_mux crs_out_src1(
+    fifo_cascade #(.WIDTH(36), .SIZE(9/*512 lines plenty for short pkts*/)) cpu_out_fifo (
         .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready),
-        .data1_i(_sp_split_to_mux_data),      .src1_rdy_i(_sp_split_to_mux_valid),      .dst1_rdy_o(_sp_split_to_mux_ready),
-        .data_o(crs_out_data),                .src_rdy_o(crs_out_valid),                .dst_rdy_i(crs_out_ready)
+        .datain(_cpu_out_data), .src_rdy_i(_cpu_out_valid), .dst_rdy_o(_cpu_out_ready),
+        .dataout(cpu_out_data), .src_rdy_o(cpu_out_valid),  .dst_rdy_i(cpu_out_ready)
     );
 
     ////////////////////////////////////////////////////////////////////
@@ -607,7 +649,7 @@ module packet_router
 
     fifo36_mux com_out_mux(
         .clk(stream_clk), .reset(stream_rst), .clear(stream_clr),
-        .data0_i(crs_inp_data),  .src0_rdy_i(crs_inp_valid),  .dst0_rdy_o(crs_inp_ready),
+        .data0_i(ext_inp_data),  .src0_rdy_i(ext_inp_valid),  .dst0_rdy_o(ext_inp_ready),
         .data1_i(_com_out_data), .src1_rdy_i(_com_out_valid), .dst1_rdy_o(_com_out_ready),
         .data_o(com_out_data),   .src_rdy_o(com_out_valid),   .dst_rdy_i(com_out_ready)
     );
@@ -630,16 +672,16 @@ module packet_router
         cpu_out_ready, cpu_out_valid,
 
         //inspector interfaces (8)
-        com_inp_ready, com_inp_valid,
-        com_insp_out_fp_this_ready, com_insp_out_fp_this_valid,
-        com_insp_out_fp_other_ready, com_insp_out_fp_other_valid,
-        com_insp_out_sp_both_ready, com_insp_out_sp_both_valid,
+        com_insp_out_dsp_ready, com_insp_out_dsp_valid,
+        com_insp_out_ext_ready, com_insp_out_ext_valid,
+        com_insp_out_cpu_ready, com_insp_out_cpu_valid,
+        com_insp_out_bof_ready, com_insp_out_bof_valid,
 
         //other interfaces (8)
-        crs_inp_ready, crs_inp_valid,
+        ext_inp_ready, ext_inp_valid,
         com_out_ready, com_out_valid,
-        crs_out_ready, crs_out_valid,
-        _sp_split_to_mux_ready, _sp_split_to_mux_valid
+        ext_out_ready, ext_out_valid,
+        com_inp_ready, com_inp_valid
     };
 
 endmodule // packet_router
diff --git a/usrp2/timing/time_64bit.v b/usrp2/timing/time_64bit.v
index 51c006962..33eb2b25a 100644
--- a/usrp2/timing/time_64bit.v
+++ b/usrp2/timing/time_64bit.v
@@ -3,27 +3,41 @@
 module time_64bit
   #(parameter TICKS_PER_SEC = 32'd100000000,
     parameter BASE = 0)
-    (input clk, input rst,
-     input set_stb, input [7:0] set_addr, input [31:0] set_data,  
-     input pps,
-     output [63:0] vita_time, output pps_int
-     );
-
+   (input clk, input rst,
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,  
+    input pps,
+    output [63:0] vita_time, output pps_int,
+    input exp_time_in, output exp_time_out,
+    output [31:0] debug
+    );
+   
    localparam 	   NEXT_SECS = 0;   
    localparam 	   NEXT_TICKS = 1;
    localparam      PPS_POLSRC = 2;
    localparam      PPS_IMM = 3;
    localparam      TPS = 4;
+   localparam      MIMO_SYNC = 5;
    
    reg [31:0] 	   seconds, ticks;
    wire 	   end_of_second;
    assign 	   vita_time = {seconds,ticks};
+   wire [63:0] 	   vita_time_rcvd;
    
    wire [31:0] 	   next_ticks_preset, next_seconds_preset;
    wire [31:0] 	   ticks_per_sec_reg;
    wire 	   set_on_pps_trig;
    reg 		   set_on_next_pps;
    wire 	   pps_polarity, pps_source, set_imm;
+   reg [1:0] 	   pps_del;
+   reg 		   pps_reg_p, pps_reg_n, pps_reg;
+   wire 	   pps_edge;
+
+   reg [15:0] 	   sync_counter;
+   wire 	   sync_rcvd;
+   wire [31:0] 	   mimo_secs, mimo_ticks;
+   wire 	   mimo_sync_now;
+   wire 	   mimo_sync;
+   wire [7:0] 	   sync_delay;
    
    setting_reg #(.my_addr(BASE+NEXT_TICKS)) sr_next_ticks
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
@@ -45,10 +59,10 @@ module time_64bit
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(ticks_per_sec_reg),.changed());
 
-   reg [1:0] 	   pps_del;
-   reg 		   pps_reg_p, pps_reg_n, pps_reg;
-   wire 	   pps_edge;
-   
+   setting_reg #(.my_addr(BASE+MIMO_SYNC), .at_reset(0), .width(9)) sr_mimosync
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({mimo_sync,sync_delay}),.changed());
+
    always @(posedge clk)  pps_reg_p <= pps;   
    always @(negedge clk)  pps_reg_n <= pps;
    always @* pps_reg <= pps_polarity ? pps_reg_p : pps_reg_n;
@@ -82,6 +96,11 @@ module time_64bit
 	  seconds <= next_seconds_preset;
 	  ticks <= next_ticks_preset;
        end
+     else if(mimo_sync_now)
+       begin
+	  seconds <= mimo_secs;
+	  ticks <= mimo_ticks;
+       end
      else if(ticks_plus_one == ticks_per_sec_reg)
        begin
 	  seconds <= seconds + 1;
@@ -91,5 +110,36 @@ module time_64bit
        ticks <= ticks_plus_one;
 
    assign pps_int = pps_edge;
+
+   // MIMO Connector Time Sync
+   wire send_sync = (sync_counter == 59999); // X % 10 = 9
+
+   always @(posedge clk)
+     if(rst)
+       sync_counter <= 0;
+     else
+       if(send_sync)
+	 sync_counter <= 0;
+       else
+	 sync_counter <= sync_counter + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time),
+      .send_sync(send_sync),
+      .exp_time_out(exp_time_out) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .vita_time(vita_time_rcvd),
+      .sync_rcvd(sync_rcvd),
+      .exp_time_in(exp_time_in) );
+
+   assign mimo_secs = vita_time_rcvd[63:32];
+   assign mimo_ticks = vita_time_rcvd[31:0] + {16'd0,sync_delay};
+   assign mimo_sync_now = mimo_sync & sync_rcvd & (mimo_ticks <= TICKS_PER_SEC);
+
+   assign debug = { { 24'b0} ,
+		    { 2'b0, exp_time_in, exp_time_out, mimo_sync, mimo_sync_now, sync_rcvd, send_sync} };
    
 endmodule // time_64bit
diff --git a/usrp2/timing/time_receiver.v b/usrp2/timing/time_receiver.v
index 8e7d3f1ea..fd8651d29 100644
--- a/usrp2/timing/time_receiver.v
+++ b/usrp2/timing/time_receiver.v
@@ -1,9 +1,9 @@
 
 module time_receiver
   (input clk, input rst,
-   output [31:0] master_time,
-   output sync_rcvd,
-   input exp_pps_in);
+   output reg [63:0] vita_time,
+   output reg sync_rcvd,
+   input exp_time_in);
 
    wire       code_err, disp_err, dispout, complete_word;
    reg 	      disp_reg;
@@ -13,7 +13,7 @@ module time_receiver
    reg [8:0]  dataout_reg;
  	      
    always @(posedge clk)
-     shiftreg <= {exp_pps_in, shiftreg[9:1]};
+     shiftreg <= {exp_time_in, shiftreg[9:1]};
 
    localparam COMMA_0 = 10'h283;
    localparam COMMA_1 = 10'h17c;
@@ -55,40 +55,76 @@ module time_receiver
    localparam STATE_T1 = 2;
    localparam STATE_T2 = 3;
    localparam STATE_T3 = 4;
+   localparam STATE_T4 = 5;
+   localparam STATE_T5 = 6;
+   localparam STATE_T6 = 7;
+   localparam STATE_T7 = 8;
+   localparam STATE_TAIL = 9;
    
    localparam HEAD = 9'h13c;   
-
-   reg [7:0]  clock_a, clock_b, clock_c;
-   reg [2:0]  state;
+   localparam TAIL = 9'h1F7;
+   
+   reg [3:0]  state;
    
    always @(posedge clk)
      if(rst)
        state <= STATE_IDLE;
      else if(complete_word)
-       case(state)
-	 STATE_IDLE :
-	   if(dataout_reg == HEAD)
-	     state <= STATE_T0;
-	 STATE_T0 :
-	   begin
-	      clock_a <= dataout_reg[7:0];
-	      state <= STATE_T1;
-	   end
-	 STATE_T1 :
-	   begin
-	      clock_b <= dataout_reg[7:0];
-	      state <= STATE_T2;
-	   end
-	 STATE_T2 :
-	   begin
-	      clock_c <= dataout_reg[7:0];
-	      state <= STATE_T3;
-	   end
-	 STATE_T3 :
-	   state <= STATE_IDLE;
-       endcase // case(state)
-
-   assign master_time =  {clock_a, clock_b, clock_c, dataout_reg[7:0]};
-   assign sync_rcvd = (complete_word & (state == STATE_T3));
-
+       if(code_err | disp_err)
+	 state <= STATE_IDLE;
+       else
+	 case(state)
+	   STATE_IDLE :
+	     if(dataout_reg == HEAD)
+	       state <= STATE_T0;
+	   STATE_T0 :
+	     begin
+		vita_time[63:56] <= dataout_reg[7:0];
+		state <= STATE_T1;
+	     end
+	   STATE_T1 :
+	     begin
+		vita_time[55:48] <= dataout_reg[7:0];
+		state <= STATE_T2;
+	     end
+	   STATE_T2 :
+	     begin
+		vita_time[47:40] <= dataout_reg[7:0];
+		state <= STATE_T3;
+	     end
+	   STATE_T3 :
+	     begin
+		vita_time[39:32] <= dataout_reg[7:0];
+		state <= STATE_T4;
+	     end
+	   STATE_T4 :
+	     begin
+		vita_time[31:24] <= dataout_reg[7:0];
+		state <= STATE_T5;
+	     end
+	   STATE_T5 :
+	     begin
+		vita_time[23:16] <= dataout_reg[7:0];
+		state <= STATE_T6;
+	     end
+	   STATE_T6 :
+	     begin
+		vita_time[15:8] <= dataout_reg[7:0];
+		state <= STATE_T7;
+	     end
+	   STATE_T7 :
+	     begin
+		vita_time[7:0] <= dataout_reg[7:0];
+		state <= STATE_TAIL;
+	     end
+	   STATE_TAIL :
+	     state <= STATE_IDLE;
+	 endcase // case(state)
+   
+   always @(posedge clk)
+     if(rst)
+       sync_rcvd <= 0;
+     else
+       sync_rcvd <= (complete_word & (state == STATE_TAIL) & (dataout_reg[8:0] == TAIL));
+   
 endmodule // time_sender
diff --git a/usrp2/timing/time_sender.v b/usrp2/timing/time_sender.v
index aa2fcbbdb..f4ee5226a 100644
--- a/usrp2/timing/time_sender.v
+++ b/usrp2/timing/time_sender.v
@@ -2,23 +2,23 @@
 
 module time_sender
   (input clk, input rst,
-   input [31:0] master_time,
+   input [63:0] vita_time,
    input send_sync,
-   output exp_pps_out);
+   output reg exp_time_out);
 
    reg [7:0] datain;
    reg 	     k;
    wire [9:0] dataout;
-   reg [9:0] dataout_reg;
-   reg 	     disp_reg;
-   wire      disp, new_word;
+   reg [9:0]  dataout_reg;
+   reg 	      disp_reg;
+   wire       disp, new_word;
+   reg [4:0]  state;
+   reg [3:0]  bit_count;
    
    encode_8b10b encode_8b10b 
      (.datain({k,datain}),.dispin(disp_reg),
       .dataout(dataout),.dispout(disp));
 
-   assign    exp_pps_out = dataout_reg[0];
-
    always @(posedge clk)
      if(rst)
        disp_reg <= 0;
@@ -33,9 +33,9 @@ module time_sender
      else
        dataout_reg <= {1'b0,dataout_reg[9:1]};
    
-   reg [4:0] state;
-   reg [3:0] bit_count;
-
+   always @(posedge clk)
+     exp_time_out <= dataout_reg[0];
+   
    assign    new_word = (bit_count == 9);
    
    always @(posedge clk)
@@ -52,17 +52,23 @@ module time_sender
    localparam SEND_T1 = 3;
    localparam SEND_T2 = 4;
    localparam SEND_T3 = 5;
+   localparam SEND_T4 = 6;
+   localparam SEND_T5 = 7;
+   localparam SEND_T6 = 8;
+   localparam SEND_T7 = 9;
+   localparam SEND_TAIL = 10;
 
    localparam COMMA = 8'hBC;
    localparam HEAD = 8'h3C;
-
-   reg [31:0] master_time_reg;
+   localparam TAIL = 8'hF7;
+   
+   reg [63:0] vita_time_reg;
    
    always @(posedge clk)
      if(rst)
-       master_time_reg <= 0;
+       vita_time_reg <= 0;
      else if(send_sync)
-       master_time_reg <= master_time;
+       vita_time_reg <= vita_time;
    
    always @(posedge clk)
      if(rst)
@@ -84,27 +90,51 @@ module time_sender
 	     end
 	   SEND_T0 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[31:24] };
+		{k,datain} <= {1'b0, vita_time_reg[63:56] };
 		state <= SEND_T1;
 	     end
 	   SEND_T1 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[23:16]};
+		{k,datain} <= {1'b0, vita_time_reg[55:48]};
 		state <= SEND_T2;
 	     end
 	   SEND_T2 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[15:8]};
+		{k,datain} <= {1'b0, vita_time_reg[47:40]};
 		state <= SEND_T3;
 	     end
 	   SEND_T3 :
 	     begin
-		{k,datain} <= {1'b0, master_time_reg[7:0]};
+		{k,datain} <= {1'b0, vita_time_reg[39:32]};
+		state <= SEND_T4;
+	     end
+	   SEND_T4 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[31:24]};
+		state <= SEND_T5;
+	     end
+	   SEND_T5 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[23:16]};
+		state <= SEND_T6;
+	     end
+	   SEND_T6 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[15:8]};
+		state <= SEND_T7;
+	     end
+	   SEND_T7 :
+	     begin
+		{k,datain} <= {1'b0, vita_time_reg[7:0]};
+		state <= SEND_TAIL;
+	     end
+	   SEND_TAIL :
+	     begin
+		{k,datain} <= {1'b1, TAIL};
 		state <= SEND_IDLE;
 	     end
 	   default :
 	     state <= SEND_IDLE;
 	 endcase // case(state)
    
-   
 endmodule // time_sender
diff --git a/usrp2/timing/time_transfer_tb.v b/usrp2/timing/time_transfer_tb.v
index 2b75c60bd..0c164f82c 100644
--- a/usrp2/timing/time_transfer_tb.v
+++ b/usrp2/timing/time_transfer_tb.v
@@ -18,12 +18,12 @@ module time_transfer_tb();
    
    initial #100000000 $finish;
 
-   wire exp_pps, pps, pps_rcv;
-   wire [31:0] master_clock_rcv;
-   reg [31:0]  master_clock = 0;
-   reg [31:0]  counter = 0;
+   wire exp_time, pps, pps_rcv;
+   wire [63:0] vita_time_rcv;
+   reg [63:0]  vita_time = 0;
+   reg [63:0]  counter = 0;
 
-   localparam  PPS_PERIOD = 109;
+   localparam  PPS_PERIOD = 439; // PPS_PERIOD % 10 must = 9
    always @(posedge clk)
      if(counter == PPS_PERIOD)
        counter <= 0;
@@ -32,19 +32,19 @@ module time_transfer_tb();
    assign      pps = (counter == (PPS_PERIOD-1));
    
    always @(posedge clk)
-     master_clock <= master_clock + 1;
+     vita_time <= vita_time + 1;
    
    time_sender time_sender
      (.clk(clk),.rst(rst),
-      .master_clock(master_clock),
-      .pps(pps),
-      .exp_pps_out(exp_pps) );
+      .vita_time(vita_time),
+      .send_sync(pps),
+      .exp_time_out(exp_time) );
 
    time_receiver time_receiver
      (.clk(clk),.rst(rst),
-      .master_clock(master_clock_rcv),
-      .pps(pps_rcv),
-      .exp_pps_in(exp_pps) );
+      .vita_time(vita_time_rcv),
+      .sync_rcvd(pps_rcv),
+      .exp_time_in(exp_time) );
 
-   wire [31:0] delta = master_clock - master_clock_rcv;
+   wire [31:0] delta = vita_time - vita_time_rcv;
 endmodule // time_transfer_tb
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index 68c296b9b..05ada2476 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -6,7 +6,7 @@
 # Project Setup
 ##################################################
 TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build$(ISE))
+BUILD_DIR = $(abspath build)
 
 ##################################################
 # Include other makefiles
@@ -24,6 +24,8 @@ include ../../vrt/Makefile.srcs
 include ../../udp/Makefile.srcs
 include ../../coregen/Makefile.srcs
 include ../../extram/Makefile.srcs
+include ../../extramfifo/Makefile.srcs
+
 
 ##################################################
 # Project Properties
diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
deleted file mode 100644
index 99effb038..000000000
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ /dev/null
@@ -1,99 +0,0 @@
-#
-# Copyright 2008 Ettus Research LLC
-#
-
-##################################################
-# Project Setup
-##################################################
-TOP_MODULE = u2_rev3
-BUILD_DIR = $(abspath build-udp$(ISE))
-
-##################################################
-# Include other makefiles
-##################################################
-
-include ../Makefile.common
-include ../../fifo/Makefile.srcs
-include ../../control_lib/Makefile.srcs
-include ../../sdr_lib/Makefile.srcs
-include ../../serdes/Makefile.srcs
-include ../../simple_gemac/Makefile.srcs
-include ../../timing/Makefile.srcs
-include ../../opencores/Makefile.srcs
-include ../../vrt/Makefile.srcs
-include ../../udp/Makefile.srcs
-include ../../coregen/Makefile.srcs
-include ../../extram/Makefile.srcs
-include ../../extramfifo/Makefile.srcs
-
-
-##################################################
-# Project Properties
-##################################################
-PROJECT_PROPERTIES = \
-family Spartan3 \
-device xc3s2000 \
-package fg456 \
-speed -5 \
-top_level_module_type "HDL" \
-synthesis_tool "XST (VHDL/Verilog)" \
-simulator "ISE Simulator (VHDL/Verilog)" \
-"Preferred Language" "Verilog" \
-"Enable Message Filtering" FALSE \
-"Display Incremental Messages" FALSE 
-
-##################################################
-# Sources
-##################################################
-TOP_SRCS = \
-u2_core_udp.v \
-u2_rev3.v \
-u2_rev3.ucf
-
-SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
-$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
-$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
-$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
-
-##################################################
-# Process Properties
-##################################################
-SYNTHESIZE_PROPERTIES = \
-"Number of Clock Buffers" 8 \
-"Pack I/O Registers into IOBs" Yes \
-"Optimization Effort" High \
-"Optimize Instantiated Primitives" TRUE \
-"Register Balancing" Yes \
-"Use Clock Enable" Auto \
-"Use Synchronous Reset" Auto \
-"Use Synchronous Set" Auto
-
-TRANSLATE_PROPERTIES = \
-"Macro Search Path" "$(shell pwd)/../../coregen/"
-
-MAP_PROPERTIES = \
-"Allow Logic Optimization Across Hierarchy" TRUE \
-"Map to Input Functions" 4 \
-"Optimization Strategy (Cover Mode)" Speed \
-"Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs" \
-"Perform Timing-Driven Packing and Placement" TRUE \
-"Map Effort Level" High \
-"Extra Effort" Normal \
-"Combinatorial Logic Optimization" TRUE \
-"Register Duplication" TRUE
-
-PLACE_ROUTE_PROPERTIES = \
-"Place & Route Effort Level (Overall)" High 
-
-STATIC_TIMING_PROPERTIES = \
-"Number of Paths in Error/Verbose Report" 10 \
-"Report Type" "Error Report"
-
-GEN_PROG_FILE_PROPERTIES = \
-"Configuration Rate" 6 \
-"Create Binary Configuration File" TRUE \
-"Done (Output Events)" 5 \
-"Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 
-
-SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index 26e2cc4ab..fff7ab914 100644
--- a/usrp2/top/u2_rev3/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -17,8 +17,8 @@ module u2_core
    output [1:0] debug_clk,
 
    // Expansion
-   input exp_pps_in,
-   output exp_pps_out,
+   input exp_time_in,
+   output exp_time_out,
    
    // GMII
    //   GMII-CTRL
@@ -440,7 +440,7 @@ module u2_core
    wb_readback_mux buff_pool_status
      (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s5_stb),
       .wb_adr_i(s5_adr), .wb_dat_o(s5_dat_i), .wb_ack_o(s5_ack),
-      
+
       .word00(32'b0),.word01(32'b0),.word02(32'b0),.word03(32'b0),
       .word04(32'b0),.word05(32'b0),.word06(32'b0),.word07(32'b0),
       .word08(status),.word09({sim_mode,27'b0,clock_divider[3:0]}),.word10(vita_time[63:32]),
@@ -730,10 +730,14 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
 
+   wire [31:0] 	 debug_sync;
+
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
-   
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out),
+      .debug(debug_sync));
+
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
   
diff --git a/usrp2/top/u2_rev3/u2_rev3.ucf b/usrp2/top/u2_rev3/u2_rev3.ucf
index 6e0caedd5..8017f61ff 100644
--- a/usrp2/top/u2_rev3/u2_rev3.ucf
+++ b/usrp2/top/u2_rev3/u2_rev3.ucf
@@ -40,10 +40,10 @@ NET "debug_clk[0]"  LOC = "N4"  ;
 NET "debug_clk[1]"  LOC = "M1"  ;
 NET "uart_tx_o"  LOC = "C7"  ;
 NET "uart_rx_i"  LOC = "A3"  ;
-NET "exp_pps_in_p"  LOC = "V3"  ; 
-NET "exp_pps_in_n"  LOC = "V4"  ; 
-NET "exp_pps_out_p"  LOC = "V1"  ; 
-NET "exp_pps_out_n"  LOC = "V2"  ; 
+NET "exp_time_in_p"  LOC = "V3"  ; 
+NET "exp_time_in_n"  LOC = "V4"  ; 
+NET "exp_time_out_p"  LOC = "V1"  ; 
+NET "exp_time_out_n"  LOC = "V2"  ; 
 NET "GMII_COL"  LOC = "U16"  ; 
 NET "GMII_CRS"  LOC = "U17"  ; 
 NET "GMII_TXD[0]"  LOC = "W14"  |IOSTANDARD = LVCMOS25  |DRIVE = 12  |SLEW = FAST ;
diff --git a/usrp2/top/u2_rev3/u2_rev3.v b/usrp2/top/u2_rev3/u2_rev3.v
index 4f7f9bf1a..f2bba6c50 100644
--- a/usrp2/top/u2_rev3/u2_rev3.v
+++ b/usrp2/top/u2_rev3/u2_rev3.v
@@ -11,10 +11,10 @@ module u2_rev3
    input uart_rx_i,
    
    // Expansion
-   input exp_pps_in_p, // Diff
-   input exp_pps_in_n, // Diff
-   output exp_pps_out_p, // Diff 
-   output exp_pps_out_n, // Diff 
+   input exp_time_in_p, // Diff
+   input exp_time_in_n, // Diff
+   output exp_time_out_p, // Diff 
+   output exp_time_out_n, // Diff 
    
    // GMII
    //   GMII-CTRL
@@ -181,13 +181,13 @@ module u2_rev3
    wire 	cpld_clock_buf;
    BUFG cpld_clock_BUF (.O(cpld_clock_buf),.I(cpld_clock));
    
-   wire 	exp_pps_in;
-   IBUFDS exp_pps_in_pin (.O(exp_pps_in),.I(exp_pps_in_p),.IB(exp_pps_in_n));
-   defparam 	exp_pps_in_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_in;
+   IBUFDS exp_time_in_pin (.O(exp_time_in),.I(exp_time_in_p),.IB(exp_time_in_n));
+   defparam 	exp_time_in_pin.IOSTANDARD = "LVDS_25";
    
-   wire 	exp_pps_out;
-   OBUFDS exp_pps_out_pin (.O(exp_pps_out_p),.OB(exp_pps_out_n),.I(exp_pps_out));
-   defparam 	exp_pps_out_pin.IOSTANDARD = "LVDS_25";
+   wire 	exp_time_out;
+   OBUFDS exp_time_out_pin (.O(exp_time_out_p),.OB(exp_time_out_n),.I(exp_time_out));
+   defparam 	exp_time_out_pin.IOSTANDARD = "LVDS_25";
 
    reg [5:0] 	clock_ready_d;
    always @(posedge clk_fpga)
@@ -480,8 +480,8 @@ module u2_rev3
 	     .leds		(leds_int),
 	     .debug		(debug[31:0]),
 	     .debug_clk		(debug_clk[1:0]),
-	     .exp_pps_in	(exp_pps_in),
-	     .exp_pps_out	(exp_pps_out),
+	     .exp_time_in	(exp_time_in),
+	     .exp_time_out	(exp_time_out),
 	     .GMII_COL		(GMII_COL),
 	     .GMII_CRS		(GMII_CRS),
 	     .GMII_TXD		(GMII_TXD_unreg[7:0]),
diff --git a/usrp2/top/u2plus/u2plus.ucf b/usrp2/top/u2plus/u2plus.ucf
index 25267a67e..5fbe55c26 100755
--- a/usrp2/top/u2plus/u2plus.ucf
+++ b/usrp2/top/u2plus/u2plus.ucf
@@ -158,7 +158,7 @@ NET "RXD<2>"  LOC = "AF15"  ;
 NET "RXD<1>"  LOC = "AD12"  ;
 
 ## AD9510
-NET "CLK_STATUS"  LOC = "AD22"  ;
+NET "clk_status"  LOC = "AD22"  ;
 NET "CLK_FUNC"  LOC = "AC21"  ;
 NET "clk_sel<0>"  LOC = "AE21"  ;
 NET "clk_sel<1>"  LOC = "AD21"  ;
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v
index 270655a8d..c0140e989 100644
--- a/usrp2/top/u2plus/u2plus.v
+++ b/usrp2/top/u2plus/u2plus.v
@@ -44,7 +44,7 @@ module u2plus
    output [1:0] clk_en,
    output [1:0] clk_sel,
    input CLK_FUNC,        // FIXME is an input to control the 9510
-   input CLK_STATUS,
+   input clk_status,
 
    inout SCL, inout SDA,   // I2C
 
@@ -357,8 +357,8 @@ module u2plus
 		     .leds		(leds_int),
 		     .debug		(debug[31:0]),
 		     .debug_clk		(debug_clk[1:0]),
-		     .exp_pps_in	(exp_time_in),
-		     .exp_pps_out	(exp_time_out),
+		     .exp_time_in	(exp_time_in),
+		     .exp_time_out	(exp_time_out),
 		     .GMII_COL		(GMII_COL),
 		     .GMII_CRS		(GMII_CRS),
 		     .GMII_TXD		(GMII_TXD_unreg[7:0]),
diff --git a/usrp2/top/u2plus/u2plus_core.v b/usrp2/top/u2plus/u2plus_core.v
index 8426826e2..4e0b190ef 100644
--- a/usrp2/top/u2plus/u2plus_core.v
+++ b/usrp2/top/u2plus/u2plus_core.v
@@ -16,8 +16,8 @@ module u2plus_core
    output [1:0] debug_clk,
 
    // Expansion
-   input exp_pps_in,
-   output exp_pps_out,
+   input exp_time_in,
+   output exp_time_out,
    
    // GMII
    //   GMII-CTRL
@@ -683,7 +683,8 @@ module u2plus_core
 
    time_64bit #(.TICKS_PER_SEC(32'd100000000),.BASE(SR_TIME64)) time_64bit
      (.clk(dsp_clk), .rst(dsp_rst), .set_stb(set_stb_dsp), .set_addr(set_addr_dsp), .set_data(set_data_dsp),
-      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int));
+      .pps(pps_in), .vita_time(vita_time), .pps_int(pps_int),
+      .exp_time_in(exp_time_in), .exp_time_out(exp_time_out));
    
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
diff --git a/usrp2/vrt/vita_tx_control.v b/usrp2/vrt/vita_tx_control.v
index 20ad6b995..ab6da8bd0 100644
--- a/usrp2/vrt/vita_tx_control.v
+++ b/usrp2/vrt/vita_tx_control.v
@@ -40,7 +40,21 @@ module vita_tx_control
    time_compare 
      time_compare (.time_now(vita_time), .trigger_time(send_time), 
 		   .now(now), .early(early), .late(late), .too_early());
+
+   reg 	       late_qual, late_del;
+
+   always @(posedge clk)
+     if(reset | clear)
+       late_del <= 0;
+     else
+       late_del <= late;
    
+   always @(posedge clk)
+     if(reset | clear)
+       late_qual <= 0;
+     else
+       late_qual <= (sample_fifo_src_rdy_i & ~sample_fifo_dst_rdy_o);
+      
    localparam IBS_IDLE = 0;
    localparam IBS_RUN = 1;  // FIXME do we need this?
    localparam IBS_CONT_BURST = 2;
@@ -87,7 +101,7 @@ module vita_tx_control
 	       end
 	     else if(~send_at | now)
 	       ibs_state <= IBS_RUN;
-	     else if(late | too_early)
+	     else if((late_qual & late_del) | too_early)
 	       begin
 		  ibs_state <= IBS_ERROR;
 		  error_code <= CODE_TIME_ERROR;
@@ -166,7 +180,7 @@ module vita_tx_control
      else
        packet_consumed <= eop & sample_fifo_src_rdy_i & sample_fifo_dst_rdy_o;
    
-   assign debug = { { now,early,late,ack,eop,eob,sob,send_at },
+   assign debug = { { now,late_qual,late_del,ack,eop,eob,sob,send_at },
 		    { sample_fifo_src_rdy_i, sample_fifo_dst_rdy_o, strobe, run, error, ibs_state[2:0] },
 		    { 8'b0 },
 		    { 8'b0 } };