Added a bunch of debug signals.

4 files changed, 19 insertions, 9 deletions

diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index c6a64fc65..b17fde10b 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -37,7 +37,8 @@ module ext_fifo
      output dst_rdy_o,               // not FULL
      output [INT_WIDTH-1:0] dataout,
      output src_rdy_o,               // not EMPTY
-     input dst_rdy_i                 // READ
+     input dst_rdy_i,                 // READ
+     output reg [31:0] debug
      );
 
    wire [EXT_WIDTH-1:0] write_data;
@@ -46,7 +47,8 @@ module ext_fifo
    wire 	    almost_full2, full2, empty2;
    wire [INT_WIDTH-1:0] data_to_fifo;
    wire [INT_WIDTH-1:0] data_from_fifo;
-
+   wire [FIFO_DEPTH-1:0] capacity;
+		
    
    // FIFO buffers data from UDP engine into external FIFO clock domain.
    fifo_xlnx_512x36_2clk_36to18 fifo_xlnx_512x36_2clk_36to18_i1 (
@@ -88,7 +90,8 @@ module ext_fifo
 	   .space_avail(space_avail),
 	   .read_data(read_data),
 	   .read_strobe(~almost_full2),
-	   .data_avail(data_avail)
+	   .data_avail(data_avail),
+	   .capacity(capacity)
 	   );
 `endif // !`ifdef NO_EXT_FIFO
    
@@ -107,5 +110,10 @@ module ext_fifo
 								 .empty(empty2));
    assign  src_rdy_o = ~empty2;
 
+   always @ (posedge int_clk)
+     debug[31:16] = {12'h0,empty2,full1,dst_rdy_i,src_rdy_i };
+   
+   always @ (posedge ext_clk)
+     debug[15:0] = {3'h0,empty1,space_avail,data_avail,full2,almost_full2,capacity[7:0] };
 
 endmodule // ext_fifo
diff --git a/usrp2/extramfifo/ext_fifo_tb.cmd b/usrp2/extramfifo/ext_fifo_tb.cmd
index b0ab830dc..521f88f21 100644
--- a/usrp2/extramfifo/ext_fifo_tb.cmd
+++ b/usrp2/extramfifo/ext_fifo_tb.cmd
@@ -1,6 +1,7 @@
 /opt/Xilinx/12.1/ISE_DS/ISE/verilog/src/glbl.v
 -y .
 -y ../coregen/
+-y ../fifo
 -y ../models
 -y /home/ianb/usrp-fpga/usrp2/sdr_lib
 -y /home/ianb/usrp-fpga/usrp2/control_lib
diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index c2811c833..f8ea5330b 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -171,7 +171,7 @@ module u2_core
    wire [31:0] 	atr_lines;
 
    wire [31:0] 	debug_rx, debug_mac, debug_mac0, debug_mac1, debug_tx_dsp, debug_txc,
-		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp;
+		debug_serdes0, debug_serdes1, debug_serdes2, debug_rx_dsp, debug_udp, debug_extfifo;
 
    wire [15:0] 	ser_rx_occ, ser_tx_occ, dsp_rx_occ, dsp_tx_occ, eth_rx_occ, eth_tx_occ, eth_rx_occ2;
    wire 	ser_rx_full, ser_tx_full, dsp_rx_full, dsp_tx_full, eth_rx_full, eth_tx_full, eth_rx_full2;
@@ -669,7 +669,8 @@ module u2_core
 	.dst_rdy_o(rd1_ready_i),               // not FULL
 	.dataout(tx_data),
 	.src_rdy_o(tx_src_rdy),               // not EMPTY
-	.dst_rdy_i(tx_dst_rdy)
+	.dst_rdy_i(tx_dst_rdy),
+	.debug(debug_extfifo)
 	);
 
    vita_tx_chain #(.BASE_CTRL(SR_TX_CTRL), .BASE_DSP(SR_TX_DSP), 
@@ -712,8 +713,8 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
   
-   assign debug_clk = 2'b00;
-   assign debug = 32'd0;
+   assign debug_clk = {dsp_clk, clk_to_mac};
+   assign debug = debug_extfifo;
    assign debug_gpio_0 = 32'd0;
    assign debug_gpio_1 = 32'd0;
    
diff --git a/usrp2/vrt/vita_tx_deframer.v b/usrp2/vrt/vita_tx_deframer.v
index f9cd7d00d..b62507092 100644
--- a/usrp2/vrt/vita_tx_deframer.v
+++ b/usrp2/vrt/vita_tx_deframer.v
@@ -84,7 +84,7 @@ module vita_tx_deframer
 	  seqnum_err <= 0;
        end
      else 
-       if((vita_state == VITA_STORE) & fifo_space)
+       if((vita_state == VITA_STORE) & fifo_space ) //& src_rdy_i)
 	 if(eop)  
 	   if(has_trailer_reg)
 	     vita_state <= VITA_TRAILER;
@@ -183,7 +183,7 @@ module vita_tx_deframer
 	 3: sample_d <= data_i[31:0];
        endcase // case (vector_phase)
    
-   wire 		      store = (vita_state == VITA_STORE);
+   wire 		      store = (vita_state == VITA_STORE) ; //& src_rdy_i;
    fifo_short #(.WIDTH(FIFOWIDTH)) short_tx_q
      (.clk(clk), .reset(reset), .clear(clear),
       .datain(fifo_i), .src_rdy_i(store), .dst_rdy_o(fifo_space),