Merge branch 'master' into u1e_newbuild

Made so Makefile changes as well to get it to build
* master:
  new make works on ise12
  produces good bin files
  first attempt at cleaning up the build system
  get rid of debug stuff to help timing
  move u2_core into u2_rev3 directory to simplify directory structure and save headaches

Conflicts:
	usrp2/fifo/fifo36_to_fifo18.v
	usrp2/top/u2_rev3/Makefile
	usrp2/top/u2_rev3/Makefile.udp
	usrp2/top/u2_rev3/u2_core_udp.v

42 files changed, 672 insertions, 715 deletions

diff --git a/usrp2/control_lib/Makefile.srcs b/usrp2/control_lib/Makefile.srcs
new file mode 100644
index 000000000..095890d59
--- /dev/null
+++ b/usrp2/control_lib/Makefile.srcs
@@ -0,0 +1,47 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Control Lib Sources
+##################################################
+CONTROL_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../control_lib/, \
+CRC16_D16.v \
+atr_controller.v \
+bin2gray.v \
+dcache.v \
+decoder_3_8.v \
+dpram32.v \
+gray2bin.v \
+gray_send.v \
+icache.v \
+mux4.v \
+mux8.v \
+nsgpio.v \
+ram_2port.v \
+ram_harv_cache.v \
+ram_loader.v \
+setting_reg.v \
+settings_bus.v \
+settings_bus_crossclock.v \
+srl.v \
+system_control.v \
+wb_1master.v \
+wb_readback_mux.v \
+simple_uart.v \
+simple_uart_tx.v \
+simple_uart_rx.v \
+oneshot_2clk.v \
+sd_spi.v \
+sd_spi_wb.v \
+wb_bridge_16_32.v \
+reset_sync.v \
+priority_enc.v \
+pic.v \
+longfifo.v \
+shortfifo.v \
+medfifo.v \
+nsgpio16LE.v \
+settings_bus_16LE.v \
+atr_controller16.v \
+))
diff --git a/usrp2/coregen/Makefile.srcs b/usrp2/coregen/Makefile.srcs
new file mode 100644
index 000000000..7b29225ca
--- /dev/null
+++ b/usrp2/coregen/Makefile.srcs
@@ -0,0 +1,19 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Coregen Sources
+##################################################
+COREGEN_SRCS = $(abspath $(addprefix $(BASE_DIR)/../coregen/, \
+fifo_xlnx_2Kx36_2clk.v \
+fifo_xlnx_2Kx36_2clk.xco \
+fifo_xlnx_512x36_2clk.v \
+fifo_xlnx_512x36_2clk.xco \
+fifo_xlnx_64x36_2clk.v \
+fifo_xlnx_64x36_2clk.xco \
+fifo_xlnx_16x19_2clk.v \
+fifo_xlnx_16x19_2clk.xco \
+fifo_xlnx_16x40_2clk.v \
+fifo_xlnx_16x40_2clk.xco \
+))
diff --git a/usrp2/extram/Makefile.srcs b/usrp2/extram/Makefile.srcs
new file mode 100644
index 000000000..90be02142
--- /dev/null
+++ b/usrp2/extram/Makefile.srcs
@@ -0,0 +1,10 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Extram Sources
+##################################################
+EXTRAM_SRCS = $(abspath $(addprefix $(BASE_DIR)/../extram/, \
+wb_zbt16_b.v \
+))
diff --git a/usrp2/control_lib/newfifo/.gitignore b/usrp2/fifo/.gitignore
index 866f1faad..866f1faad 100644
--- a/usrp2/control_lib/newfifo/.gitignore
+++ b/usrp2/fifo/.gitignore
diff --git a/usrp2/fifo/Makefile.srcs b/usrp2/fifo/Makefile.srcs
new file mode 100644
index 000000000..22867da7e
--- /dev/null
+++ b/usrp2/fifo/Makefile.srcs
@@ -0,0 +1,23 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# FIFO Sources
+##################################################
+FIFO_SRCS = $(abspath $(addprefix $(BASE_DIR)/../fifo/, \
+buffer_int.v \
+buffer_pool.v \
+fifo_2clock.v \
+fifo_2clock_cascade.v \
+ll8_shortfifo.v \
+fifo_short.v \
+fifo_long.v \
+fifo_cascade.v \
+fifo36_to_ll8.v \
+ll8_to_fifo36.v \
+fifo19_to_ll8.v \
+ll8_to_fifo19.v \
+fifo36_to_fifo19.v \
+fifo19_to_fifo36.v \
+))
diff --git a/usrp2/control_lib/newfifo/buffer_int.v b/usrp2/fifo/buffer_int.v
index b45ed3532..b45ed3532 100644
--- a/usrp2/control_lib/newfifo/buffer_int.v
+++ b/usrp2/fifo/buffer_int.v
diff --git a/usrp2/control_lib/newfifo/buffer_int_tb.v b/usrp2/fifo/buffer_int_tb.v
index df54dcc0b..df54dcc0b 100644
--- a/usrp2/control_lib/newfifo/buffer_int_tb.v
+++ b/usrp2/fifo/buffer_int_tb.v
diff --git a/usrp2/control_lib/newfifo/buffer_pool.v b/usrp2/fifo/buffer_pool.v
index 41ac1deb3..41ac1deb3 100644
--- a/usrp2/control_lib/newfifo/buffer_pool.v
+++ b/usrp2/fifo/buffer_pool.v
diff --git a/usrp2/control_lib/newfifo/buffer_pool_tb.v b/usrp2/fifo/buffer_pool_tb.v
index 91a01d268..91a01d268 100644
--- a/usrp2/control_lib/newfifo/buffer_pool_tb.v
+++ b/usrp2/fifo/buffer_pool_tb.v
diff --git a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v b/usrp2/fifo/fifo19_to_fifo36.v
index 0e6bcea68..0e6bcea68 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_fifo36.v
+++ b/usrp2/fifo/fifo19_to_fifo36.v
diff --git a/usrp2/control_lib/newfifo/fifo19_to_ll8.v b/usrp2/fifo/fifo19_to_ll8.v
index 4707f7523..4707f7523 100644
--- a/usrp2/control_lib/newfifo/fifo19_to_ll8.v
+++ b/usrp2/fifo/fifo19_to_ll8.v
diff --git a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v b/usrp2/fifo/fifo36_to_fifo19.v
index 517a2a476..517a2a476 100644
--- a/usrp2/control_lib/newfifo/fifo36_to_fifo19.v
+++ b/usrp2/fifo/fifo36_to_fifo19.v
diff --git a/usrp2/control_lib/newfifo/fifo36_to_ll8.v b/usrp2/fifo/fifo36_to_ll8.v
index 9604d0e38..9604d0e38 100644
--- a/usrp2/control_lib/newfifo/fifo36_to_ll8.v
+++ b/usrp2/fifo/fifo36_to_ll8.v
diff --git a/usrp2/control_lib/newfifo/fifo_2clock.v b/usrp2/fifo/fifo_2clock.v
index 34c85ccb4..34c85ccb4 100644
--- a/usrp2/control_lib/newfifo/fifo_2clock.v
+++ b/usrp2/fifo/fifo_2clock.v
diff --git a/usrp2/control_lib/newfifo/fifo_2clock_cascade.v b/usrp2/fifo/fifo_2clock_cascade.v
index 5ce726977..5ce726977 100644
--- a/usrp2/control_lib/newfifo/fifo_2clock_cascade.v
+++ b/usrp2/fifo/fifo_2clock_cascade.v
diff --git a/usrp2/control_lib/newfifo/fifo_cascade.v b/usrp2/fifo/fifo_cascade.v
index fdd8449bc..fdd8449bc 100644
--- a/usrp2/control_lib/newfifo/fifo_cascade.v
+++ b/usrp2/fifo/fifo_cascade.v
diff --git a/usrp2/control_lib/newfifo/fifo_long.v b/usrp2/fifo/fifo_long.v
index 0426779f6..0426779f6 100644
--- a/usrp2/control_lib/newfifo/fifo_long.v
+++ b/usrp2/fifo/fifo_long.v
diff --git a/usrp2/control_lib/newfifo/fifo_new_tb.vcd b/usrp2/fifo/fifo_new_tb.vcd
index 796889e7d..796889e7d 100644
--- a/usrp2/control_lib/newfifo/fifo_new_tb.vcd
+++ b/usrp2/fifo/fifo_new_tb.vcd
diff --git a/usrp2/control_lib/newfifo/fifo_short.v b/usrp2/fifo/fifo_short.v
index 53a7603c7..53a7603c7 100644
--- a/usrp2/control_lib/newfifo/fifo_short.v
+++ b/usrp2/fifo/fifo_short.v
diff --git a/usrp2/control_lib/newfifo/fifo_spec.txt b/usrp2/fifo/fifo_spec.txt
index 133b9fa8e..133b9fa8e 100644
--- a/usrp2/control_lib/newfifo/fifo_spec.txt
+++ b/usrp2/fifo/fifo_spec.txt
diff --git a/usrp2/control_lib/newfifo/fifo_tb.v b/usrp2/fifo/fifo_tb.v
index f561df7fa..f561df7fa 100644
--- a/usrp2/control_lib/newfifo/fifo_tb.v
+++ b/usrp2/fifo/fifo_tb.v
diff --git a/usrp2/control_lib/newfifo/ll8_shortfifo.v b/usrp2/fifo/ll8_shortfifo.v
index 39ada9a4f..39ada9a4f 100644
--- a/usrp2/control_lib/newfifo/ll8_shortfifo.v
+++ b/usrp2/fifo/ll8_shortfifo.v
diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v
index af3b91afb..af3b91afb 100644
--- a/usrp2/control_lib/newfifo/ll8_to_fifo19.v
+++ b/usrp2/fifo/ll8_to_fifo19.v
diff --git a/usrp2/control_lib/newfifo/ll8_to_fifo36.v b/usrp2/fifo/ll8_to_fifo36.v
index 108daa903..108daa903 100644
--- a/usrp2/control_lib/newfifo/ll8_to_fifo36.v
+++ b/usrp2/fifo/ll8_to_fifo36.v
diff --git a/usrp2/gpmc/Makefile.srcs b/usrp2/gpmc/Makefile.srcs
new file mode 100644
index 000000000..bff6ae3e0
--- /dev/null
+++ b/usrp2/gpmc/Makefile.srcs
@@ -0,0 +1,20 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# SERDES Sources
+##################################################
+GPMC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpmc/, \
+dbsm.v \
+edge_sync.v \
+fifo_to_gpmc_async.v \
+fifo_to_gpmc_sync.v \
+fifo_watcher.v \
+gpmc_async.v \
+gpmc_sync.v \
+gpmc_to_fifo_async.v \
+gpmc_to_fifo_sync.v \
+gpmc_wb.v \
+ram_to_fifo.v \
+))
diff --git a/usrp2/opencores/Makefile.srcs b/usrp2/opencores/Makefile.srcs
new file mode 100644
index 000000000..1ccecf337
--- /dev/null
+++ b/usrp2/opencores/Makefile.srcs
@@ -0,0 +1,27 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Open Cores Sources
+##################################################
+OPENCORES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../opencores/, \
+8b10b/decode_8b10b.v \
+8b10b/encode_8b10b.v \
+aemb/rtl/verilog/aeMB_bpcu.v \
+aemb/rtl/verilog/aeMB_core_BE.v \
+aemb/rtl/verilog/aeMB_ctrl.v \
+aemb/rtl/verilog/aeMB_edk32.v \
+aemb/rtl/verilog/aeMB_ibuf.v \
+aemb/rtl/verilog/aeMB_regf.v \
+aemb/rtl/verilog/aeMB_xecu.v \
+i2c/rtl/verilog/i2c_master_bit_ctrl.v \
+i2c/rtl/verilog/i2c_master_byte_ctrl.v \
+i2c/rtl/verilog/i2c_master_defines.v \
+i2c/rtl/verilog/i2c_master_top.v \
+i2c/rtl/verilog/timescale.v \
+spi/rtl/verilog/spi_clgen.v \
+spi/rtl/verilog/spi_defines.v \
+spi/rtl/verilog/spi_shift.v \
+spi/rtl/verilog/spi_top16.v \
+))
diff --git a/usrp2/sdr_lib/Makefile.srcs b/usrp2/sdr_lib/Makefile.srcs
new file mode 100644
index 000000000..90eede20f
--- /dev/null
+++ b/usrp2/sdr_lib/Makefile.srcs
@@ -0,0 +1,37 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# FIFO Sources
+##################################################
+SDR_LIB_SRCS = $(abspath $(addprefix $(BASE_DIR)/../sdr_lib/, \
+acc.v \
+add2.v \
+add2_and_round.v \
+add2_and_round_reg.v \
+add2_reg.v \
+cic_dec_shifter.v \
+cic_decim.v \
+cic_int_shifter.v \
+cic_interp.v \
+cic_strober.v \
+clip.v \
+clip_reg.v \
+cordic.v \
+cordic_z24.v \
+cordic_stage.v \
+dsp_core_rx.v \
+dsp_core_rx_old.v \
+dsp_core_tx.v \
+hb_dec.v \
+hb_interp.v \
+round.v \
+round_reg.v \
+rx_control.v \
+rx_dcoffset.v \
+sign_extend.v \
+small_hb_dec.v \
+small_hb_int.v \
+tx_control.v \
+))
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v
index aba18fccb..1e689fc7f 100644
--- a/usrp2/sdr_lib/dsp_core_rx.v
+++ b/usrp2/sdr_lib/dsp_core_rx.v
@@ -1,6 +1,6 @@
 
-`define DSP_CORE_RX_BASE 160
 module dsp_core_rx
+  #(parameter BASE = 160)
   (input clk, input rst,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
 
@@ -37,33 +37,33 @@ module dsp_core_rx
    wire [31:4] 	UNUSED_2;
    wire [31:2] 	UNUSED_3;
    
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+   setting_reg #(.my_addr(BASE+0)) sr_0
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(phase_inc),.changed());
    
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+   setting_reg #(.my_addr(BASE+1)) sr_1
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({scale_i,scale_q}),.changed());
    
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+   setting_reg #(.my_addr(BASE+2)) sr_2
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed());
 
-   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_in(adc_a),.adc_out(adc_a_ofs));
    
-   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+   rx_dcoffset #(.WIDTH(14),.ADDR(BASE+4)) rx_dcoffset_b
      (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_in(adc_b),.adc_out(adc_b_ofs));
 
    wire [3:0]  muxctrl;
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+   setting_reg #(.my_addr(BASE+5)) sr_8
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({UNUSED_2,muxctrl}),.changed());
 
    wire [1:0] gpio_ena;
-   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+   setting_reg #(.my_addr(BASE+6)) sr_9
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
 
diff --git a/usrp2/sdr_lib/dsp_core_rx_old.v b/usrp2/sdr_lib/dsp_core_rx_old.v
new file mode 100644
index 000000000..ba301e91b
--- /dev/null
+++ b/usrp2/sdr_lib/dsp_core_rx_old.v
@@ -0,0 +1,183 @@
+
+`define DSP_CORE_RX_BASE 160
+module dsp_core_rx_old
+  (input clk, input rst,
+   input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+   input [13:0] adc_a, input adc_ovf_a,
+   input [13:0] adc_b, input adc_ovf_b,
+   
+   input [15:0] io_rx,
+
+   output [31:0] sample,
+   input run,
+   output strobe,
+   output [31:0] debug
+   );
+
+   wire [15:0] scale_i, scale_q;
+   wire [13:0] adc_a_ofs, adc_b_ofs;
+   reg [13:0] adc_i, adc_q;
+   wire [31:0] phase_inc;
+   reg [31:0]  phase;
+
+   wire [35:0] prod_i, prod_q;
+   wire [23:0] i_cordic, q_cordic;
+   wire [23:0] i_cic, q_cic;
+   wire [17:0] i_cic_scaled, q_cic_scaled;
+   wire [17:0] i_hb1, q_hb1;
+   wire [17:0] i_hb2, q_hb2;
+   wire [15:0] i_out, q_out;
+
+   wire        strobe_cic, strobe_hb1, strobe_hb2;
+   wire        enable_hb1, enable_hb2;
+   wire [7:0]  cic_decim_rate;
+
+   wire [31:10] UNUSED_1;
+   wire [31:4] 	UNUSED_2;
+   wire [31:2] 	UNUSED_3;
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+0)) sr_0
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(phase_inc),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+1)) sr_1
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({scale_i,scale_q}),.changed());
+   
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed());
+
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+6)) rx_dcoffset_a
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_a),.adc_out(adc_a_ofs));
+   
+   rx_dcoffset #(.WIDTH(14),.ADDR(`DSP_CORE_RX_BASE+7)) rx_dcoffset_b
+     (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+      .adc_in(adc_b),.adc_out(adc_b_ofs));
+
+   wire [3:0]  muxctrl;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+8)) sr_8
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({UNUSED_2,muxctrl}),.changed());
+
+   wire [1:0] gpio_ena;
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+9)) sr_9
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({UNUSED_3,gpio_ena}),.changed());
+
+   // The TVRX connects to what is called adc_b, thus A and B are
+   // swapped throughout the design.
+   //
+   // In the interest of expediency and keeping the s/w sane, we just remap them here.
+   // The I & Q fields are mapped the same:
+   // 0 -> "the real A" (as determined by the TVRX)
+   // 1 -> "the real B"
+   // 2 -> const zero
+   
+   always @(posedge clk)
+     case(muxctrl[1:0])		// The I mapping
+       0: adc_i <= adc_b_ofs;	// "the real A"
+       1: adc_i <= adc_a_ofs;
+       2: adc_i <= 0;
+       default: adc_i <= 0;
+     endcase // case(muxctrl[1:0])
+          
+   always @(posedge clk)
+     case(muxctrl[3:2])		// The Q mapping
+       0: adc_q <= adc_b_ofs;	// "the real A"
+       1: adc_q <= adc_a_ofs;
+       2: adc_q <= 0;
+       default: adc_q <= 0;
+     endcase // case(muxctrl[3:2])
+       
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(~run)
+       phase <= 0;
+     else
+       phase <= phase + phase_inc;
+
+   MULT18X18S mult_i
+     (.P(prod_i),    // 36-bit multiplier output
+      .A({{4{adc_i[13]}},adc_i} ),    // 18-bit multiplier input
+      .B({{2{scale_i[15]}},scale_i}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      );
+
+   MULT18X18S mult_q
+     (.P(prod_q),    // 36-bit multiplier output
+      .A({{4{adc_q[13]}},adc_q} ),    // 18-bit multiplier input
+      .B({{2{scale_q[15]}},scale_q}),    // 18-bit multiplier input
+      .C(clk),    // Clock input
+      .CE(1),  // Clock enable input
+      .R(rst)     // Synchronous reset input
+      ); 
+
+   
+   cordic_z24 #(.bitwidth(24))
+     cordic(.clock(clk), .reset(rst), .enable(run),
+	    .xi(prod_i[23:0]),. yi(prod_q[23:0]), .zi(phase[31:8]),
+	    .xo(i_cordic),.yo(q_cordic),.zo() );
+
+   cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate),
+			   .strobe_fast(1),.strobe_slow(strobe_cic) );
+
+   cic_decim #(.bw(24))
+     decim_i (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(i_cordic),.signal_out(i_cic));
+   
+   cic_decim #(.bw(24))
+     decim_q (.clock(clk),.reset(rst),.enable(run),
+	      .rate(cic_decim_rate),.strobe_in(1'b1),.strobe_out(strobe_cic),
+	      .signal_in(q_cordic),.signal_out(q_cic));
+
+   round_reg #(.bits_in(24),.bits_out(18)) round_icic (.clk(clk),.in(i_cic),.out(i_cic_scaled));
+   round_reg #(.bits_in(24),.bits_out(18)) round_qcic (.clk(clk),.in(q_cic),.out(q_cic_scaled));
+   reg 	       strobe_cic_d1;
+   always @(posedge clk) strobe_cic_d1 <= strobe_cic;
+   
+   small_hb_dec #(.WIDTH(18)) small_hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+      .stb_in(strobe_cic_d1),.data_in(i_cic_scaled),.stb_out(strobe_hb1),.data_out(i_hb1));
+   
+   small_hb_dec #(.WIDTH(18)) small_hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb1),.run(run),
+      .stb_in(strobe_cic_d1),.data_in(q_cic_scaled),.stb_out(),.data_out(q_hb1));
+
+   wire [8:0]  cpi_hb = enable_hb1 ? {cic_decim_rate,1'b0} : {1'b0,cic_decim_rate};
+   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_i
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(i_hb1),.stb_out(strobe_hb2),.data_out(i_hb2));
+
+   hb_dec #(.IWIDTH(18), .OWIDTH(18), .CWIDTH(18), .ACCWIDTH(24)) hb_q
+     (.clk(clk),.rst(rst),.bypass(~enable_hb2),.run(run),.cpi(cpi_hb),
+      .stb_in(strobe_hb1),.data_in(q_hb1),.stb_out(),.data_out(q_hb2));
+
+   round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out));
+   round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out));
+
+   // Streaming GPIO
+   //
+   // io_rx[15] => I channel LSB if gpio_ena[0] high
+   // io_rx[14] => Q channel LSB if gpio_ena[1] high
+
+   reg [31:0] sample_reg;
+   always @(posedge clk)
+     begin
+	sample_reg[31:17] <= i_out[15:1];
+	sample_reg[15:1]  <= q_out[15:1];
+	sample_reg[16]    <= gpio_ena[0] ? io_rx[15] : i_out[0]; 
+	sample_reg[0]     <= gpio_ena[1] ? io_rx[14] : q_out[0];
+     end
+   
+   assign      sample = sample_reg;
+   assign      strobe = strobe_hb2;
+   assign      debug = {enable_hb1, enable_hb2, run, strobe, strobe_cic, strobe_cic_d1, strobe_hb1, strobe_hb2};
+   
+endmodule // dsp_core_rx
diff --git a/usrp2/serdes/Makefile.srcs b/usrp2/serdes/Makefile.srcs
new file mode 100644
index 000000000..bade46ad1
--- /dev/null
+++ b/usrp2/serdes/Makefile.srcs
@@ -0,0 +1,14 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# SERDES Sources
+##################################################
+SERDES_SRCS = $(abspath $(addprefix $(BASE_DIR)/../serdes/, \
+serdes.v \
+serdes_fc_rx.v \
+serdes_fc_tx.v \
+serdes_rx.v \
+serdes_tx.v \
+))
diff --git a/usrp2/simple_gemac/Makefile.srcs b/usrp2/simple_gemac/Makefile.srcs
new file mode 100644
index 000000000..6480cd5a4
--- /dev/null
+++ b/usrp2/simple_gemac/Makefile.srcs
@@ -0,0 +1,26 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Simple GEMAC Sources
+##################################################
+SIMPLE_GEMAC_SRCS = $(abspath $(addprefix $(BASE_DIR)/../simple_gemac/, \
+simple_gemac_wrapper.v \
+simple_gemac_wrapper19.v \
+simple_gemac.v \
+simple_gemac_wb.v \
+simple_gemac_tx.v \
+simple_gemac_rx.v \
+crc.v \
+delay_line.v \
+flow_ctrl_tx.v \
+flow_ctrl_rx.v \
+address_filter.v \
+ll8_to_txmac.v \
+rxmac_to_ll8.v \
+miim/eth_miim.v \
+miim/eth_clockgen.v \
+miim/eth_outputcontrol.v \
+miim/eth_shiftreg.v \
+))
diff --git a/usrp2/timing/Makefile.srcs b/usrp2/timing/Makefile.srcs
new file mode 100644
index 000000000..0cf9372d3
--- /dev/null
+++ b/usrp2/timing/Makefile.srcs
@@ -0,0 +1,16 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# Timing Sources
+##################################################
+TIMING_SRCS = $(abspath $(addprefix $(BASE_DIR)/../timing/, \
+time_64bit.v \
+time_compare.v \
+time_receiver.v \
+time_sender.v \
+time_sync.v \
+timer.v \
+simple_timer.v \
+))
diff --git a/usrp2/top/Makefile.common b/usrp2/top/Makefile.common
new file mode 100644
index 000000000..d1c89fdfb
--- /dev/null
+++ b/usrp2/top/Makefile.common
@@ -0,0 +1,57 @@
+#
+# Copyright 2008, 2009, 2010 Ettus Research LLC
+#
+
+##################################################
+# Constants
+##################################################
+ISE_VER = $(shell xtclsh -h | head -n1 | cut -f2 -d" " | cut -f1 -d.)
+ifeq ($(ISE_VER),10)
+	ISE_EXT = ise
+else
+	ISE_EXT = xise
+endif
+BASE_DIR = $(abspath ..)
+ISE_HELPER = xtclsh $(BASE_DIR)/tcl/ise_helper.tcl
+ISE_FILE = $(BUILD_DIR)/$(TOP_MODULE).$(ISE_EXT)
+BIN_FILE = $(BUILD_DIR)/$(TOP_MODULE).bin
+MCS_FILE = $(BUILD_DIR)/$(TOP_MODULE).mcs
+
+##################################################
+# Global Targets
+##################################################
+all: bin
+
+proj: $(ISE_FILE)
+
+check: $(ISE_FILE)
+	$(ISE_HELPER) "Check Syntax"
+
+synth: $(ISE_FILE)
+	$(ISE_HELPER) "Synthesize - XST"
+
+bin: $(BIN_FILE)
+
+mcs: $(MCS_FILE)
+
+clean:
+	$(RM) -r $(BUILD_DIR)
+
+.PHONY: all proj check synth bin mcs clean
+
+##################################################
+# Dependency Targets
+##################################################
+$(ISE_FILE): $(SOURCES)
+	@echo $@
+	$(ISE_HELPER) ""
+
+$(BIN_FILE): $(ISE_FILE)
+	@echo $@
+	$(ISE_HELPER) "Generate Programming File"
+	touch $@
+
+$(MCS_FILE): $(BIN_FILE)
+	promgen -w -spi -p mcs -o $(MCS_FILE) -s 4096 -u 0 $(BIN_FILE)
+
+.EXPORT_ALL_VARIABLES:
diff --git a/usrp2/top/tcl/ise_helper.tcl b/usrp2/top/tcl/ise_helper.tcl
index fe9db87af..a4bee76b8 100644
--- a/usrp2/top/tcl/ise_helper.tcl
+++ b/usrp2/top/tcl/ise_helper.tcl
@@ -40,12 +40,12 @@ proc set_props {process options} {
 	}
 }
 
-if [file isfile $env(PROJ_FILE)] {
-	puts ">>> Opening project: $env(PROJ_FILE)"
-	project open $env(PROJ_FILE)
+if [file isfile $env(ISE_FILE)] {
+	puts ">>> Opening project: $env(ISE_FILE)"
+	project open $env(ISE_FILE)
 } else {	
-	puts ">>> Creating project: $env(PROJ_FILE)"
-	project new $env(PROJ_FILE)
+	puts ">>> Creating project: $env(ISE_FILE)"
+	project new $env(ISE_FILE)
 	
 	##################################################
 	# Set the project properties
@@ -56,7 +56,6 @@ if [file isfile $env(PROJ_FILE)] {
 	# Add the sources
 	##################################################
 	foreach source $env(SOURCES) {
-		set source $env(SOURCE_ROOT)$source
 		puts ">>> Adding source to project: $source"
 		xfile add $source
 	}
@@ -78,9 +77,9 @@ if [file isfile $env(PROJ_FILE)] {
 	set_props "Generate Post-Place & Route Simulation Model" $env(SIM_MODEL_PROPERTIES)
 }
 
-if [string compare $env(PROCESS_RUN) ""] {
-	puts ">>> Running Process: $env(PROCESS_RUN)"
-	process run $env(PROCESS_RUN)
+if [string compare [lindex $argv 0] ""] {
+	puts ">>> Running Process: [lindex $argv 0]"
+	process run [lindex $argv 0]
 }
 
 project close
diff --git a/usrp2/top/u1e/Makefile b/usrp2/top/u1e/Makefile
index cfef1378f..f4a643176 100644
--- a/usrp2/top/u1e/Makefile
+++ b/usrp2/top/u1e/Makefile
@@ -1,37 +1,30 @@
 #
 # Copyright 2008 Ettus Research LLC
-# 
-# This file is part of GNU Radio
-# 
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-# 
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-# 
+#
 
 ##################################################
-# xtclsh Shell and tcl Script Path
+# Project Setup
 ##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+TOP_MODULE = u1e
+BUILD_DIR = $(abspath build$(ISE))
 
 ##################################################
-# Project Setup
+# Include other makefiles
 ##################################################
-BUILD_DIR := build/
-export TOP_MODULE := u1e
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
+include ../../gpmc/Makefile.srcs
 
 ##################################################
 # Project Properties
@@ -51,159 +44,23 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 # Sources
 ##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller16.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio16LE.v \
-control_lib/ram_2port.v \
-control_lib/ram_2port_mixed_width.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus_16LE.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/newfifo/packet_generator.v \
-control_lib/newfifo/packet_verifier.v \
-control_lib/newfifo/packet_generator32.v \
-control_lib/newfifo/packet_verifier32.v \
-control_lib/newfifo/fifo_pacer.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/simple_pic/rtl/simple_pic.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top16.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx_udp.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/time_64bit.v \
-gpmc/gpmc_async.v \
-gpmc/edge_sync.v \
-gpmc/dbsm.v \
-gpmc/gpmc_to_fifo_async.v \
-gpmc/fifo_to_gpmc_async.v \
-gpmc/fifo_watcher.v \
-gpmc/gpmc_wb.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-timing/time_compare.v \
-top/u1e/u1e_core.v \
-top/u1e/u1e.ucf \
-top/u1e/timing.ucf \
-top/u1e/u1e.v 
+TOP_SRCS = \
+u1e_core.v \
+u1e.v \
+u1e.ucf \
+timing.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS) \
+$(GPMC_SRCS)
 
 ##################################################
 # Process Properties
 ##################################################
-export SYNTHESIZE_PROPERTIES := \
-"Number of Clock Buffers" 6 \
+SYNTHESIZE_PROPERTIES = \
+"Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
 "Optimize Instantiated Primitives" TRUE \
@@ -212,10 +69,10 @@ export SYNTHESIZE_PROPERTIES := \
 "Use Synchronous Reset" Auto \
 "Use Synchronous Set" Auto
 
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
 
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
 "Allow Logic Optimization Across Hierarchy" TRUE \
 "Map to Input Functions" 4 \
 "Optimization Strategy (Cover Mode)" Speed \
@@ -226,42 +83,18 @@ export MAP_PROPERTIES := \
 "Combinatorial Logic Optimization" TRUE \
 "Register Duplication" TRUE
 
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
 "Place & Route Effort Level (Overall)" High 
 
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
 "Number of Paths in Error/Verbose Report" 10 \
 "Report Type" "Error Report"
 
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
 "Configuration Rate" 6 \
 "Create Binary Configuration File" TRUE \
 "Done (Output Events)" 5 \
 "Enable Bitstream Compression" TRUE \
-"Enable Outputs (Output Events)" 6 \
-"Unused IOB Pins" "Pull Up"
-
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
-	@echo make proj, check, synth, bin, or clean
-
-proj:
-	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
-
-check:
-	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
-
-synth:
-	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
-
-bin:
-	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
-
-clean:
-	rm -rf $(BUILD_DIR)
-
+"Enable Outputs (Output Events)" 6 
 
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2_core/.gitignore b/usrp2/top/u2_core/.gitignore
deleted file mode 100644
index 9728395c1..000000000
--- a/usrp2/top/u2_core/.gitignore
+++ /dev/null
@@ -1,44 +0,0 @@
-*~
-/xst
-/_ngo
-/_xmsgs
-/*.stx
-/*.tspec
-/*.xml
-/*.gyd
-/*.ngr
-/*.tim
-/*.err
-/*.lso
-/*.bld
-/*.cmd_log
-/*.ise_ISE_Backup
-/*.mfd
-/*.vm6
-/*.syr
-/*.xst
-/*.csv
-/*.html
-/*.jed
-/*.pad
-/*.ng*
-/*.pnx
-/*.rpt
-/*.prj
-/*_html
-/*_log
-/*.lfp
-/*.bit
-/*.bin
-/*.vcd
-/*.unroutes
-/*.drc
-/*_map.*
-/*_guide.*
-/*.twr
-/*.twx
-/a.out
-/*.xpi
-/*_pad.txt
-/*.bgn
-/*.par
diff --git a/usrp2/top/u2_rev3/Makefile b/usrp2/top/u2_rev3/Makefile
index f5cac7ad2..68c296b9b 100644
--- a/usrp2/top/u2_rev3/Makefile
+++ b/usrp2/top/u2_rev3/Makefile
@@ -1,42 +1,34 @@
 #
 # Copyright 2008 Ettus Research LLC
-# 
-# This file is part of GNU Radio
-# 
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-# 
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-# 
+#
 
 ##################################################
-# xtclsh Shell and tcl Script Path
+# Project Setup
 ##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build$(ISE))
 
 ##################################################
-# Project Setup
+# Include other makefiles
 ##################################################
-BUILD_DIR := build$(ISE)/
-export TOP_MODULE := u2_rev3
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
 
 ##################################################
 # Project Properties
 ##################################################
-export PROJECT_PROPERTIES := \
+PROJECT_PROPERTIES = \
 family Spartan3 \
 device xc3s2000 \
 package fg456 \
@@ -51,160 +43,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 # Sources
 ##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio.v \
-control_lib/ram_2port.v \
-control_lib/ram_harvard.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus.v \
-control_lib/settings_bus_crossclock.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-control_lib/priority_enc.v \
-control_lib/pic.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-udp/udp_wrapper.v \
-udp/fifo19_rxrealign.v \
-udp/prot_eng_tx.v \
-udp/add_onescomp.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac_wrapper19.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo19_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo19.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-coregen/fifo_xlnx_16x19_2clk.v \
-coregen/fifo_xlnx_16x19_2clk.xco \
-coregen/fifo_xlnx_16x40_2clk.v \
-coregen/fifo_xlnx_16x40_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top.v \
-opencores/spi/rtl/verilog/timescale.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_64bit.v \
-timing/time_compare.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/simple_timer.v \
-top/u2_core/u2_core.v \
-top/u2_rev3/u2_rev3.ucf \
-top/u2_rev3/u2_rev3.v 
+TOP_SRCS = \
+u2_core.v \
+u2_rev3.v \
+u2_rev3.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
 
 ##################################################
 # Process Properties
 ##################################################
-export SYNTHESIZE_PROPERTIES := \
+SYNTHESIZE_PROPERTIES = \
 "Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
@@ -214,10 +66,10 @@ export SYNTHESIZE_PROPERTIES := \
 "Use Synchronous Reset" Auto \
 "Use Synchronous Set" Auto
 
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
 
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
 "Allow Logic Optimization Across Hierarchy" TRUE \
 "Map to Input Functions" 4 \
 "Optimization Strategy (Cover Mode)" Speed \
@@ -228,41 +80,18 @@ export MAP_PROPERTIES := \
 "Combinatorial Logic Optimization" TRUE \
 "Register Duplication" TRUE
 
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
 "Place & Route Effort Level (Overall)" High 
 
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
 "Number of Paths in Error/Verbose Report" 10 \
 "Report Type" "Error Report"
 
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
 "Configuration Rate" 6 \
 "Create Binary Configuration File" TRUE \
 "Done (Output Events)" 5 \
 "Enable Bitstream Compression" TRUE \
 "Enable Outputs (Output Events)" 6 
 
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
-	@echo make proj, check, synth, bin, or clean
-
-proj:
-	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
-
-check:
-	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
-
-synth:
-	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
-
-bin:
-	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
-
-clean:
-	rm -rf $(BUILD_DIR)
-
-
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2_rev3/Makefile.udp b/usrp2/top/u2_rev3/Makefile.udp
index 217871dbb..9962887d4 100644
--- a/usrp2/top/u2_rev3/Makefile.udp
+++ b/usrp2/top/u2_rev3/Makefile.udp
@@ -1,42 +1,34 @@
 #
 # Copyright 2008 Ettus Research LLC
-# 
-# This file is part of GNU Radio
-# 
-# GNU Radio is free software; you can redistribute it and/or modify
-# it under the terms of the GNU General Public License as published by
-# the Free Software Foundation; either version 3, or (at your option)
-# any later version.
-# 
-# GNU Radio is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-# 
-# You should have received a copy of the GNU General Public License
-# along with GNU Radio; see the file COPYING.  If not, write to
-# the Free Software Foundation, Inc., 51 Franklin Street,
-# Boston, MA 02110-1301, USA.
-# 
+#
 
 ##################################################
-# xtclsh Shell and tcl Script Path
+# Project Setup
 ##################################################
-#XTCLSH := /opt/Xilinx/10.1/ISE/bin/lin/xtclsh
-XTCLSH := xtclsh
-ISE_HELPER := ../tcl/ise_helper.tcl
+TOP_MODULE = u2_rev3
+BUILD_DIR = $(abspath build-udp$(ISE))
 
 ##################################################
-# Project Setup
+# Include other makefiles
 ##################################################
-BUILD_DIR := build-udp$(ISE)/
-export TOP_MODULE := u2_rev3
-export PROJ_FILE := $(BUILD_DIR)$(TOP_MODULE).ise
+
+include ../Makefile.common
+include ../../fifo/Makefile.srcs
+include ../../control_lib/Makefile.srcs
+include ../../sdr_lib/Makefile.srcs
+include ../../serdes/Makefile.srcs
+include ../../simple_gemac/Makefile.srcs
+include ../../timing/Makefile.srcs
+include ../../opencores/Makefile.srcs
+include ../../vrt/Makefile.srcs
+include ../../udp/Makefile.srcs
+include ../../coregen/Makefile.srcs
+include ../../extram/Makefile.srcs
 
 ##################################################
 # Project Properties
 ##################################################
-export PROJECT_PROPERTIES := \
+PROJECT_PROPERTIES = \
 family Spartan3 \
 device xc3s2000 \
 package fg456 \
@@ -51,160 +43,20 @@ simulator "ISE Simulator (VHDL/Verilog)" \
 ##################################################
 # Sources
 ##################################################
-export SOURCE_ROOT := ../../../
-export SOURCES := \
-control_lib/CRC16_D16.v \
-control_lib/atr_controller.v \
-control_lib/bin2gray.v \
-control_lib/dcache.v \
-control_lib/decoder_3_8.v \
-control_lib/dpram32.v \
-control_lib/gray2bin.v \
-control_lib/gray_send.v \
-control_lib/icache.v \
-control_lib/mux4.v \
-control_lib/mux8.v \
-control_lib/nsgpio.v \
-control_lib/ram_2port.v \
-control_lib/ram_harvard.v \
-control_lib/ram_harv_cache.v \
-control_lib/ram_loader.v \
-control_lib/setting_reg.v \
-control_lib/settings_bus.v \
-control_lib/settings_bus_crossclock.v \
-control_lib/srl.v \
-control_lib/system_control.v \
-control_lib/wb_1master.v \
-control_lib/wb_readback_mux.v \
-control_lib/simple_uart.v \
-control_lib/simple_uart_tx.v \
-control_lib/simple_uart_rx.v \
-control_lib/oneshot_2clk.v \
-control_lib/sd_spi.v \
-control_lib/sd_spi_wb.v \
-control_lib/wb_bridge_16_32.v \
-control_lib/reset_sync.v \
-control_lib/priority_enc.v \
-control_lib/pic.v \
-vrt/vita_rx_control.v \
-vrt/vita_rx_framer.v \
-vrt/vita_tx_control.v \
-vrt/vita_tx_deframer.v \
-udp/udp_wrapper.v \
-udp/fifo19_rxrealign.v \
-udp/prot_eng_tx.v \
-udp/add_onescomp.v \
-simple_gemac/simple_gemac_wrapper.v \
-simple_gemac/simple_gemac_wrapper19.v \
-simple_gemac/simple_gemac.v \
-simple_gemac/simple_gemac_wb.v \
-simple_gemac/simple_gemac_tx.v \
-simple_gemac/simple_gemac_rx.v \
-simple_gemac/crc.v \
-simple_gemac/delay_line.v \
-simple_gemac/flow_ctrl_tx.v \
-simple_gemac/flow_ctrl_rx.v \
-simple_gemac/address_filter.v \
-simple_gemac/ll8_to_txmac.v \
-simple_gemac/rxmac_to_ll8.v \
-simple_gemac/miim/eth_miim.v \
-simple_gemac/miim/eth_clockgen.v \
-simple_gemac/miim/eth_outputcontrol.v \
-simple_gemac/miim/eth_shiftreg.v \
-control_lib/newfifo/buffer_int.v \
-control_lib/newfifo/buffer_pool.v \
-control_lib/newfifo/fifo_2clock.v \
-control_lib/newfifo/fifo_2clock_cascade.v \
-control_lib/newfifo/ll8_shortfifo.v \
-control_lib/newfifo/fifo_short.v \
-control_lib/newfifo/fifo_long.v \
-control_lib/newfifo/fifo_cascade.v \
-control_lib/newfifo/fifo36_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo36.v \
-control_lib/newfifo/fifo19_to_ll8.v \
-control_lib/newfifo/ll8_to_fifo19.v \
-control_lib/newfifo/fifo36_to_fifo19.v \
-control_lib/newfifo/fifo19_to_fifo36.v \
-control_lib/longfifo.v \
-control_lib/shortfifo.v \
-control_lib/medfifo.v \
-coregen/fifo_xlnx_2Kx36_2clk.v \
-coregen/fifo_xlnx_2Kx36_2clk.xco \
-coregen/fifo_xlnx_512x36_2clk.v \
-coregen/fifo_xlnx_512x36_2clk.xco \
-coregen/fifo_xlnx_64x36_2clk.v \
-coregen/fifo_xlnx_64x36_2clk.xco \
-coregen/fifo_xlnx_16x19_2clk.v \
-coregen/fifo_xlnx_16x19_2clk.xco \
-coregen/fifo_xlnx_16x40_2clk.v \
-coregen/fifo_xlnx_16x40_2clk.xco \
-extram/wb_zbt16_b.v \
-opencores/8b10b/decode_8b10b.v \
-opencores/8b10b/encode_8b10b.v \
-opencores/aemb/rtl/verilog/aeMB_bpcu.v \
-opencores/aemb/rtl/verilog/aeMB_core_BE.v \
-opencores/aemb/rtl/verilog/aeMB_ctrl.v \
-opencores/aemb/rtl/verilog/aeMB_edk32.v \
-opencores/aemb/rtl/verilog/aeMB_ibuf.v \
-opencores/aemb/rtl/verilog/aeMB_regf.v \
-opencores/aemb/rtl/verilog/aeMB_xecu.v \
-opencores/i2c/rtl/verilog/i2c_master_bit_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v \
-opencores/i2c/rtl/verilog/i2c_master_defines.v \
-opencores/i2c/rtl/verilog/i2c_master_top.v \
-opencores/i2c/rtl/verilog/timescale.v \
-opencores/spi/rtl/verilog/spi_clgen.v \
-opencores/spi/rtl/verilog/spi_defines.v \
-opencores/spi/rtl/verilog/spi_shift.v \
-opencores/spi/rtl/verilog/spi_top.v \
-opencores/spi/rtl/verilog/timescale.v \
-sdr_lib/acc.v \
-sdr_lib/add2.v \
-sdr_lib/add2_and_round.v \
-sdr_lib/add2_and_round_reg.v \
-sdr_lib/add2_reg.v \
-sdr_lib/cic_dec_shifter.v \
-sdr_lib/cic_decim.v \
-sdr_lib/cic_int_shifter.v \
-sdr_lib/cic_interp.v \
-sdr_lib/cic_strober.v \
-sdr_lib/clip.v \
-sdr_lib/clip_reg.v \
-sdr_lib/cordic.v \
-sdr_lib/cordic_z24.v \
-sdr_lib/cordic_stage.v \
-sdr_lib/dsp_core_rx_udp.v \
-sdr_lib/dsp_core_tx.v \
-sdr_lib/hb_dec.v \
-sdr_lib/hb_interp.v \
-sdr_lib/round.v \
-sdr_lib/round_reg.v \
-sdr_lib/rx_control.v \
-sdr_lib/rx_dcoffset.v \
-sdr_lib/sign_extend.v \
-sdr_lib/small_hb_dec.v \
-sdr_lib/small_hb_int.v \
-sdr_lib/tx_control.v \
-serdes/serdes.v \
-serdes/serdes_fc_rx.v \
-serdes/serdes_fc_tx.v \
-serdes/serdes_rx.v \
-serdes/serdes_tx.v \
-timing/time_64bit.v \
-timing/time_compare.v \
-timing/time_receiver.v \
-timing/time_sender.v \
-timing/time_sync.v \
-timing/timer.v \
-timing/simple_timer.v \
-top/u2_core/u2_core_udp.v \
-top/u2_rev3/u2_rev3.ucf \
-top/u2_rev3/u2_rev3.v 
+TOP_SRCS = \
+u2_core_udp.v \
+u2_rev3.v \
+u2_rev3.ucf
+
+SOURCES = $(abspath $(TOP_SRCS)) $(FIFO_SRCS) \
+$(CONTROL_LIB_SRCS) $(SDR_LIB_SRCS) $(SERDES_SRCS) \
+$(SIMPLE_GEMAC_SRCS) $(TIMING_SRCS) $(OPENCORES_SRCS) \
+$(VRT_SRCS) $(UDP_SRCS) $(COREGEN_SRCS) $(EXTRAM_SRCS)
 
 ##################################################
 # Process Properties
 ##################################################
-export SYNTHESIZE_PROPERTIES := \
+SYNTHESIZE_PROPERTIES = \
 "Number of Clock Buffers" 8 \
 "Pack I/O Registers into IOBs" Yes \
 "Optimization Effort" High \
@@ -214,10 +66,10 @@ export SYNTHESIZE_PROPERTIES := \
 "Use Synchronous Reset" Auto \
 "Use Synchronous Set" Auto
 
-export TRANSLATE_PROPERTIES := \
+TRANSLATE_PROPERTIES = \
 "Macro Search Path" "$(shell pwd)/../../coregen/"
 
-export MAP_PROPERTIES := \
+MAP_PROPERTIES = \
 "Allow Logic Optimization Across Hierarchy" TRUE \
 "Map to Input Functions" 4 \
 "Optimization Strategy (Cover Mode)" Speed \
@@ -228,41 +80,18 @@ export MAP_PROPERTIES := \
 "Combinatorial Logic Optimization" TRUE \
 "Register Duplication" TRUE
 
-export PLACE_ROUTE_PROPERTIES := \
+PLACE_ROUTE_PROPERTIES = \
 "Place & Route Effort Level (Overall)" High 
 
-export STATIC_TIMING_PROPERTIES := \
+STATIC_TIMING_PROPERTIES = \
 "Number of Paths in Error/Verbose Report" 10 \
 "Report Type" "Error Report"
 
-export GEN_PROG_FILE_PROPERTIES := \
+GEN_PROG_FILE_PROPERTIES = \
 "Configuration Rate" 6 \
 "Create Binary Configuration File" TRUE \
 "Done (Output Events)" 5 \
 "Enable Bitstream Compression" TRUE \
 "Enable Outputs (Output Events)" 6 
 
-export SIM_MODEL_PROPERTIES := ""
-
-##################################################
-# Make Options
-##################################################
-all:
-	@echo make proj, check, synth, bin, or clean
-
-proj:
-	PROCESS_RUN="" $(XTCLSH) $(ISE_HELPER)	
-
-check:
-	PROCESS_RUN="Check Syntax" $(XTCLSH) $(ISE_HELPER)	
-
-synth:
-	PROCESS_RUN="Synthesize - XST" $(XTCLSH) $(ISE_HELPER)	
-
-bin:
-	PROCESS_RUN="Generate Programming File" $(XTCLSH) $(ISE_HELPER)		
-
-clean:
-	rm -rf $(BUILD_DIR)
-
-
+SIM_MODEL_PROPERTIES = ""
diff --git a/usrp2/top/u2_core/u2_core.v b/usrp2/top/u2_rev3/u2_core.v
index ad15eef67..f669d9a82 100755..100644
--- a/usrp2/top/u2_core/u2_core.v
+++ b/usrp2/top/u2_rev3/u2_core.v
@@ -582,8 +582,7 @@ module u2_core
       .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty),
       .debug_rx(debug_rx) );
    
-   // dummy_rx dsp_core_rx
-   dsp_core_rx dsp_core_rx
+   dsp_core_rx_old dsp_core_rx_old
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
diff --git a/usrp2/top/u2_core/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index d2e842b1c..cb0ed78c7 100644
--- a/usrp2/top/u2_core/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -279,33 +279,33 @@ module u2_core
    // ///////////////////////////////////////////////////////////////////
    // RAM Loader
 
-   wire [31:0] 	 ram_loader_dat, if_dat;
-   wire [15:0] 	 ram_loader_adr;
-   wire [14:0] 	 if_adr;
+   wire [31:0] 	 ram_loader_dat, iwb_dat;
+   wire [15:0] 	 ram_loader_adr, iwb_adr;
    wire [3:0] 	 ram_loader_sel;
-   wire 	 ram_loader_stb, ram_loader_we;
+   wire 	 ram_loader_stb, ram_loader_we, ram_loader_ack;
    wire 	 iwb_ack, iwb_stb;
    ram_loader #(.AWIDTH(16),.RAM_SIZE(RAM_SIZE))
-     ram_loader (.wb_clk(wb_clk),.dsp_clk(dsp_clk),.ram_loader_rst(ram_loader_rst),
-		 .wb_dat(ram_loader_dat),.wb_adr(ram_loader_adr),
-		 .wb_stb(ram_loader_stb),.wb_sel(ram_loader_sel),
-		 .wb_we(ram_loader_we),
-		 .ram_loader_done(ram_loader_done),
+     ram_loader (.clk_i(wb_clk),.rst_i(ram_loader_rst),
 		 // CPLD Interface
-		 .cpld_clk(cpld_clk),
-		 .cpld_din(cpld_din),
-		 .cpld_start(cpld_start_int),
-		 .cpld_mode(cpld_mode_int),
-		 .cpld_done(cpld_done_int),
-		 .cpld_detached(cpld_detached));
-   
+		 .cfg_clk_i(cpld_clk),
+		 .cfg_data_i(cpld_din),
+		 .start_o(cpld_start_int),
+		 .mode_o(cpld_mode_int),
+		 .done_o(cpld_done_int),
+		 .detached_i(cpld_detached),
+		 // Wishbone Interface
+		 .wb_dat_o(ram_loader_dat),.wb_adr_o(ram_loader_adr),
+		 .wb_stb_o(ram_loader_stb),.wb_cyc_o(),.wb_sel_o(ram_loader_sel),
+		 .wb_we_o(ram_loader_we),.wb_ack_i(ram_loader_ack),
+		 .ram_loader_done_o(ram_loader_done));
+
    // /////////////////////////////////////////////////////////////////////////
    // Processor
    aeMB_core_BE #(.ISIZ(16),.DSIZ(16),.MUL(0),.BSF(1))
      aeMB (.sys_clk_i(wb_clk), .sys_rst_i(wb_rst),
 	   // Instruction Wishbone bus to I-RAM
-	   .if_adr(if_adr),
-	   .if_dat(if_dat),
+	   .iwb_stb_o(iwb_stb),.iwb_adr_o(iwb_adr),
+	   .iwb_dat_i(iwb_dat),.iwb_ack_i(iwb_ack),
 	   // Data Wishbone bus to system bus fabric
 	   .dwb_we_o(m0_we),.dwb_stb_o(m0_stb),.dwb_dat_o(m0_dat_i),.dwb_adr_o(m0_adr),
 	   .dwb_dat_i(m0_dat_o),.dwb_ack_i(m0_ack),.dwb_sel_o(m0_sel),.dwb_cyc_o(m0_cyc),
@@ -319,16 +319,16 @@ module u2_core
    // I-port connects directly to processor and ram loader
 
    wire 	 flush_icache;
-   ram_harvard #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
+   ram_harv_cache #(.AWIDTH(15),.RAM_SIZE(RAM_SIZE),.ICWIDTH(7),.DCWIDTH(6))
      sys_ram(.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),
 	     
 	     .ram_loader_adr_i(ram_loader_adr[14:0]), .ram_loader_dat_i(ram_loader_dat),
 	     .ram_loader_stb_i(ram_loader_stb), .ram_loader_sel_i(ram_loader_sel),
-	     .ram_loader_we_i(ram_loader_we),
+	     .ram_loader_we_i(ram_loader_we), .ram_loader_ack_o(ram_loader_ack),
 	     .ram_loader_done_i(ram_loader_done),
 	     
-	     .if_adr(if_adr), 
-	     .if_data(if_dat), 
+	     .iwb_adr_i(iwb_adr[14:0]), .iwb_stb_i(iwb_stb),
+	     .iwb_dat_o(iwb_dat), .iwb_ack_o(iwb_ack),
 	     
 	     .dwb_adr_i(s0_adr[14:0]), .dwb_dat_i(s0_dat_o), .dwb_dat_o(s0_dat_i),
 	     .dwb_we_i(s0_we), .dwb_ack_o(s0_ack), .dwb_stb_i(s0_stb), .dwb_sel_i(s0_sel),
@@ -690,6 +690,7 @@ module u2_core
    // ///////////////////////////////////////////////////////////////////////////////////
    // External RAM Interface
 
+   /*
    localparam PAGE_SIZE = 10;  // PAGE SIZE is in bytes, 10 = 1024 bytes
 
    wire [15:0] bus2ram, ram2bus;
@@ -719,6 +720,7 @@ module u2_core
 
    assign      RAM_CE1n = 0;
    assign      RAM_D[17:16] = 2'bzz;
+   */
    
    // /////////////////////////////////////////////////////////////////////////
    // VITA Timing
@@ -729,15 +731,15 @@ module u2_core
    
    // /////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
-
-   assign debug_clk[1:0] = 2'b00;
+  
+   assign debug_clk = 2'b00;
    assign debug = 32'd0;
    assign debug_gpio_0 = 32'd0;
    assign debug_gpio_1 = 32'd0;
    
 endmodule // u2_core
 
-   /*
+/*
    // FIFO Level Debugging
    reg [31:0]  host_to_dsp_fifo,dsp_to_host_fifo,eth_mac_debug,serdes_to_dsp_fifo,dsp_to_serdes_fifo;
    
@@ -763,13 +765,16 @@ endmodule // u2_core
    
    assign  debug_clk[0]  = GMII_RX_CLK; // wb_clk;
    assign  debug_clk[1]  = dsp_clk;
-
+*/
+/*
+ 
    wire        mdio_cpy  = MDIO;
    assign  debug 	 = { { 1'b0, s6_stb, s6_ack, s6_we, s6_sel[3:0] },
 			     { s6_adr[15:8] },
 			     { s6_adr[7:0] },
 			     { 6'd0, mdio_cpy, MDC } };
-
+*/
+/*
    assign debug 	 = { { GMII_TXD },
 			     { 5'd0, GMII_TX_EN, GMII_TX_ER, GMII_GTX_CLK },
 			     { wr2_flags, rd2_flags },
@@ -778,23 +783,25 @@ endmodule // u2_core
 			     { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
 			     { wr2_flags, rd2_flags },
 			     { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
+ */
 
-   assign debug = debug_udp;
-   assign debug = vrc_debug;
-   assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state},
+//   assign debug = debug_udp;
+  // assign debug = vrc_debug;
+/*
+  assign debug_gpio_0 = { {pps_in, pps_int, 2'd0, vita_state},
 			   {2'd0, rx_dst_rdy, rx_src_rdy, rx_data[99:96]},
 			   {run_rx_d1, run_rx, strobe_rx, overrun, wr1_flags[3:0]} , 
 			   {wr1_ready_i, wr1_ready_o, rx1_src_rdy, rx1_dst_rdy, rx1_data[35:32]}};
-
-   assign debug_gpio_1 = {vita_time[63:32] };
+*/
+//   assign debug_gpio_1 = {vita_time[63:32] };
    
-   assign debug_gpio_1 = { { tx_f19_data[15:8] },
+/*
+    assign debug_gpio_1 = { { tx_f19_data[15:8] },
 			   { tx_f19_data[7:0] },
 			   { 3'd0, tx_f19_src_rdy, tx_f19_dst_rdy, tx_f19_data[18:16] },
 			   { 2'b0, rd2_ready_i, rd2_ready_o, rd2_flags } };
  */  
    
-
 //   wire        debug_mux;
 //   setting_reg #(.my_addr(5)) sr_debug (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
 //					.in(set_data),.out(debug_mux),.changed());
diff --git a/usrp2/udp/Makefile.srcs b/usrp2/udp/Makefile.srcs
new file mode 100644
index 000000000..293094abe
--- /dev/null
+++ b/usrp2/udp/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# UDP Sources
+##################################################
+UDP_SRCS = $(abspath $(addprefix $(BASE_DIR)/../udp/, \
+udp_wrapper.v \
+fifo19_rxrealign.v \
+prot_eng_tx.v \
+add_onescomp.v \
+))
diff --git a/usrp2/vrt/Makefile.srcs b/usrp2/vrt/Makefile.srcs
new file mode 100644
index 000000000..07c62224b
--- /dev/null
+++ b/usrp2/vrt/Makefile.srcs
@@ -0,0 +1,13 @@
+#
+# Copyright 2010 Ettus Research LLC
+#
+
+##################################################
+# VRT Sources
+##################################################
+VRT_SRCS = $(abspath $(addprefix $(BASE_DIR)/../vrt/, \
+vita_rx_control.v \
+vita_rx_framer.v \
+vita_tx_control.v \
+vita_tx_deframer.v \
+))