Merge branch 'fpga_next' into next

23 files changed, 4958 insertions, 1214 deletions

diff --git a/fpga/usrp2/control_lib/Makefile.srcs b/fpga/usrp2/control_lib/Makefile.srcs
index 0bb9a3efe..42862a50f 100644
--- a/fpga/usrp2/control_lib/Makefile.srcs
+++ b/fpga/usrp2/control_lib/Makefile.srcs
@@ -57,4 +57,5 @@ gpio_atr.v \
 user_settings.v \
 settings_fifo_ctrl.v \
 simple_spi_core.v \
+simple_i2c_core.v \
 ))
diff --git a/fpga/usrp2/control_lib/settings_fifo_ctrl.v b/fpga/usrp2/control_lib/settings_fifo_ctrl.v
index 82651e776..37f11776e 100644
--- a/fpga/usrp2/control_lib/settings_fifo_ctrl.v
+++ b/fpga/usrp2/control_lib/settings_fifo_ctrl.v
@@ -19,6 +19,7 @@
 
 module settings_fifo_ctrl
     #(
+        parameter XPORT_HDR = 1, //extra transport hdr line
         parameter PROT_DEST = 0, //protocol framer destination
         parameter PROT_HDR = 1, //needs a protocol header?
         parameter ACK_SID = 0 //stream ID for packet ACK
@@ -120,6 +121,8 @@ module settings_fifo_ctrl
     localparam WAIT_EOF       = 10;
     localparam STORE_CMD      = 11;
 
+    localparam START_STATE = (XPORT_HDR)? READ_LINE0 : VITA_HDR;
+
     reg [4:0] in_state;
 
     //holdover from current read inputs
@@ -140,13 +143,13 @@ module settings_fifo_ctrl
 
     always @(posedge clock) begin
         if (reset) begin
-            in_state <= READ_LINE0;
+            in_state <= START_STATE;
         end
         else begin
             case (in_state)
 
             READ_LINE0: begin
-                if (reading/* && in_data[32]*/) in_state <= VITA_HDR;
+                if (reading) in_state <= VITA_HDR;
             end
 
             VITA_HDR: begin
@@ -216,7 +219,7 @@ module settings_fifo_ctrl
             end
 
             STORE_CMD: begin
-                if (~command_fifo_full) in_state <= READ_LINE0;
+                if (~command_fifo_full) in_state <= START_STATE;
             end
 
             endcase //in_state
diff --git a/fpga/usrp2/control_lib/simple_i2c_core.v b/fpga/usrp2/control_lib/simple_i2c_core.v
new file mode 100644
index 000000000..9c61de8fb
--- /dev/null
+++ b/fpga/usrp2/control_lib/simple_i2c_core.v
@@ -0,0 +1,116 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// Simple I2C core
+
+// Settings reg map:
+//
+// BASE+0 control register
+//   byte0 - control bits, data byte, or command bits, prescaler
+//   byte1 - what to do? (documented in cpp file)
+//      write prescaler lo
+//      write prescaler hi
+//      write control
+//      write data
+//      write command
+//      read data
+//      read status
+//
+
+// Readback:
+//
+// byte0 has readback value based on the last read command
+//
+
+module simple_i2c_core
+    #(
+        //settings register base address
+        parameter BASE = 0,
+
+        //i2c line level at reset
+        parameter ARST_LVL = 1
+    )
+    (
+        //clock and synchronous reset
+        input clock, input reset,
+
+        //32-bit settings bus inputs
+        input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+        //32-bit data readback
+        output reg [31:0] readback,
+
+        //read is high when i2c core can begin another transaction
+        output reg ready,
+
+        // I2C signals
+        // i2c clock line
+        input  scl_pad_i,       // SCL-line input
+        output scl_pad_o,       // SCL-line output (always 1'b0)
+        output scl_padoen_o,    // SCL-line output enable (active low)
+
+        // i2c data line
+        input  sda_pad_i,       // SDA-line input
+        output sda_pad_o,       // SDA-line output (always 1'b0)
+        output sda_padoen_o,    // SDA-line output enable (active low)
+
+        //optional debug output
+        output [31:0] debug
+    );
+
+    //declare command settings register
+    wire [7:0] sr_what, sr_data;
+    wire sr_changed;
+    setting_reg #(.my_addr(BASE+0),.width(16)) i2c_cmd_sr(
+        .clk(clock),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out({sr_what, sr_data}),.changed(sr_changed));
+
+    //declare wb interface signals
+    wire [2:0] wb_addr;
+    wire [7:0] wb_data_mosi;
+    wire [7:0] wb_data_miso;
+    wire wb_we, wb_stb, wb_cyc;
+    wire wb_ack;
+
+    //create wishbone-based i2c core
+    i2c_master_top #(.ARST_LVL(ARST_LVL)) i2c 
+     (.wb_clk_i(clock),.wb_rst_i(reset),.arst_i(1'b0), 
+      .wb_adr_i(wb_addr),.wb_dat_i(wb_data_mosi),.wb_dat_o(wb_data_miso),
+      .wb_we_i(wb_we),.wb_stb_i(wb_stb),.wb_cyc_i(wb_cyc),
+      .wb_ack_o(wb_ack),.wb_inta_o(),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_padoen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_padoen_o) );
+
+    //not ready between setting register and wishbone ack
+    always @(posedge clock) begin
+        if (reset || wb_ack) ready <= 1;
+        else if (sr_changed) ready <= 0;
+    end
+
+    //register wishbone data on every ack
+    always @(posedge clock) begin
+        if (wb_ack) readback <= {24'b0, wb_data_miso};
+    end
+
+    //assign wishbone signals
+    assign wb_addr = sr_what[2:0];
+    assign wb_stb = sr_changed;
+    assign wb_we = wb_stb && sr_what[3];
+    assign wb_cyc = wb_stb;
+    assign wb_data_mosi = sr_data;
+
+endmodule //simple_i2c_core
diff --git a/fpga/usrp2/fifo/Makefile.srcs b/fpga/usrp2/fifo/Makefile.srcs
index 6cbd5cd3f..55ba0be2a 100644
--- a/fpga/usrp2/fifo/Makefile.srcs
+++ b/fpga/usrp2/fifo/Makefile.srcs
@@ -1,5 +1,5 @@
 #
-# Copyright 2010 Ettus Research LLC
+# Copyright 2010-2012 Ettus Research LLC
 #
 
 ##################################################
@@ -38,4 +38,5 @@ packet_generator.v \
 packet_verifier32.v \
 packet_verifier.v \
 fifo19_pad.v \
+packet_padder36.v \
 ))
diff --git a/fpga/usrp2/fifo/packet_padder36.v b/fpga/usrp2/fifo/packet_padder36.v
new file mode 100644
index 000000000..7197b5ea5
--- /dev/null
+++ b/fpga/usrp2/fifo/packet_padder36.v
@@ -0,0 +1,155 @@
+//
+// Copyright 2011-2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// The packet padder 36 for use with RX VITA stream output.
+// Packet padder understands the concept of USB LUTs,
+// and will forward packets through the interface,
+// adding zero padding as needed to properly flush.
+// The padder will never write a packet across a LUT boundary.
+// When flushing, padder writes out zeros until the LUT boundary.
+// Requires that the input line0 be a VITA header, and SOF set.
+// Flush when the LUT is partially filled and timeout is reached,
+// or when the LUT is partially filled and the DSP is inactive.
+
+module packet_padder36
+#(
+    parameter BASE = 0,
+
+    //default is 16K LUT
+    parameter DEFAULT_LINES32 = 4096,
+
+    //default about 1ms at 64MHz clock
+    parameter DEFAULT_IDLE_CYC = 65536
+)
+(
+    input clk, input reset,
+
+    //setting bus
+    input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+    //input interface
+    input [35:0] data_i,
+    input src_rdy_i,
+    output dst_rdy_o,
+
+    //output interface
+    output [35:0] data_o,
+    output src_rdy_o,
+    input dst_rdy_i,
+
+    input always_flush
+);
+
+    wire lut_lines_changed;
+    wire [15:0] max_lut_lines32;
+    setting_reg #(.my_addr(BASE+0),.width(16),.at_reset(DEFAULT_LINES32)) sr_num_lines(
+        .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(max_lut_lines32),.changed(lut_lines_changed));
+
+    wire idle_cyc_changed;
+    wire [17:0] idle_flush_cycles;
+    setting_reg #(.my_addr(BASE+1),.width(18),.at_reset(DEFAULT_IDLE_CYC)) sr_flush_cyc(
+        .clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),.in(set_data),
+        .out(idle_flush_cycles),.changed(idle_cyc_changed));
+
+    //state machine definitions
+    localparam STATE_READ_HDR = 0;
+    localparam STATE_WRITE_HDR = 1;
+    localparam STATE_FORWARD = 2;
+    localparam STATE_WRITE_PAD = 3;
+    reg [1:0] state;
+
+    //keep track of the outgoing lines
+    reg [15:0] line_count;
+    wire line_count_done = line_count == 1;
+    wire lut_is_empty = line_count == max_lut_lines32;
+    always @(posedge clk) begin
+        if (reset || lut_lines_changed) begin
+            line_count <= max_lut_lines32;
+        end
+        else if (src_rdy_o && dst_rdy_i) begin
+            line_count <= (line_count_done)? max_lut_lines32 : line_count - 1;
+        end
+    end
+
+    //count the number of cycles since RX data so we can force a flush
+    reg [17:0] non_rx_cycles;
+    wire idle_timeout = (non_rx_cycles == idle_flush_cycles);
+    always @(posedge clk) begin
+        if(reset || state != STATE_READ_HDR || idle_cyc_changed) begin
+            non_rx_cycles <= 0;
+        end
+        else if (~idle_timeout) begin
+            non_rx_cycles <= non_rx_cycles + 1;
+        end
+    end
+
+    //flush when we have written data to a LUT and either idle or non active DSP
+    wire force_flush = ~lut_is_empty && (idle_timeout || always_flush);
+
+    //the padding state machine
+    reg [31:0] vita_hdr;
+    reg has_vita_hdr;
+    always @(posedge clk) begin
+        if (reset) begin
+            state <= STATE_READ_HDR;
+        end
+        else case(state)
+
+        STATE_READ_HDR: begin
+            if (src_rdy_i && dst_rdy_o && data_i[32]) begin
+                vita_hdr <= data_i[31:0];
+                has_vita_hdr <= 1;
+                state <= (data_i[15:0] > line_count)? state <= STATE_WRITE_PAD : STATE_WRITE_HDR;
+            end
+            else if (force_flush) begin
+                has_vita_hdr <= 0;
+                state <= STATE_WRITE_PAD;
+            end
+        end
+
+        STATE_WRITE_HDR: begin
+            if (src_rdy_o && dst_rdy_i) begin
+                state <= STATE_FORWARD;
+            end
+        end
+
+        STATE_FORWARD: begin
+            if (src_rdy_i && dst_rdy_o && data_i[33]) begin
+                state <= STATE_READ_HDR;
+            end
+        end
+
+        STATE_WRITE_PAD: begin
+            if (src_rdy_o && dst_rdy_i && line_count_done) begin
+                state <= (has_vita_hdr)? STATE_WRITE_HDR : STATE_READ_HDR;
+            end
+        end
+
+        endcase //state
+    end
+
+    //assign outgoing signals
+    assign dst_rdy_o = (state == STATE_READ_HDR)? 1 : ((state == STATE_FORWARD)? dst_rdy_i : 0);
+    assign src_rdy_o = (state == STATE_WRITE_HDR || state == STATE_WRITE_PAD)? 1 : ((state == STATE_FORWARD )? src_rdy_i : 0);
+    assign data_o = (state == STATE_WRITE_HDR)? {4'b0001, vita_hdr} : ((state == STATE_FORWARD)? data_i : 0);
+
+endmodule // packet_padder36
+
+
+
+
diff --git a/fpga/usrp2/gpif/Makefile.srcs b/fpga/usrp2/gpif/Makefile.srcs
index 524e3660d..7909fb5ff 100644
--- a/fpga/usrp2/gpif/Makefile.srcs
+++ b/fpga/usrp2/gpif/Makefile.srcs
@@ -8,4 +8,6 @@
 GPIF_SRCS = $(abspath $(addprefix $(BASE_DIR)/../gpif/, \
 packet_reframer.v \
 slave_fifo.v \
+fifo36_to_gpmc16.v \
+gpmc16_to_fifo36.v \
 ))
diff --git a/fpga/usrp2/gpif/fifo36_to_gpmc16.v b/fpga/usrp2/gpif/fifo36_to_gpmc16.v
new file mode 100644
index 000000000..508cd319c
--- /dev/null
+++ b/fpga/usrp2/gpif/fifo36_to_gpmc16.v
@@ -0,0 +1,54 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module fifo36_to_gpmc16
+#(
+    parameter FIFO_SIZE = 9
+)
+(
+    //input fifo interface
+    input fifo_clk, input fifo_rst,
+    input [35:0] in_data,
+    input in_src_rdy,
+    output in_dst_rdy,
+
+    //output interface
+    input gpif_clk, input gpif_rst,
+    output [15:0] out_data,
+    output valid,
+    input enable,
+    output eof
+);
+
+    wire [35:0] data_int;
+    wire src_rdy_int, dst_rdy_int;
+
+    fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk
+     (.wclk(fifo_clk), .datain(in_data), .src_rdy_i(in_src_rdy), .dst_rdy_o(in_dst_rdy), .space(),
+      .rclk(gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
+      .arst(fifo_rst | gpif_rst));
+
+    wire [18:0] data18_int;
+    fifo36_to_fifo19 #(.LE(1)) f36_to_f19
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .f19_dataout(data18_int), .f19_src_rdy_o(valid), .f19_dst_rdy_i(enable) );
+
+    assign out_data = data18_int[15:0];
+    assign eof = data18_int[17];
+
+endmodule //fifo_to_gpmc16
diff --git a/fpga/usrp2/gpif/gpmc16_to_fifo36.v b/fpga/usrp2/gpif/gpmc16_to_fifo36.v
new file mode 100644
index 000000000..933891715
--- /dev/null
+++ b/fpga/usrp2/gpif/gpmc16_to_fifo36.v
@@ -0,0 +1,64 @@
+//
+// Copyright 2012 Ettus Research LLC
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module gpmc16_to_fifo36
+#(
+    parameter FIFO_SIZE = 9,
+
+    //not ready until minimum xfers of space available
+    parameter MIN_SPACE16 = 128
+)
+(
+    //input interface
+    input gpif_clk, input gpif_rst,
+    input [15:0] in_data,
+    input valid,
+    output reg ready,
+
+    //output fifo interface
+    input fifo_clk, input fifo_rst,
+    output [35:0] out_data,
+    output out_src_rdy,
+    input out_dst_rdy
+);
+
+    wire [35:0] data_int;
+    wire src_rdy_int, dst_rdy_int;
+    wire [18:0] refr_data;
+    wire refr_src_rdy, refr_dst_rdy;
+
+    wire [15:0] fifo_space;
+
+    always @(posedge gpif_clk)
+        ready <= (fifo_space >= MIN_SPACE16/2);
+
+   packet_reframer packet_reframer 
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .data_i(in_data), .src_rdy_i(valid), .dst_rdy_o(),
+      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy));
+
+   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
+     (.clk(gpif_clk), .reset(gpif_rst), .clear(1'b0),
+      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
+      .f36_dataout(data_int), .f36_src_rdy_o(src_rdy_int), .f36_dst_rdy_i(dst_rdy_int));
+
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(FIFO_SIZE)) fifo_2clk
+     (.wclk(gpif_clk), .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(fifo_space),
+      .rclk(fifo_clk), .dataout(out_data), .src_rdy_o(out_src_rdy), .dst_rdy_i(out_dst_rdy), .occupied(),
+      .arst(fifo_rst | gpif_rst));
+
+endmodule //fifo_to_gpmc16
diff --git a/fpga/usrp2/gpif/slave_fifo.v b/fpga/usrp2/gpif/slave_fifo.v
index d1a0a027b..0f301f8a6 100644
--- a/fpga/usrp2/gpif/slave_fifo.v
+++ b/fpga/usrp2/gpif/slave_fifo.v
@@ -20,85 +20,70 @@
 //this is a FIFO master interface for the FX2 in "slave fifo" mode.
 
 module slave_fifo
-  #(parameter TXFIFOSIZE = 12, parameter RXFIFOSIZE = 12)
+  #(
+        //how many cycles max in a transfer state
+        parameter DATA_XFER_COUNT = 256,
+        parameter CTRL_XFER_COUNT = 32,
+
+        //sizes for fifo36 2 clock cascade fifos
+        parameter DATA_RX_FIFO_SIZE = 9,
+        parameter DATA_TX_FIFO_SIZE = 9,
+        parameter CTRL_RX_FIFO_SIZE = 9,
+        parameter CTRL_TX_FIFO_SIZE = 9
+   )
    (// GPIF signals
     input gpif_clk, input gpif_rst,
     inout [15:0] gpif_d,
     input [3:0] gpif_ctl,
-    output sloe, output slrd, output slwr, output pktend, output [1:0] fifoadr,
-    
-    // Wishbone signals
-    input wb_clk, input wb_rst,
-    output [15:0] wb_adr_o, output [15:0] wb_dat_mosi, input [15:0] wb_dat_miso,
-    output [1:0] wb_sel_o, output wb_cyc_o, output wb_stb_o, output wb_we_o, input wb_ack_i,
-    input [7:0] triggers,
-    
-    input dsp_rx_run,
-    
+    output reg sloe, output reg slrd, output reg slwr, output reg pktend, output reg [1:0] fifoadr,
+
     // FIFO interface
-    input fifo_clk, input fifo_rst, input clear_tx, input clear_rx,
-    output [35:0] tx_data_o, output tx_src_rdy_o, input tx_dst_rdy_i,
-    input [35:0] rx_data_i, input rx_src_rdy_i, output rx_dst_rdy_o,
-    input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
-    output tx_underrun, output rx_overrun,
-    
-    input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl,
-    output [31:0] debug0, output [31:0] debug1
+    input fifo_clk, input fifo_rst,
+    output [35:0] tx_data, output tx_src_rdy, input tx_dst_rdy,
+    input [35:0] rx_data, input rx_src_rdy, output rx_dst_rdy,
+    output [35:0] ctrl_data, output ctrl_src_rdy, input ctrl_dst_rdy,
+    input [35:0] resp_data, input resp_src_rdy, output resp_dst_rdy,
+
+    output [31:0] debug
     );
 
-    reg FX2_DE, FX2_CE, FX2_DF, FX2_CF;
+    wire FX2_DE_pre = ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
+    wire FX2_CE_pre = ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
+    wire FX2_DF_pre = ~gpif_ctl[2]; //EP6 FX2 FIFO full  (FLAGC)
+    wire FX2_CF_pre = ~gpif_ctl[3]; //EP8 FX2 FIFO full  (FLAGD)
 
-   // inputs to FPGA (all active low)
+    reg FX2_DE, FX2_CE, FX2_DF, FX2_CF;
     always @(posedge gpif_clk) begin
-        FX2_DE <= ~gpif_ctl[0]; //EP2 FX2 FIFO empty (FLAGA)
-        FX2_CE <= ~gpif_ctl[1]; //EP4 FX2 FIFO empty (FLAGB)
-        FX2_DF <= ~gpif_ctl[2]; //EP6 FX2 FIFO full  (FLAGC)
-        FX2_CF <= ~gpif_ctl[3]; //EP8 FX2 FIFO full  (FLAGD)
+        FX2_DE <= FX2_DE_pre; //EP2 FX2 FIFO empty (FLAGA)
+        FX2_CE <= FX2_CE_pre; //EP4 FX2 FIFO empty (FLAGB)
+        FX2_DF <= FX2_DF_pre; //EP6 FX2 FIFO full  (FLAGC)
+        FX2_CF <= FX2_CF_pre; //EP8 FX2 FIFO full  (FLAGD)
     end
 
-   wire [17:0] 	  gpif_d_out_ctrl, gpif_d_out_data, gpif_d_out;
+   wire [15:0] gpif_d_out_ctrl, gpif_d_out_data;
+   reg [15:0] gpif_d_out, gpif_d_in;
 
    // ////////////////////////////////////////////////////////////////////
    // GPIF bus master state machine
 
-   //transfer size for GPIF data. this can be anything really, it's specified only for
-   //fairness in bus sharing. 256 lines is 512 bytes over the wire, half the size of
-   //the double buffers in B100/B150. this should probably be a toplevel parameter or even
-   //a settings register value.
-   localparam data_transfer_size = 256;
-   localparam ctrl_transfer_size = 16; //probably unnecessary since ctrl xfers won't back up
-
-   // state machine i/o to four fifos
-   //tx
-   wire ctrl_tx_dst_rdy; //sm input, ctrl tx path has space
-   wire ctrl_tx_src_rdy; //sm output, ctrl tx path enable
-   wire data_tx_dst_rdy; //sm input, data tx path has space
-   wire data_tx_src_rdy; //sm output, data tx path enable
-
-   //rx
-   wire ctrl_rx_dst_rdy; //sm output, ctrl rx path enable
-   wire ctrl_rx_src_rdy; //sm input, ctrl rx path has space
-   wire data_rx_dst_rdy; //sm output, data rx path enable
-   wire data_rx_src_rdy; //sm input, data rx path has space
-
-   reg tx_data_enough_space;
+    wire rx_valid, resp_valid;
+    reg tx_valid, ctrl_valid;
+    wire tx_ready, ctrl_ready;
+    reg rx_enable, resp_enable;
 
    reg [9:0] transfer_count; //number of lines (a line is 16 bits) in active transfer
 
-   reg pktend_latch;
-
    reg [3:0] state; //state machine current state
    localparam STATE_IDLE    = 0;
-   localparam STATE_DATA_RX = 5;
+   localparam STATE_THINK   = 1;
+   localparam STATE_DATA_RX = 2;
    localparam STATE_DATA_TX = 3;
-   localparam STATE_CTRL_RX = 6;
-   localparam STATE_CTRL_TX = 9;
-   localparam STATE_DATA_TX_SLOE = 2;
-   localparam STATE_CTRL_TX_SLOE = 8;
-   localparam STATE_DATA_RX_ADR = 1;
-   localparam STATE_CTRL_RX_ADR = 4;
-   localparam STATE_PKTEND_ADR = 10;
-   localparam STATE_PKTEND = 7;
+   localparam STATE_CTRL_RX = 4;
+   localparam STATE_CTRL_TX = 5;
+   localparam STATE_DATA_TX_SLOE = 6;
+   localparam STATE_CTRL_TX_SLOE = 7;
+   localparam STATE_DATA_RX_ADR = 8;
+   localparam STATE_CTRL_RX_ADR = 9;
 
    //logs the last bus user for xfer fairness
    //we only care about data rx vs. tx since ctrl pkts are so short
@@ -106,384 +91,184 @@ module slave_fifo
    localparam BUS_HOG_RX = 0;
    localparam BUS_HOG_TX = 1;
 
-    //count the number of cycles since RX data so we can force a flush
-    reg [17:0] non_rx_cycles;
-    localparam rx_idle_flush_cycles = 65536; //about 1ms at 64MHz clock
-    always @(posedge gpif_clk) begin
-        if(gpif_rst || state == STATE_DATA_RX || state == STATE_PKTEND)
-            non_rx_cycles <= 0;
-        else if (non_rx_cycles != rx_idle_flush_cycles)
-            non_rx_cycles <= non_rx_cycles + 1;
-    end
-
-    //when should we flush aka pktend?
-    //pktend_latch tells us that its ok to flush -> we just had an RX xfer with EOF
-    //the RX DSP not running or a cycle counter gives us the flushing response dynamic
-    wire rx_data_flush = (~dsp_rx_run || non_rx_cycles == rx_idle_flush_cycles) && pktend_latch;
+    wire resp_eof;
+    reg [1:0] idle_count;
 
    // //////////////////////////////////////////////////////////////
    // FX2 slave FIFO bus master state machine
    //
-   always @(posedge gpif_clk)
-     if(gpif_rst) begin
-       state <= STATE_IDLE;
-       pktend_latch <= 0;
-     end
-     else
-        begin
-       case (state)
-         STATE_IDLE:
-            begin
-           transfer_count <= 0;
-           //handle transitions to other states
-           if(ctrl_tx_dst_rdy & ~FX2_CE) //if there's room in the ctrl fifo and the FX2 has ctrl data
-             state <= STATE_CTRL_TX_SLOE;
-           else if(ctrl_rx_src_rdy & ~FX2_CF) //if the ctrl fifo has data and the FX2 isn't full
-             state <= STATE_CTRL_RX_ADR;
-           else if(data_tx_dst_rdy & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX & tx_data_enough_space) //if there's room in the data fifo and the FX2 has data
-             state <= STATE_DATA_TX_SLOE;
-           else if(data_rx_src_rdy & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) //if the data fifo has data and the FX2 isn't full
-             state <= STATE_DATA_RX_ADR;
-           else if(data_tx_dst_rdy & ~FX2_DE & tx_data_enough_space)
-             state <= STATE_DATA_TX_SLOE;
-           else if(data_rx_src_rdy & ~FX2_DF)
-             state <= STATE_DATA_RX_ADR;
-           else if(rx_data_flush & ~FX2_DF)
-             state <= STATE_PKTEND_ADR;
-            end
-
-         STATE_DATA_TX_SLOE: //just to assert SLOE one cycle before SLRD
-           state <= STATE_DATA_TX;
-         STATE_CTRL_TX_SLOE:
-           state <= STATE_CTRL_TX;
-
-         STATE_DATA_RX_ADR: //just to assert FIFOADR one cycle before SLWR
-           state <= STATE_DATA_RX;
-         STATE_CTRL_RX_ADR:
-           state <= STATE_CTRL_RX;
-
-         STATE_DATA_RX:
-            begin
-                if(data_rx_src_rdy && data_rx_dst_rdy) begin
-                    transfer_count <= transfer_count + 1;
-                    pktend_latch <= gpif_d_out_data[17]; //ok to do pkt end when we complete with EOF
-                end
-                else
-                    state <= STATE_IDLE;
-                last_data_bus_hog <= BUS_HOG_RX;
-            end
-            
-         STATE_PKTEND_ADR:
-            begin
-           state <= STATE_PKTEND;
-            end
-
-         STATE_PKTEND:
-            begin
-           state <= STATE_IDLE;
-           pktend_latch <= 0;
-            end
-            
-         STATE_DATA_TX:
-            begin
-                if(data_tx_dst_rdy && data_tx_src_rdy)
-                    transfer_count <= transfer_count + 1;
-                else
-                    state <= STATE_IDLE;
-                last_data_bus_hog <= BUS_HOG_TX;
-            end
-         STATE_CTRL_RX:
-            begin
-                if(ctrl_rx_src_rdy && ctrl_rx_dst_rdy)
-                    transfer_count <= transfer_count + 1;
-                else
-                    state <= STATE_IDLE;
-            end
-         STATE_CTRL_TX:
-            begin
-                if(ctrl_tx_dst_rdy && ctrl_tx_src_rdy)
-                    transfer_count <= transfer_count + 1;
-                else
-                    state <= STATE_IDLE;
-            end
-       endcase
+    always @(posedge gpif_clk)
+    if(gpif_rst) begin
+        state <= STATE_IDLE;
+        sloe <= 1;
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        rx_enable <= 0;
+        tx_valid <= 0;
+        ctrl_valid <= 0;
+        resp_enable <= 0;
+        idle_count <= 0;
+    end
+    else case (state)
+    STATE_IDLE: begin
+        transfer_count <= 0;
+        sloe <= 1;
+        slrd <= 1;
+        slwr <= 1;
+        pktend <= 1;
+        rx_enable <= 0;
+        tx_valid <= 0;
+        ctrl_valid <= 0;
+        resp_enable <= 0;
+        if (idle_count == 2'b11) state <= STATE_THINK;
+        idle_count <= idle_count + 1;
+    end
+
+    STATE_THINK: begin
+
+        idle_count <= 0;
+
+        //handle transitions to other states
+        if(ctrl_ready & ~FX2_CE) begin //if there's room in the ctrl fifo and the FX2 has ctrl data
+            state <= STATE_CTRL_TX_SLOE;
+            fifoadr <= 2'b01;
+            sloe <= 0;
         end
+        else if(resp_valid & ~FX2_CF) begin //if the ctrl fifo has data and the FX2 isn't full
+            state <= STATE_CTRL_RX_ADR;
+            fifoadr <= 2'b11;
+        end
+        else if(tx_ready & ~FX2_DE & last_data_bus_hog == BUS_HOG_RX) begin //if there's room in the data fifo and the FX2 has data
+            state <= STATE_DATA_TX_SLOE;
+            last_data_bus_hog <= BUS_HOG_TX;
+            fifoadr <= 2'b00;
+            sloe <= 0;
+        end
+        else if(rx_valid & ~FX2_DF & last_data_bus_hog == BUS_HOG_TX) begin //if the data fifo has data and the FX2 isn't full
+            state <= STATE_DATA_RX_ADR;
+            last_data_bus_hog <= BUS_HOG_RX;
+            fifoadr <= 2'b10;
+        end
+        else if(tx_ready & ~FX2_DE) begin
+            state <= STATE_DATA_TX_SLOE;
+            last_data_bus_hog <= BUS_HOG_TX;
+            fifoadr <= 2'b00;
+            sloe <= 0;
+        end
+        else if(rx_valid & ~FX2_DF) begin
+            state <= STATE_DATA_RX_ADR;
+            last_data_bus_hog <= BUS_HOG_RX;
+            fifoadr <= 2'b10;
+        end
+    end
+
+    STATE_DATA_TX_SLOE: begin //just to assert SLOE one cycle before SLRD
+        state <= STATE_DATA_TX;
+        slrd <= 0;
+    end
 
-   // ///////////////////////////////////////////////////////////////////
-   // fifo signal assignments and enables
+    STATE_CTRL_TX_SLOE: begin
+        state <= STATE_CTRL_TX;
+        slrd <= 0;
+    end
 
-   //enable fifos
-   assign data_rx_dst_rdy = (state == STATE_DATA_RX) && ~FX2_DF && (transfer_count != data_transfer_size);
-   assign data_tx_src_rdy = (state == STATE_DATA_TX) && ~FX2_DE && (transfer_count != data_transfer_size);
-   assign ctrl_rx_dst_rdy = (state == STATE_CTRL_RX) && ~FX2_CF;
-   assign ctrl_tx_src_rdy = (state == STATE_CTRL_TX) && ~FX2_CE;
+    STATE_DATA_RX_ADR: begin //just to assert FIFOADR one cycle before SLWR
+        state <= STATE_DATA_RX;
+        rx_enable <= 1;
+    end
 
-   //framing for TX ctrl packets
-   wire sop_ctrl, eop_ctrl;
-   assign sop_ctrl = (transfer_count == 0);
-   assign eop_ctrl = (transfer_count == (ctrl_transfer_size-1));
+    STATE_CTRL_RX_ADR: begin
+        state <= STATE_CTRL_RX;
+        resp_enable <= 1;
+    end
+
+    STATE_DATA_RX: begin
+        if (FX2_DF_pre || ~rx_valid || transfer_count == DATA_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            rx_enable <= 0;
+        end
+        gpif_d_out <= gpif_d_out_data;
+        slwr <= ~rx_valid;
+        transfer_count <= transfer_count + 1;
+    end
+
+    STATE_DATA_TX: begin
+        if (FX2_DE_pre || transfer_count == DATA_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            slrd <= 1;
+        end
+        gpif_d_in <= gpif_d;
+        tx_valid <= 1;
+        transfer_count <= transfer_count + 1;
+    end
+
+    STATE_CTRL_RX: begin
+        if (FX2_CF_pre || ~resp_valid || resp_eof || transfer_count == CTRL_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            resp_enable <= 0;
+        end
+        pktend <= ~resp_eof;
+        gpif_d_out <= gpif_d_out_ctrl;
+        slwr <= ~resp_valid;
+        transfer_count <= transfer_count + 1;
+    end
+
+    STATE_CTRL_TX: begin
+        if (FX2_CE_pre || transfer_count == CTRL_XFER_COUNT-1) begin
+            state <= STATE_IDLE;
+            slrd <= 1;
+        end
+        gpif_d_in <= gpif_d;
+        ctrl_valid <= 1;
+        transfer_count <= transfer_count + 1;
+    end
+    endcase
 
-   // ////////////////////////////////////////////////////////////////////
-   // set GPIF pins
-
-   //set fifoadr to the appropriate endpoint
-   // {0,0}: EP2, data TX from host
-   // {0,1}: EP4, ctrl TX from host
-   // {1,0}: EP6, data RX to host
-   // {1,1}: EP8, ctrl RX to host
-   assign fifoadr = {(state == STATE_DATA_RX) | (state == STATE_CTRL_RX) | (state == STATE_DATA_RX_ADR) | (state == STATE_CTRL_RX_ADR) | (state == STATE_PKTEND) | (state == STATE_PKTEND_ADR),
-                     (state == STATE_CTRL_RX) | (state == STATE_CTRL_RX_ADR) | (state == STATE_CTRL_TX) | (state == STATE_CTRL_TX_SLOE)};
-   //set sloe, slwr, slrd (all active low)
-   //SLOE gets asserted when we want data from the FX2; i.e., TX mode
-   assign sloe = ~{(state == STATE_DATA_TX) | (state == STATE_CTRL_TX) | (state == STATE_DATA_TX_SLOE) | (state == STATE_CTRL_TX_SLOE)};
-   //"read" and "write" here are from the master's point of view;
-   //so "read" means "transmit" and "write" means "receive"
-   assign slwr = ~{(data_rx_src_rdy && data_rx_dst_rdy) || (ctrl_rx_src_rdy && ctrl_rx_dst_rdy)};
-   assign slrd = ~{(data_tx_src_rdy && data_tx_dst_rdy) || (ctrl_tx_src_rdy && ctrl_tx_dst_rdy)};
-
-   wire pktend_ctrl, pktend_data;
-   assign pktend_ctrl = ((~ctrl_rx_src_rdy | gpif_d_out_ctrl[17]) & (state == STATE_CTRL_RX));
-   assign pktend_data = (state == STATE_PKTEND);
-   assign pktend = ~(pktend_ctrl | pktend_data);
-
-   //mux between ctrl/data RX data out based on endpoint selection
-   assign gpif_d_out = fifoadr[0] ? gpif_d_out_ctrl : gpif_d_out_data;
    // GPIF output data lines, tristate
-   assign gpif_d = sloe ? gpif_d_out : 16'bz;
+   assign gpif_d = (sloe)? gpif_d_out[15:0] : 16'bz;
    
    // ////////////////////////////////////////////////////////////////////
    // TX Data Path
 
-   wire [15:0] 	  txfifo_data;
-   wire 	  txfifo_src_rdy, txfifo_dst_rdy;
-   wire [35:0] 	  tx36_data;
-   wire 	  tx36_src_rdy, tx36_dst_rdy;
-   wire [15:0]    data_tx_2clk;
-   wire           tx_src_rdy_2clk, tx_dst_rdy_2clk;
-   
-   wire [15:0] wr_fifo_space;
-
-   always @(posedge gpif_clk)
-     tx_data_enough_space <= (wr_fifo_space >= data_transfer_size);
-
-   fifo_cascade #(.WIDTH(16), .SIZE(12)) wr_fifo
-     (.clk(gpif_clk), .reset(gpif_rst), .clear(clear_tx),
-      .datain(gpif_d), .src_rdy_i(data_tx_src_rdy), .dst_rdy_o(data_tx_dst_rdy), .space(wr_fifo_space),
-      .dataout(txfifo_data), .src_rdy_o(txfifo_src_rdy), .dst_rdy_i(txfifo_dst_rdy), .occupied());
-   
-   fifo_2clock_cascade #(.WIDTH(16), .SIZE(4)) wr_fifo_2clk
-     (.wclk(gpif_clk), .datain(txfifo_data), .src_rdy_i(txfifo_src_rdy), .dst_rdy_o(txfifo_dst_rdy), .space(),
-      .rclk(fifo_clk), .dataout(data_tx_2clk), .src_rdy_o(tx_src_rdy_2clk), .dst_rdy_i(tx_dst_rdy_2clk), .occupied(),
-      .arst(fifo_rst));
-
-   // join vita packets which are longer than one frame, add SOP/EOP/OCC
-   wire [18:0] 	  refr_data;
-   wire 	  refr_src_rdy, refr_dst_rdy;
-   //below 3 signals for debug only
-   wire refr_state;
-   wire refr_eof;
-   wire [15:0] refr_len;
-   
-   packet_reframer tx_packet_reframer 
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .data_i(data_tx_2clk), .src_rdy_i(tx_src_rdy_2clk), .dst_rdy_o(tx_dst_rdy_2clk),
-      .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy),
-      .state(refr_state), .eof_out(refr_eof), .length(refr_len));
-
-   fifo19_to_fifo36 #(.LE(1)) f19_to_f36
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy),
-      .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy));
-   
-   fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .datain(tx36_data), .src_rdy_i(tx36_src_rdy), .dst_rdy_o(tx36_dst_rdy),
-      .dataout(tx_data_o), .src_rdy_o(tx_src_rdy_o), .dst_rdy_i(tx_dst_rdy_i));
+    gpmc16_to_fifo36 #(.FIFO_SIZE(DATA_TX_FIFO_SIZE), .MIN_SPACE16(DATA_XFER_COUNT)) fifo36_to_gpmc16_tx(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .in_data(gpif_d_in), .ready(tx_ready), .valid(tx_valid),
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .out_data(tx_data), .out_src_rdy(tx_src_rdy), .out_dst_rdy(tx_dst_rdy)
+    );
 
    // ////////////////////////////////////////////
    // RX Data Path
 
-   wire [35:0] 	  rx36_data;
-   wire 	  rx36_src_rdy, rx36_dst_rdy;
-   wire [18:0] 	  rx19_data;
-   wire 	  rx19_src_rdy, rx19_dst_rdy;
-   wire [15:0] rxfifospace;
-
-   //deep 36 bit wide input fifo buffers from DSP
-   fifo_cascade #(.WIDTH(36), .SIZE(9)) rx_fifo36
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .datain(rx_data_i), .src_rdy_i(rx_src_rdy_i), .dst_rdy_o(rx_dst_rdy_o),
-      .dataout(rx36_data), .src_rdy_o(rx36_src_rdy), .dst_rdy_i(rx36_dst_rdy));
-
-   //convert to fifo19
-   fifo36_to_fifo19 #(.LE(1)) f36_to_f19
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .f36_datain(rx36_data), .f36_src_rdy_i(rx36_src_rdy), .f36_dst_rdy_o(rx36_dst_rdy),
-      .f19_dataout(rx19_data), .f19_src_rdy_o(rx19_src_rdy), .f19_dst_rdy_i(rx19_dst_rdy) );
-
-   wire [18:0] 	data_rx_int;
-   wire 	rx_src_rdy_int, rx_dst_rdy_int;
-   //clock domain crossing fifo for RX data
-   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk
-     (.wclk(fifo_clk), .datain(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy), .space(),
-      .rclk(~gpif_clk), .dataout(data_rx_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .occupied(),
-      .arst(fifo_rst));
-
-   //rd_fifo buffers writes to the 2clock fifo above
-   fifo_cascade #(.WIDTH(18), .SIZE(RXFIFOSIZE)) rd_fifo
-     (.clk(~gpif_clk), .reset(gpif_rst), .clear(clear_rx),
-      .datain(data_rx_int[17:0]), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .space(rxfifospace),
-      .dataout(gpif_d_out_data), .src_rdy_o(data_rx_src_rdy), .dst_rdy_i(data_rx_dst_rdy), .occupied());
+    fifo36_to_gpmc16 #(.FIFO_SIZE(DATA_RX_FIFO_SIZE)) fifo36_to_gpmc16_rx(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .in_data(rx_data), .in_src_rdy(rx_src_rdy), .in_dst_rdy(rx_dst_rdy),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .out_data(gpif_d_out_data), .valid(rx_valid), .enable(rx_enable)
+    );
 
    // ////////////////////////////////////////////////////////////////////
-   // FIFO to Wishbone interface
+   // CTRL TX Data Path
 
-   wire [18:0] 	  resp_data, resp_int;
-   wire 	  resp_src_rdy, resp_dst_rdy;
-   wire 	  resp_src_rdy_int, resp_dst_rdy_int;
-   
-   wire [18:0] 	  tx_err19_data;
-   wire 	  tx_err19_src_rdy, tx_err19_dst_rdy;
-
-   wire [18:0] 	  ctrl_data;
-   wire 	  ctrl_src_rdy, ctrl_dst_rdy;
-
-   fifo_to_wb fifo_to_wb
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(0),
-      .data_i(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy),
-      .data_o(resp_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int),
-      .wb_adr_o(wb_adr_o), .wb_dat_mosi(wb_dat_mosi), .wb_dat_miso(wb_dat_miso), .wb_sel_o(wb_sel_o), 
-      .wb_cyc_o(wb_cyc_o), .wb_stb_o(wb_stb_o), .wb_we_o(wb_we_o), .wb_ack_i(wb_ack_i),
-      .triggers(triggers),
-      .debug0(), .debug1());
-      
-   // ////////////////////////////////////////////////////////////////////
-   // TX CTRL PATH (ctrl commands into Wishbone)
+    gpmc16_to_fifo36 #(.FIFO_SIZE(CTRL_TX_FIFO_SIZE), .MIN_SPACE16(CTRL_XFER_COUNT)) fifo36_to_gpmc16_ctrl(
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .in_data(gpif_d_in), .ready(ctrl_ready), .valid(ctrl_valid),
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .out_data(ctrl_data), .out_src_rdy(ctrl_src_rdy), .out_dst_rdy(ctrl_dst_rdy)
+    );
 
-   //how does this use fifo_clk instead of wb_clk
-   //answer: on b100 fifo clk IS wb clk
-   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) ctrl_fifo_2clk
-     (.wclk(gpif_clk), .datain({1'b0,eop_ctrl,sop_ctrl,gpif_d}), 
-      .src_rdy_i(ctrl_tx_src_rdy), .dst_rdy_o(ctrl_tx_dst_rdy), .space(),
-      .rclk(fifo_clk), .dataout(ctrl_data), 
-      .src_rdy_o(ctrl_src_rdy), .dst_rdy_i(ctrl_dst_rdy), .occupied(),
-      .arst(fifo_rst));
+   // ////////////////////////////////////////////
+   // CTRL RX Data Path
+
+    fifo36_to_gpmc16 #(.FIFO_SIZE(CTRL_RX_FIFO_SIZE)) fifo36_to_gpmc16_resp(
+        .fifo_clk(fifo_clk), .fifo_rst(fifo_rst),
+        .in_data(resp_data), .in_src_rdy(resp_src_rdy), .in_dst_rdy(resp_dst_rdy),
+        .gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
+        .out_data(gpif_d_out_ctrl), .valid(resp_valid), .enable(resp_enable),
+        .eof(resp_eof)
+    );
 
-   // ////////////////////////////////////////////////////////////////////
-   // RX CTRL PATH (async packets, ctrl response data)
-   
-   //tx_err_data_i is the 36wide tx async err data clocked on fifo_clk
-   fifo36_to_fifo19 #(.LE(1)) f36_to_f19_txerr
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .f36_datain(tx_err_data_i), .f36_src_rdy_i(tx_err_src_rdy_i), .f36_dst_rdy_o(tx_err_dst_rdy_o),
-      .f19_dataout(tx_err19_data), .f19_src_rdy_o(tx_err19_src_rdy), .f19_dst_rdy_i(tx_err19_dst_rdy) );
-
-   //mux FIFO-to-WB along with async tx err pkts into one ctrl resp fifo
-   //how is this clocked on wb_clk?
-   fifo19_mux #(.prio(0)) mux_err_stream
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
-      .data0_i(resp_int), .src0_rdy_i(resp_src_rdy_int), .dst0_rdy_o(resp_dst_rdy_int),
-      .data1_i(tx_err19_data), .src1_rdy_i(tx_err19_src_rdy), .dst1_rdy_o(tx_err19_dst_rdy),
-      .data_o(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy));
-
-   //clock domain crossing cascade fifo for mux_err_stream to get from wb_clk to gpif_clk
-   //the output of this fifo is CTRL DATA PENDING FOR GPIF
-   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) resp_fifo_2clk
-     (.wclk(wb_clk), .datain(resp_data[17:0]), .src_rdy_i(resp_src_rdy), .dst_rdy_o(resp_dst_rdy), .space(),
-      .rclk(~gpif_clk), .dataout(gpif_d_out_ctrl), 
-      .src_rdy_o(ctrl_rx_src_rdy), .dst_rdy_i(ctrl_rx_dst_rdy), .occupied(),
-      .arst(wb_rst));
-
-        
-   // ////////////////////////////////////////////////////////////////////
-   // Debug support, timed and loopback
-   // RX side muxes test data into the same stream
+    assign debug = 0;
 
-   ///////////////////////////////////////////////////////////////////////
-   // debug lines
-   wire [31:0] 	  debug_rd, debug_wr, debug_split0, debug_split1;
-   
-   wire [35:0] 	timedrx_data, loopbackrx_data, testrx_data;
-   wire [35:0] 	timedtx_data, loopbacktx_data, testtx_data;
-   wire 	timedrx_src_rdy, timedrx_dst_rdy, loopbackrx_src_rdy, loopbackrx_dst_rdy,
-		testrx_src_rdy, testrx_dst_rdy;
-   wire 	timedtx_src_rdy, timedtx_dst_rdy, loopbacktx_src_rdy, loopbacktx_dst_rdy,
-		testtx_src_rdy, testtx_dst_rdy;
-   wire 	timedrx_src_rdy_int, timedrx_dst_rdy_int, timedtx_src_rdy_int, timedtx_dst_rdy_int;
-
-   wire [31:0] 	total, crc_err, seq_err, len_err;
-   wire 	sel_testtx = test_ctrl[0];
-   wire 	sel_loopbacktx = test_ctrl[1];
-   wire 	pkt_src_enable = test_ctrl[2];
-   wire 	pkt_sink_enable = test_ctrl[3];
-/*   
-   fifo36_mux rx_test_mux_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(timedrx_data), .src0_rdy_i(timedrx_src_rdy), .dst0_rdy_o(timedrx_dst_rdy),
-      .data1_i(loopbackrx_data), .src1_rdy_i(loopbackrx_src_rdy), .dst1_rdy_o(loopbackrx_dst_rdy),
-      .data_o(testrx_data), .src_rdy_o(testrx_src_rdy), .dst_rdy_i(testrx_dst_rdy));
-   
-   fifo36_mux rx_test_mux_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .data0_i(testrx_data), .src0_rdy_i(testrx_src_rdy), .dst0_rdy_o(testrx_dst_rdy),
-      .data1_i(rx_data_i), .src1_rdy_i(rx_src_rdy_i), .dst1_rdy_o(rx_dst_rdy_o),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
-   
-   fifo_short #(.WIDTH(36)) loopback_fifo
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx | clear_rx),
-      .datain(loopbacktx_data), .src_rdy_i(loopbacktx_src_rdy), .dst_rdy_o(loopbacktx_dst_rdy),
-      .dataout(loopbackrx_data), .src_rdy_o(loopbackrx_src_rdy), .dst_rdy_i(loopbackrx_dst_rdy));
-   
-   // Crossbar used as a demux for switching TX stream to main DSP or to test logic
-   crossbar36 tx_crossbar_lvl_1
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_testtx),
-      .data0_i(tx_data), .src0_rdy_i(tx_src_rdy), .dst0_rdy_o(tx_dst_rdy),
-      .data1_i(tx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(tx_data_o), .src0_rdy_o(tx_src_rdy_o), .dst0_rdy_i(tx_dst_rdy_i),
-      .data1_o(testtx_data), .src1_rdy_o(testtx_src_rdy), .dst1_rdy_i(testtx_dst_rdy) );
-   
-   crossbar36 tx_crossbar_lvl_2
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .cross(sel_loopbacktx),
-      .data0_i(testtx_data), .src0_rdy_i(testtx_src_rdy), .dst0_rdy_o(testtx_dst_rdy),
-      .data1_i(testtx_data), .src1_rdy_i(1'b0), .dst1_rdy_o(),  // No 2nd input
-      .data0_o(timedtx_data), .src0_rdy_o(timedtx_src_rdy), .dst0_rdy_i(timedtx_dst_rdy),
-      .data1_o(loopbacktx_data), .src1_rdy_o(loopbacktx_src_rdy), .dst1_rdy_i(loopbacktx_dst_rdy) );
-   
-   // Fixed rate TX traffic consumer
-   fifo_pacer tx_pacer
-     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_sink_enable),
-      .src1_rdy_i(timedtx_src_rdy), .dst1_rdy_o(timedtx_dst_rdy),
-      .src2_rdy_o(timedtx_src_rdy_int), .dst2_rdy_i(timedtx_dst_rdy_int),
-      .underrun(tx_underrun), .overrun());
-
-   packet_verifier32 pktver32
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx),
-      .data_i(timedtx_data), .src_rdy_i(timedtx_src_rdy_int), .dst_rdy_o(timedtx_dst_rdy_int),
-      .total(total), .crc_err(crc_err), .seq_err(seq_err), .len_err(len_err));
-
-   // Fixed rate RX traffic generator
-   vita_pkt_gen pktgen
-     (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
-      .len(test_len),
-      .data_o(timedrx_data), .src_rdy_o(timedrx_src_rdy_int), .dst_rdy_i(timedrx_dst_rdy_int));
-
-   fifo_pacer rx_pacer
-     (.clk(fifo_clk), .reset(fifo_rst), .rate(test_rate), .enable(pkt_src_enable),
-      .src1_rdy_i(timedrx_src_rdy_int), .dst1_rdy_o(timedrx_dst_rdy_int),
-      .src2_rdy_o(timedrx_src_rdy), .dst2_rdy_i(timedrx_dst_rdy),
-      .underrun(), .overrun(rx_overrun));
-*/
-   // ////////////////////////////////////////////
-   //    DEBUG
-   
-   assign debug0 = { pktend_latch, data_rx_src_rdy, gpif_ctl[3:0], sloe, slrd, slwr, pktend, fifoadr[1:0], state[3:0], gpif_d[15:0]};
-   //assign debug0 = { data_tx_src_rdy, data_tx_dst_rdy, tx_src_rdy_int, tx_dst_rdy_int, 
-   //                  tx19_src_rdy, tx19_dst_rdy, refr_src_rdy, refr_dst_rdy, 
-   //                  tx36_src_rdy, tx36_dst_rdy,
-   //                  gpif_ctl[3:0], fifoadr[1:0], 
-   //                  wr_fifo_space[15:0]};
-   assign debug1 = { 16'b0, transfer_count[7:0], ctrl_rx_src_rdy, ctrl_tx_dst_rdy, data_rx_src_rdy,
-                     data_tx_dst_rdy, ctrl_tx_src_rdy, ctrl_rx_dst_rdy, data_tx_src_rdy, data_rx_dst_rdy};
 endmodule // slave_fifo
diff --git a/fpga/usrp2/models/DCM_SP.v b/fpga/usrp2/models/DCM_SP.v
new file mode 100644
index 000000000..2142fa736
--- /dev/null
+++ b/fpga/usrp2/models/DCM_SP.v
@@ -0,0 +1,1244 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/DCM_SP.v,v 1.9.4.3 2007/04/11 20:30:19 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 9.2i (J.36)
+//  \   \         Description : Xilinx Function Simulation Library Component
+//  /   /                  Digital Clock Manager
+// /___/   /\     Filename : DCM_SP.v
+// \   \  /  \    Timestamp : 
+//  \___\/\___\
+//
+// Revision:
+//    02/28/06 - Initial version.
+//    05/09/06 - Add clkin_ps_mkup and clkin_ps_mkup_win for phase shifting (CR 229789).
+//    06/14/06 - Add clkin_ps_mkup_flag for multiple cycle delays (CR233283).
+//    07/21/06 - Change range of variable phase shifting to +/- integer of 20*(Period-3ns).
+//               Give warning not support initial phase shifting for variable phase shifting.
+//               (CR 235216).
+//    09/22/06 - Add lock_period and lock_fb to clkfb_div block (CR 418722).
+//    12/19/06 - Add clkfb_div_en for clkfb2x divider (CR431210).
+//    04/06/07 - Enable the clock out in clock low time after reset in model 
+//               clock_divide_by_2  (CR 437471).
+// End Revision
+
+
+`timescale  1 ps / 1 ps
+
+module DCM_SP (
+	CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90,
+	CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE, STATUS,
+	CLKFB, CLKIN, DSSEN, PSCLK, PSEN, PSINCDEC, RST);
+
+parameter CLKDV_DIVIDE = 2.0;
+parameter integer CLKFX_DIVIDE = 1;
+parameter integer CLKFX_MULTIPLY = 4;
+parameter CLKIN_DIVIDE_BY_2 = "FALSE";
+parameter CLKIN_PERIOD = 10.0;			// non-simulatable
+parameter CLKOUT_PHASE_SHIFT = "NONE";
+parameter CLK_FEEDBACK = "1X";
+parameter DESKEW_ADJUST = "SYSTEM_SYNCHRONOUS";	// non-simulatable
+parameter DFS_FREQUENCY_MODE = "LOW";
+parameter DLL_FREQUENCY_MODE = "LOW";
+parameter DSS_MODE = "NONE";			// non-simulatable
+parameter DUTY_CYCLE_CORRECTION = "TRUE";
+parameter FACTORY_JF = 16'hC080;		// non-simulatable
+parameter integer MAXPERCLKIN = 1000000;		// non-modifiable simulation parameter
+parameter integer MAXPERPSCLK = 100000000;		// non-modifiable simulation parameter
+parameter integer PHASE_SHIFT = 0;
+parameter integer SIM_CLKIN_CYCLE_JITTER = 300;		// non-modifiable simulation parameter
+parameter integer SIM_CLKIN_PERIOD_JITTER = 1000;	// non-modifiable simulation parameter
+parameter STARTUP_WAIT = "FALSE";		// non-simulatable
+
+
+localparam PS_STEP = 25;
+
+input CLKFB, CLKIN, DSSEN;
+input PSCLK, PSEN, PSINCDEC, RST;
+
+output CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
+output CLKDV, CLKFX, CLKFX180, LOCKED, PSDONE;
+output [7:0] STATUS;
+
+reg CLK0, CLK180, CLK270, CLK2X, CLK2X180, CLK90;
+reg CLKDV, CLKFX, CLKFX180;
+
+wire locked_out_out;
+wire clkfb_in, clkin_in, dssen_in;
+wire psclk_in, psen_in, psincdec_in, rst_in;
+reg clk0_out;
+reg clk2x_out, clkdv_out;
+reg clkfx_out, clkfx180_en;
+reg rst_flag;
+reg locked_out, psdone_out, ps_overflow_out, ps_lock;
+reg clkfb_div, clkfb_chk, clkfb_div_en;
+integer clkdv_cnt;
+
+reg [1:0] clkfb_type;
+reg [8:0] divide_type;
+reg clkin_type;
+reg [1:0] ps_type;
+reg [3:0] deskew_adjust_mode;
+reg dfs_mode_type;
+reg dll_mode_type;
+reg clk1x_type;
+integer ps_in;
+
+reg lock_period, lock_delay, lock_clkin, lock_clkfb;
+reg first_time_locked;
+reg en_status;
+reg ps_overflow_out_ext;
+reg clkin_lost_out_ext;
+reg clkfx_lost_out_ext;
+reg [1:0] lock_out;
+reg lock_out1_neg;
+reg lock_fb, lock_ps, lock_ps_dly, lock_fb_dly, lock_fb_dly_tmp;
+reg fb_delay_found;
+reg clock_stopped;
+reg clkin_chkin, clkfb_chkin;
+
+wire chk_enable, chk_rst;
+wire clkin_div;
+wire lock_period_pulse;
+wire lock_period_dly, lock_period_dly1;
+
+reg clkin_ps, clkin_ps_tmp, clkin_ps_mkup, clkin_ps_mkup_win, clkin_ps_mkup_flag;
+reg clkin_fb;
+
+time FINE_SHIFT_RANGE;
+//time ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range;
+integer ps_delay, ps_delay_init, ps_delay_md, ps_delay_all, ps_max_range;
+integer ps_delay_last;
+integer ps_acc;
+time clkin_edge;
+time clkin_div_edge;
+time clkin_ps_edge;
+time delay_edge;
+time clkin_period [2:0];
+time period;
+integer period_int, period_int2, period_int3, period_ps_tmp;
+time period_div;
+integer period_orig_int;
+time period_orig;
+time period_ps;
+time clkout_delay;
+time fb_delay;
+time period_fx, remain_fx;
+time period_dv_high, period_dv_low;
+time cycle_jitter, period_jitter;
+
+reg clkin_window, clkfb_window;
+reg [2:0] rst_reg;
+reg [12:0] numerator, denominator, gcd;
+reg [23:0] i, n, d, p;
+
+reg notifier;
+
+initial begin
+    #1;
+    if ($realtime == 0) begin
+	$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
+	$display ("In order to simulate the DCM_SP, the simulator resolution must be set to 1ps or smaller.");
+	$finish;
+    end
+end
+
+initial begin
+    case (2.0)
+	1.5  : divide_type = 'd3;
+	2.0  : divide_type = 'd4;
+	2.5  : divide_type = 'd5;
+	3.0  : divide_type = 'd6;
+	3.5  : divide_type = 'd7;
+	4.0  : divide_type = 'd8;
+	4.5  : divide_type = 'd9;
+	5.0  : divide_type = 'd10;
+	5.5  : divide_type = 'd11;
+	6.0  : divide_type = 'd12;
+	6.5  : divide_type = 'd13;
+	7.0  : divide_type = 'd14;
+	7.5  : divide_type = 'd15;
+	8.0  : divide_type = 'd16;
+	9.0  : divide_type = 'd18;
+	10.0 : divide_type = 'd20;
+	11.0 : divide_type = 'd22;
+	12.0 : divide_type = 'd24;
+	13.0 : divide_type = 'd26;
+	14.0 : divide_type = 'd28;
+	15.0 : divide_type = 'd30;
+	16.0 : divide_type = 'd32;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute CLKDV_DIVIDE on DCM_SP instance %m is set to %0.1f.  Legal values for this attribute are 1.5, 2.0, 2.5, 3.0, 3.5, 4.0, 4.5, 5.0, 5.5, 6.0, 6.5, 7.0, 7.5, 8.0, 9.0, 10.0, 11.0, 12.0, 13.0, 14.0, 15.0, or 16.0.", CLKDV_DIVIDE);
+	    $finish;
+	end
+    endcase
+
+    if ((CLKFX_DIVIDE <= 0) || (32 < CLKFX_DIVIDE)) begin
+	$display("Attribute Syntax Error : The attribute CLKFX_DIVIDE on DCM_SP instance %m is set to %d.  Legal values for this attribute are 1 ... 32.", CLKFX_DIVIDE);
+	$finish;
+    end
+
+    if ((CLKFX_MULTIPLY <= 1) || (32 < CLKFX_MULTIPLY)) begin
+	$display("Attribute Syntax Error : The attribute CLKFX_MULTIPLY on DCM_SP instance %m is set to %d.  Legal values for this attribute are 2 ... 32.", CLKFX_MULTIPLY);
+	$finish;
+    end
+
+    case (CLKIN_DIVIDE_BY_2)
+	"false" : clkin_type = 0;
+	"FALSE" : clkin_type = 0;
+	"true"  : clkin_type = 1;
+	"TRUE"  : clkin_type = 1;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute CLKIN_DIVIDE_BY_2 on DCM_SP instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", CLKIN_DIVIDE_BY_2);
+	    $finish;
+	end
+    endcase
+
+    case (CLKOUT_PHASE_SHIFT)
+	"NONE"     : begin
+			 ps_in = 256;
+			 ps_type = 0;
+		     end
+	"none"     : begin
+			 ps_in = 256;
+			 ps_type = 0;
+		     end
+	"FIXED"    : begin
+			 ps_in = PHASE_SHIFT + 256;
+			 ps_type = 1;
+		     end
+	"fixed"    : begin
+			 ps_in = PHASE_SHIFT + 256;
+			 ps_type = 1;
+		     end
+	"VARIABLE" : begin
+			 ps_in = PHASE_SHIFT + 256;
+			 ps_type = 2;
+		     end
+	"variable" : begin
+			 ps_in = PHASE_SHIFT + 256;
+			 ps_type = 2;
+                         if (PHASE_SHIFT != 0)
+	                     $display("Attribute Syntax Warning : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d.  The maximum variable phase shift range is only valid when initial phase shift PHASE_SHIFT is zero.", PHASE_SHIFT);
+		     end
+	default : begin
+	    $display("Attribute Syntax Error : The attribute CLKOUT_PHASE_SHIFT on DCM_SP instance %m is set to %s.  Legal values for this attribute are NONE, FIXED or VARIABLE.", CLKOUT_PHASE_SHIFT);
+	    $finish;
+	end
+    endcase
+
+
+    case (CLK_FEEDBACK)
+	"none" : clkfb_type = 2'b00;
+	"NONE" : clkfb_type = 2'b00;
+	"1x"   : clkfb_type = 2'b01;
+	"1X"   : clkfb_type = 2'b01;
+	"2x"   : clkfb_type = 2'b10;
+	"2X"   : clkfb_type = 2'b10;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute CLK_FEEDBACK on DCM_SP instance %m is set to %s.  Legal values for this attribute are NONE, 1X or 2X.", CLK_FEEDBACK);
+	    $finish;
+	end
+    endcase
+
+    case (DESKEW_ADJUST)
+	"source_synchronous" : deskew_adjust_mode = 8;
+	"SOURCE_SYNCHRONOUS" : deskew_adjust_mode = 8;
+	"system_synchronous" : deskew_adjust_mode = 11;
+	"SYSTEM_SYNCHRONOUS" : deskew_adjust_mode = 11;
+	"0"		     : deskew_adjust_mode = 0;
+	"1"		     : deskew_adjust_mode = 1;
+	"2"		     : deskew_adjust_mode = 2;
+	"3"		     : deskew_adjust_mode = 3;
+	"4"		     : deskew_adjust_mode = 4;
+	"5"		     : deskew_adjust_mode = 5;
+	"6"		     : deskew_adjust_mode = 6;
+	"7"		     : deskew_adjust_mode = 7;
+	"8"		     : deskew_adjust_mode = 8;
+	"9"		     : deskew_adjust_mode = 9;
+	"10"		     : deskew_adjust_mode = 10;
+	"11"		     : deskew_adjust_mode = 11;
+	"12"		     : deskew_adjust_mode = 12;
+	"13"		     : deskew_adjust_mode = 13;
+	"14"		     : deskew_adjust_mode = 14;
+	"15"		     : deskew_adjust_mode = 15;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute DESKEW_ADJUST on DCM_SP instance %m is set to %s.  Legal values for this attribute are SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or 0 ... 15.", DESKEW_ADJUST);
+	    $finish;
+	end
+    endcase
+
+    case (DFS_FREQUENCY_MODE)
+	"high" : dfs_mode_type = 1;
+	"HIGH" : dfs_mode_type = 1;
+	"low"  : dfs_mode_type = 0;
+	"LOW"  : dfs_mode_type = 0;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute DFS_FREQUENCY_MODE on DCM_SP instance %m is set to %s.  Legal values for this attribute are HIGH or LOW.", DFS_FREQUENCY_MODE);
+	    $finish;
+	end
+    endcase
+
+    period_jitter = SIM_CLKIN_PERIOD_JITTER;
+    cycle_jitter = SIM_CLKIN_CYCLE_JITTER;
+
+    case (DLL_FREQUENCY_MODE)
+	"high" : dll_mode_type = 1;
+	"HIGH" : dll_mode_type = 1;
+	"low"  : dll_mode_type = 0;
+	"LOW"  : dll_mode_type = 0;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s.  Legal values for this attribute are HIGH or LOW.", DLL_FREQUENCY_MODE);
+	    $finish;
+	end
+    endcase
+
+    if ((dll_mode_type ==1) && (clkfb_type == 2'b10)) begin
+	    $display("Attribute Syntax Error : The attributes DLL_FREQUENCY_MODE on DCM_SP instance %m is set to %s and CLK_FEEDBACK is set to %s.  CLK_FEEDBACK 2X is not supported when DLL_FREQUENCY_MODE is  HIGH.", DLL_FREQUENCY_MODE, CLK_FEEDBACK);
+           $finish;
+    end 
+
+    case (DSS_MODE)
+	"none" : ;
+	"NONE" : ;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute DSS_MODE on DCM_SP instance %m is set to %s.  Legal values for this attribute is NONE.", DSS_MODE);
+	    $finish;
+	end
+    endcase
+
+    case (DUTY_CYCLE_CORRECTION)
+	"false" : clk1x_type = 0;
+	"FALSE" : clk1x_type = 0;
+	"true"  : clk1x_type = 1;
+	"TRUE"  : clk1x_type = 1;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute DUTY_CYCLE_CORRECTION on DCM_SP instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DUTY_CYCLE_CORRECTION);
+	    $finish;
+	end
+    endcase
+
+    if ((PHASE_SHIFT < -255) || (PHASE_SHIFT > 255)) begin
+	$display("Attribute Syntax Error : The attribute PHASE_SHIFT on DCM_SP instance %m is set to %d.  Legal values for this attribute are -255 ... 255.", PHASE_SHIFT);
+	$display("Error : PHASE_SHIFT = %d is not -255 ... 255.", PHASE_SHIFT);
+	$finish;
+    end
+
+    case (STARTUP_WAIT)
+	"false" : ;
+	"FALSE" : ;
+	"true"  : ;
+	"TRUE"  : ;
+	default : begin
+	    $display("Attribute Syntax Error : The attribute STARTUP_WAIT on DCM_SP instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", STARTUP_WAIT);
+	    $finish;
+	end
+    endcase
+end
+
+//
+// fx parameters
+//
+
+initial begin
+    gcd = 1;
+    for (i = 2; i <= CLKFX_MULTIPLY; i = i + 1) begin
+	if (((CLKFX_MULTIPLY % i) == 0) && ((CLKFX_DIVIDE % i) == 0))
+	    gcd = i;
+    end
+    numerator = CLKFX_MULTIPLY / gcd;
+    denominator = CLKFX_DIVIDE / gcd;
+end
+
+//
+// input wire delays
+//
+
+buf b_clkin (clkin_in, CLKIN);
+buf b_clkfb (clkfb_in, CLKFB);
+buf b_dssen (dssen_in, DSSEN);
+buf b_psclk (psclk_in, PSCLK);
+buf b_psen (psen_in, PSEN);
+buf b_psincdec (psincdec_in, PSINCDEC);
+buf b_rst (rst_in, RST);
+buf #100 b_LOCKED (LOCKED, locked_out_out);
+buf #100 b_PSDONE (PSDONE, psdone_out);
+buf b_ps_overflow (STATUS[0], ps_overflow_out_ext);
+buf b_clkin_lost (STATUS[1], clkin_lost_out_ext);
+buf b_clkfx_lost (STATUS[2], clkfx_lost_out_ext);
+
+assign STATUS[7:3] = 5'b0;
+
+dcm_sp_clock_divide_by_2 i_clock_divide_by_2 (clkin_in, clkin_type, clkin_div, rst_in);
+
+dcm_sp_maximum_period_check #("CLKIN", MAXPERCLKIN) i_max_clkin (clkin_in, rst_in);
+dcm_sp_maximum_period_check #("PSCLK", MAXPERPSCLK) i_max_psclk (psclk_in, rst_in);
+
+dcm_sp_clock_lost i_clkin_lost (clkin_in, first_time_locked, clkin_lost_out, rst_in);
+dcm_sp_clock_lost i_clkfx_lost (CLKFX, first_time_locked, clkfx_lost_out, rst_in);
+
+always @(rst_in or en_status or clkfx_lost_out or clkin_lost_out or ps_overflow_out)
+   if (rst_in == 1 || en_status == 0)  begin
+       ps_overflow_out_ext = 0;
+       clkin_lost_out_ext = 0;
+       clkfx_lost_out_ext = 0;
+    end
+   else
+   begin
+      ps_overflow_out_ext = ps_overflow_out;
+      clkin_lost_out_ext = clkin_lost_out;
+      clkfx_lost_out_ext = clkfx_lost_out;
+   end
+
+always @(posedge rst_in or posedge LOCKED)
+  if (rst_in == 1)
+      en_status <= 0;
+   else
+      en_status <= 1;
+
+
+always @(clkin_div)
+    clkin_ps_tmp <= #(ps_delay_md) clkin_div;
+
+always @(clkin_ps_tmp or clkin_ps_mkup or clkin_ps_mkup_win)
+  if (clkin_ps_mkup_win)
+       clkin_ps = clkin_ps_mkup;
+  else
+       clkin_ps = clkin_ps_tmp;   
+
+always @(ps_delay_last or period_int or ps_delay) begin
+    period_int2 = 2 * period_int;
+    period_int3 = 3 * period_int;
+  if ((ps_delay_last >= period_int  && ps_delay < period_int) ||
+       (ps_delay_last >= period_int2  && ps_delay < period_int2) ||
+       (ps_delay_last >= period_int3  && ps_delay < period_int3))
+           clkin_ps_mkup_flag = 1;
+   else 
+           clkin_ps_mkup_flag = 0;
+end
+
+always @(posedge clkin_div or negedge clkin_div) begin
+ if (ps_type == 2'b10) begin
+  if ((ps_delay_last > 0  && ps_delay <= 0 ) || clkin_ps_mkup_flag == 1) begin 
+     if (clkin_div) begin
+        clkin_ps_mkup_win <= 1;
+        clkin_ps_mkup <= 1;
+        #1;
+        @(negedge clkin_div) begin
+           clkin_ps_mkup_win <= 1;
+           clkin_ps_mkup <= 0;
+        end
+     end
+     else begin
+        clkin_ps_mkup_win <= 0;
+        clkin_ps_mkup <= 0;
+        #1;
+        @(posedge clkin_div) begin
+           clkin_ps_mkup_win <= 1;
+           clkin_ps_mkup <= 1;
+        end 
+        @(negedge clkin_div) begin
+           clkin_ps_mkup_win <= 1;
+           clkin_ps_mkup <= 0;
+        end
+     end
+   end
+   else begin
+        clkin_ps_mkup_win <= 0;
+        clkin_ps_mkup <= 0;
+   end
+   ps_delay_last <= ps_delay;
+ end
+end
+
+always @(clkin_ps or lock_fb)
+    clkin_fb =  clkin_ps & lock_fb;
+
+always @(negedge clkfb_in or posedge rst_in)
+    if (rst_in)
+        clkfb_div_en <= 0;
+    else
+       if (lock_fb_dly && lock_period && lock_fb && ~clkin_ps)
+          clkfb_div_en <= 1;
+
+always @(posedge clkfb_in or posedge rst_in)
+    if (rst_in)
+        clkfb_div <= 0;
+    else
+      if (clkfb_div_en )
+        clkfb_div <= ~clkfb_div;
+
+always @(clkfb_in or clkfb_div )
+    if (clkfb_type == 2'b10 )
+         clkfb_chk = clkfb_div;
+    else 
+         clkfb_chk = clkfb_in & lock_fb_dly;
+
+always @(posedge clkin_fb or posedge chk_rst)
+    if (chk_rst)
+       clkin_chkin <= 0;
+    else 
+       clkin_chkin <= 1;
+
+always @(posedge clkfb_chk or posedge chk_rst)
+    if (chk_rst)
+       clkfb_chkin <= 0;
+    else 
+       clkfb_chkin <= 1;
+
+    assign chk_rst = (rst_in==1 || clock_stopped==1 ) ? 1 : 0;
+    assign chk_enable = (clkin_chkin == 1 && clkfb_chkin == 1 && 
+                         lock_ps ==1 && lock_fb ==1 && lock_fb_dly == 1) ? 1 : 0;
+
+always @(posedge clkin_div or posedge rst_in)
+  if (rst_in) begin
+     period_div <= 0;
+     clkin_div_edge <= 0;
+   end
+  else
+   if ( clkin_div ==1 ) begin
+      clkin_div_edge <= $time;
+      if (($time - clkin_div_edge) <= (1.5 * period_div))
+	  period_div <= $time - clkin_div_edge;
+      else if ((period_div == 0) && (clkin_div_edge != 0))
+	  period_div <= $time - clkin_div_edge;
+   end
+
+always @(posedge clkin_ps or posedge rst_in) 
+  if (rst_in) begin
+        period_ps <= 0;
+        clkin_ps_edge <= 0;
+  end
+  else 
+  if (clkin_ps == 1 ) begin
+    clkin_ps_edge <= $time;
+    if (($time - clkin_ps_edge) <= (1.5 * period_ps))
+	period_ps <= $time - clkin_ps_edge;
+    else if ((period_ps == 0) && (clkin_ps_edge != 0))
+	period_ps <= $time - clkin_ps_edge;
+ end
+
+always @(posedge clkin_ps) begin
+    lock_ps <= lock_period;
+    lock_ps_dly <= lock_ps;
+    lock_fb <= lock_ps_dly;
+    lock_fb_dly_tmp <= lock_fb;
+end
+
+always @(negedge clkin_ps or posedge rst_in) 
+  if (rst_in)
+    lock_fb_dly <= 1'b0;
+  else
+    lock_fb_dly <= #(period/4) lock_fb_dly_tmp;
+
+
+always @(period or fb_delay )
+  if (fb_delay == 0)
+    clkout_delay = 0;
+  else
+    clkout_delay = period - fb_delay;
+
+//
+// generate master reset signal
+//
+
+always @(posedge clkin_in) begin
+    rst_reg[0] <= rst_in;
+    rst_reg[1] <= rst_reg[0] & rst_in;
+    rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst_in;
+end
+
+reg rst_tmp1, rst_tmp2;
+initial
+begin
+rst_tmp1 = 0;
+rst_tmp2 = 0;
+rst_flag = 0;
+end
+
+always @(rst_in) 
+begin
+   if (rst_in)
+       rst_flag = 0;
+
+   rst_tmp1 = rst_in;
+   if (rst_tmp1 == 0 && rst_tmp2 == 1) begin
+      if ((rst_reg[2] & rst_reg[1] & rst_reg[0]) == 0) begin
+         rst_flag = 1;
+	$display("Input Error : RST on instance %m must be asserted for 3 CLKIN clock cycles.");
+      end
+   end
+   rst_tmp2 = rst_tmp1; 
+end
+
+initial begin
+    CLK0 = 0;
+    CLK180 = 0;
+    CLK270 = 0;
+    CLK2X = 0;
+    CLK2X180 = 0;
+    CLK90 = 0;
+    CLKDV = 0;
+    CLKFX = 0;
+    CLKFX180 = 0;
+    clk0_out = 0;
+    clk2x_out = 0;
+    clkdv_out = 0;
+    clkdv_cnt = 0;
+    clkfb_window = 0;
+    clkfx_out = 0;
+    clkfx180_en = 0;
+    clkin_div_edge = 0;
+    clkin_period[0] = 0;
+    clkin_period[1] = 0;
+    clkin_period[2] = 0;
+    clkin_edge = 0;
+    clkin_ps_edge = 0;
+    clkin_window = 0;
+    clkout_delay = 0;
+    clock_stopped = 1;
+    fb_delay  = 0;
+    fb_delay_found = 0;
+    lock_clkfb = 0;
+    lock_clkin = 0;
+    lock_delay = 0;
+    lock_fb = 0;
+    lock_fb_dly = 0;
+    lock_out = 2'b00;
+    lock_out1_neg = 0;
+    lock_period = 0;
+    lock_ps = 0;
+    lock_ps_dly = 0;
+    locked_out = 0;
+    period = 0;
+    period_int = 0;
+    period_int2 = 0;
+    period_int3 = 0;
+    period_div = 0;
+    period_fx = 0;
+    period_orig = 0;
+    period_orig_int = 0;
+    period_ps = 0;
+    psdone_out = 0;
+    ps_delay = 0;
+    ps_delay_md = 0;
+    ps_delay_init = 0;
+    ps_acc = 0;
+    ps_delay_all = 0; 
+    ps_lock = 0;
+    ps_overflow_out = 0;
+    ps_overflow_out_ext = 0;
+    clkin_lost_out_ext = 0;
+    clkfx_lost_out_ext = 0;
+    rst_reg = 3'b000;
+    first_time_locked = 0;
+    en_status = 0;
+    clkfb_div = 0;
+    clkin_chkin = 0;
+    clkfb_chkin = 0;
+    clkin_ps_mkup = 0;
+    clkin_ps_mkup_win = 0;
+    clkin_ps_mkup_flag = 0;
+    ps_delay_last = 0;
+    clkin_ps_tmp = 0;
+end
+
+// RST less than 3 cycles, lock = x
+
+  assign locked_out_out = (rst_flag) ? 1'bx : locked_out;
+
+//
+// detect_first_time_locked
+//
+always @(posedge locked_out)
+  if (first_time_locked == 0)
+          first_time_locked <= 1;
+
+//
+// phase shift parameters
+//
+
+always @(posedge lock_period) 
+    ps_delay_init <= ps_in * period_orig /256;
+
+
+always @(period) begin
+    period_int = period;
+    if (clkin_type==1)
+       period_ps_tmp = 2 * period;
+    else 
+       period_ps_tmp = period;
+
+   if (period_ps_tmp > 3000) 
+        ps_max_range = 20 * (period_ps_tmp - 3000)/1000;
+   else
+     ps_max_range = 0;
+end
+
+always @(ps_delay or rst_in or period_int or lock_period)
+  if ( rst_in)
+       ps_delay_md = 0;
+  else if (lock_period) begin
+       ps_delay_md =   period_int + ps_delay %  period_int;
+  end 
+
+always @(posedge psclk_in or posedge rst_in or posedge lock_period_pulse) 
+  if (rst_in) begin
+     ps_delay <= 0;
+     ps_overflow_out <= 0;
+     ps_acc <= 0;
+  end
+  else if (lock_period_pulse) 
+     ps_delay <= ps_delay_init;
+  else 
+    if (ps_type == 2'b10)
+	if (psen_in) begin
+	    if (ps_lock == 1)
+		  $display(" Warning : Please wait for PSDONE signal before adjusting the Phase Shift.");
+	    else if (lock_ps)  begin
+	      if (psincdec_in == 1) begin
+		if (ps_acc > ps_max_range)
+		    ps_overflow_out <= 1;
+		else begin
+		    ps_delay <= ps_delay  + PS_STEP;
+                    ps_acc <= ps_acc + 1;
+		    ps_overflow_out <= 0;
+		end
+		ps_lock <= 1;
+	      end
+	      else if (psincdec_in == 0) begin
+		if (ps_acc < -ps_max_range)
+		      ps_overflow_out <= 1;
+		else begin
+		    ps_delay <= ps_delay - PS_STEP;
+                    ps_acc <= ps_acc - 1;
+		    ps_overflow_out <= 0;
+		end
+		ps_lock <= 1;
+	      end
+           end
+     end
+
+always @(posedge ps_lock) begin
+    @(posedge clkin_ps)
+    @(posedge psclk_in)
+    @(posedge psclk_in)
+    @(posedge psclk_in)
+	psdone_out <= 1;
+    @(posedge psclk_in)
+	psdone_out <= 0;
+	ps_lock <= 0;
+end
+
+//
+// determine clock period
+//
+
+always @(posedge clkin_div or negedge clkin_div or posedge rst_in)
+  if (rst_in == 1) begin
+    clkin_period[0] <= 0;
+    clkin_period[1] <= 0;
+    clkin_period[2] <= 0;
+    clkin_edge <= 0;
+  end
+  else
+  if (clkin_div == 1) begin
+    clkin_edge <= $time;
+    clkin_period[2] <= clkin_period[1];
+    clkin_period[1] <= clkin_period[0];
+    if (clkin_edge != 0)
+	clkin_period[0] <= $time - clkin_edge;
+  end
+  else if (clkin_div == 0)
+      if (lock_period == 1) 
+        if (100000000 < clkin_period[0]/1000)
+        begin
+        end
+        else if ((period_orig * 2 < clkin_period[0]) && (clock_stopped == 0)) begin
+          clkin_period[0] <= clkin_period[1];
+        end
+
+always @(negedge clkin_div or posedge rst_in) 
+  if (rst_in == 1) begin
+      lock_period <= 0;
+      clock_stopped <= 1;
+  end
+  else begin
+    if (lock_period == 1'b0) begin
+	if ((clkin_period[0] != 0) &&
+		(clkin_period[0] - cycle_jitter <= clkin_period[1]) &&
+		(clkin_period[1] <= clkin_period[0] + cycle_jitter) &&
+		(clkin_period[1] - cycle_jitter <= clkin_period[2]) &&
+		(clkin_period[2] <= clkin_period[1] + cycle_jitter)) begin
+	    lock_period <= 1;
+	    period_orig <= (clkin_period[0] +
+			    clkin_period[1] +
+			    clkin_period[2]) / 3;
+	    period <= clkin_period[0];
+	end
+    end
+    else if (lock_period == 1'b1) begin
+	if (100000000 < (clkin_period[0] / 1000)) begin
+	    $display(" Warning : CLKIN stopped toggling on instance %m exceeds %d ms.  Current CLKIN Period = %1.3f ns.", 100, clkin_period[0] / 1000.0);
+	    lock_period <= 0;
+	    @(negedge rst_reg[2]);
+	end
+	else if ((period_orig * 2 < clkin_period[0]) && clock_stopped == 1'b0) begin
+	    clock_stopped <= 1'b1;
+	end
+	else if ((clkin_period[0] < period_orig - period_jitter) ||
+		(period_orig + period_jitter < clkin_period[0])) begin
+	    $display(" Warning : Input Clock Period Jitter on instance %m exceeds %1.3f ns.  Locked CLKIN Period = %1.3f.  Current CLKIN Period = %1.3f.", period_jitter / 1000.0, period_orig / 1000.0, clkin_period[0] / 1000.0);
+	    lock_period <= 0;
+	    @(negedge rst_reg[2]);
+	end
+	else if ((clkin_period[0] < clkin_period[1] - cycle_jitter) ||
+		(clkin_period[1] + cycle_jitter < clkin_period[0])) begin
+	    $display(" Warning : Input Clock Cycle-Cycle Jitter on instance %m exceeds %1.3f ns.  Previous CLKIN Period = %1.3f.  Current CLKIN Period = %1.3f.", cycle_jitter / 1000.0, clkin_period[1] / 1000.0, clkin_period[0] / 1000.0);
+	    lock_period <= 0;
+	    @(negedge rst_reg[2]);
+	end
+	else begin
+	    period <= clkin_period[0];
+	    clock_stopped <= 1'b0;
+	end
+    end
+end
+
+  assign #1 lock_period_dly1 = lock_period;
+  assign #(period/2) lock_period_dly = lock_period_dly1;
+  assign lock_period_pulse = (lock_period_dly1==1 && lock_period_dly==0) ? 1 : 0;
+
+//
+// determine clock delay
+//
+
+//always @(posedge lock_period or posedge rst_in) 
+always @(posedge lock_ps_dly or posedge rst_in) 
+  if (rst_in) begin
+    fb_delay  <= 0;
+    fb_delay_found <= 0;
+  end
+  else begin
+    if (lock_period && clkfb_type != 2'b00) begin
+	if (clkfb_type == 2'b01) begin
+	    @(posedge CLK0 or rst_in)
+		delay_edge = $time;
+	end
+	else if (clkfb_type == 2'b10) begin
+	    @(posedge CLK2X or rst_in)
+		delay_edge = $time;
+	end
+	@(posedge clkfb_in or rst_in) begin
+	 fb_delay <= ($time - delay_edge) % period_orig;
+         fb_delay_found <= 1;
+       end
+    end
+  end
+
+//
+// determine feedback lock
+//
+
+always @(posedge clkfb_chk or posedge rst_in) 
+  if (rst_in)
+      clkfb_window <= 0;
+  else begin
+      clkfb_window <= 1;
+    #cycle_jitter clkfb_window <= 0;
+  end
+
+always @(posedge clkin_fb or posedge rst_in) 
+  if (rst_in)
+      clkin_window <= 0;
+  else begin
+      clkin_window <= 1;
+    #cycle_jitter clkin_window <= 0;
+  end
+
+always @(posedge clkin_fb or posedge rst_in) 
+  if (rst_in)
+     lock_clkin <= 0;
+  else begin
+    #1
+    if ((clkfb_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1)) 
+	lock_clkin <= 1;
+    else
+       if (chk_enable==1)
+	 lock_clkin <= 0;
+  end
+
+always @(posedge clkfb_chk or posedge rst_in) 
+  if (rst_in)
+    lock_clkfb <= 0;
+  else begin
+    #1
+    if ((clkin_window && fb_delay_found) || (clkin_lost_out == 1'b1 && lock_out[0]==1'b1))  
+	lock_clkfb <= 1;
+    else
+       if (chk_enable ==1)
+	lock_clkfb <= 0;
+  end
+
+always @(negedge clkin_fb or posedge rst_in) 
+  if (rst_in)
+    lock_delay <= 0;
+  else
+    lock_delay <= lock_clkin || lock_clkfb;
+
+//
+// generate lock signal
+//
+
+always @(posedge clkin_ps or posedge rst_in) 
+  if (rst_in) begin
+      lock_out <= 2'b0;
+      locked_out <=0;
+  end
+  else begin
+    if (clkfb_type == 2'b00)
+	lock_out[0] <= lock_period;
+    else
+	lock_out[0] <= lock_period & lock_delay & lock_fb;
+    lock_out[1] <= lock_out[0];
+    locked_out <= lock_out[1];
+  end
+
+always @(negedge clkin_ps or posedge rst_in)
+  if (rst_in)
+    lock_out1_neg <= 0;
+  else
+    lock_out1_neg <= lock_out[1];
+
+
+//
+// generate the clk1x_out
+//
+
+always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in) 
+  if (rst_in) 
+      clk0_out <= 0;
+  else 
+    if (clkin_ps ==1)
+       if (clk1x_type==1 && lock_out[0]) begin
+          clk0_out <= 1;
+          #(period / 2)
+             clk0_out <= 0;
+       end
+       else
+          clk0_out <= 1;
+    else
+      if (clkin_ps == 0 && ((clk1x_type && lock_out[0]) == 0 || (lock_out[0]== 1 && lock_out[1]== 0)))
+          clk0_out <= 0;
+
+//
+// generate the clk2x_out
+//
+
+always @(posedge clkin_ps or posedge rst_in) 
+  if (rst_in)
+     clk2x_out <= 0;
+  else begin
+    clk2x_out <= 1;
+    #(period / 4)
+    clk2x_out <= 0;
+	#(period / 4)
+	clk2x_out <= 1;
+	#(period / 4)
+	clk2x_out <= 0;
+ end
+
+//
+// generate the clkdv_out
+//
+
+always @(posedge clkin_ps or negedge clkin_ps or posedge rst_in)
+  if (rst_in) begin
+       clkdv_out <= 1'b0;
+       clkdv_cnt <= 0;
+  end
+  else
+    if (lock_out1_neg) begin
+      if (clkdv_cnt >= divide_type -1)
+           clkdv_cnt <= 0;
+      else
+           clkdv_cnt <= clkdv_cnt + 1;
+
+      if (clkdv_cnt < divide_type /2)
+          clkdv_out <= 1'b1;
+      else
+         if ( (divide_type[0] == 1'b1) && dll_mode_type == 1'b0)
+             clkdv_out <= #(period/4) 1'b0;
+         else
+            clkdv_out <= 1'b0;
+    end
+
+
+//
+// generate fx output signal
+//
+
+always @(lock_period or period or denominator or numerator) begin
+    if (lock_period == 1'b1) begin
+	period_fx = (period * denominator) / (numerator * 2);
+	remain_fx = (period * denominator) % (numerator * 2);
+    end
+end
+
+always @(posedge clkin_ps or posedge clkin_lost_out or posedge rst_in ) 
+    if (rst_in == 1) 
+       clkfx_out = 1'b0;
+    else if (clkin_lost_out == 1'b1 ) begin
+           if (locked_out == 1)
+            @(negedge rst_reg[2]);
+        end
+    else
+      if (lock_out[1] == 1) begin
+	clkfx_out = 1'b1;
+	for (p = 0; p < (numerator * 2 - 1); p = p + 1) begin
+	    #(period_fx);
+	    if (p < remain_fx)
+		#1;
+	    clkfx_out = !clkfx_out;
+	end
+	if (period_fx > (period / 2)) begin
+	    #(period_fx - (period / 2));
+	end
+      end
+
+//
+// generate all output signal
+//
+
+always @(rst_in)
+if (rst_in) begin
+   assign CLK0 = 0;
+   assign CLK90 = 0;
+   assign CLK180 = 0;
+   assign CLK270 = 0;
+   assign CLK2X = 0;
+   assign CLK2X180 =0;
+   assign CLKDV = 0;
+   assign CLKFX = 0;
+   assign CLKFX180 = 0;
+end
+else begin
+   deassign CLK0;
+   deassign CLK90;
+   deassign CLK180;
+   deassign CLK270;
+   deassign CLK2X;
+   deassign CLK2X180;
+   deassign CLKDV;
+   deassign CLKFX;
+   deassign CLKFX180;
+end
+
+always @(clk0_out) begin
+    CLK0 <= #(clkout_delay) clk0_out && (clkfb_type != 2'b00);
+    CLK90 <= #(clkout_delay + period / 4) clk0_out && !dll_mode_type && (clkfb_type != 2'b00);
+    CLK180 <= #(clkout_delay) ~clk0_out && (clkfb_type != 2'b00);
+    CLK270 <= #(clkout_delay + period / 4) ~clk0_out && !dll_mode_type && (clkfb_type != 2'b00);
+  end
+
+always @(clk2x_out) begin
+    CLK2X <= #(clkout_delay) clk2x_out && !dll_mode_type && (clkfb_type != 2'b00);
+     CLK2X180 <= #(clkout_delay) ~clk2x_out && !dll_mode_type && (clkfb_type != 2'b00);
+end
+
+always @(clkdv_out) 
+    CLKDV <= #(clkout_delay) clkdv_out && (clkfb_type != 2'b00);
+
+always @(clkfx_out )
+    CLKFX <= #(clkout_delay) clkfx_out;
+
+always @( clkfx_out or  first_time_locked or locked_out)
+  if ( ~first_time_locked)
+     CLKFX180 = 0;
+  else
+     CLKFX180 <=  #(clkout_delay) ~clkfx_out;
+
+
+endmodule
+
+//////////////////////////////////////////////////////
+
+module dcm_sp_clock_divide_by_2 (clock, clock_type, clock_out, rst);
+input clock;
+input clock_type;
+input rst;
+output clock_out;
+
+reg clock_out;
+reg clock_div2;
+reg [2:0] rst_reg;
+wire clk_src;
+
+initial begin
+    clock_out = 1'b0;
+    clock_div2 = 1'b0;
+end
+
+always @(posedge clock) 
+    clock_div2 <= ~clock_div2;
+
+always @(posedge clock) begin
+    rst_reg[0] <= rst;
+    rst_reg[1] <= rst_reg[0] & rst;
+    rst_reg[2] <= rst_reg[1] & rst_reg[0] & rst;
+end
+
+assign clk_src = (clock_type) ? clock_div2 : clock;
+
+always @(clk_src or rst or rst_reg) 
+    if (rst == 1'b0)
+        clock_out = clk_src;
+    else if (rst == 1'b1) begin
+        clock_out = 1'b0;
+        @(negedge rst_reg[2]);
+        if (clk_src == 1'b1)
+          @(negedge clk_src);
+    end
+
+
+endmodule
+
+module dcm_sp_maximum_period_check (clock, rst);
+parameter clock_name = "";
+parameter maximum_period = 0;
+input clock;
+input rst;
+
+time clock_edge;
+time clock_period;
+
+initial begin
+    clock_edge = 0;
+    clock_period = 0;
+end
+
+always @(posedge clock) begin
+    clock_edge <= $time;
+//    clock_period <= $time - clock_edge;
+    clock_period = $time - clock_edge;
+    if (clock_period > maximum_period ) begin
+        if (rst == 0) 
+	$display(" Warning : Input clock period of %1.3f ns, on the %s port of instance %m exceeds allowed value of %1.3f ns at time %1.3f ns.", clock_period/1000.0, clock_name, maximum_period/1000.0, $time/1000.0);
+    end
+end
+endmodule
+
+module dcm_sp_clock_lost (clock, enable, lost, rst);
+input clock;
+input enable;
+input rst;
+output lost;
+
+time clock_edge;
+reg [63:0] period;
+reg clock_low, clock_high;
+reg clock_posedge, clock_negedge;
+reg lost_r, lost_f, lost;
+reg clock_second_pos, clock_second_neg;
+
+initial begin
+    clock_edge = 0;
+    clock_high = 0;
+    clock_low = 0;
+    lost_r = 0;
+    lost_f = 0;
+    period = 0;
+    clock_posedge = 0;
+    clock_negedge = 0;
+    clock_second_pos = 0;
+    clock_second_neg = 0;
+end
+
+always @(posedge clock or posedge rst)
+  if (rst==1) 
+    period <= 0;
+  else begin
+    clock_edge <= $time;
+    if (period != 0 && (($time - clock_edge) <= (1.5 * period)))
+        period <= $time - clock_edge;
+    else if (period != 0 && (($time - clock_edge) > (1.5 * period)))
+        period <= 0;
+    else if ((period == 0) && (clock_edge != 0) && clock_second_pos == 1)
+        period <= $time - clock_edge;
+  end
+
+
+always @(posedge clock or posedge rst)
+  if (rst) 
+    lost_r <= 0;
+  else 
+  if (enable == 1 && clock_second_pos == 1) begin
+      #1;
+      if ( period != 0)
+         lost_r <= 0;
+      #((period * 9.1) / 10)
+      if ((clock_low != 1'b1) && (clock_posedge != 1'b1) && rst == 0)
+        lost_r <= 1;
+    end
+
+always @(posedge clock or negedge clock or posedge rst)
+  if (rst) begin
+     clock_second_pos <= 0;
+     clock_second_neg <= 0;
+  end
+  else if (clock)
+     clock_second_pos <= 1;
+  else if (~clock)
+     clock_second_neg <= 1;
+
+always @(negedge clock or posedge rst)
+  if (rst==1) begin
+     lost_f <= 0;
+   end
+   else begin
+     if (enable == 1 && clock_second_neg == 1) begin
+      if ( period != 0)
+        lost_f <= 0;
+      #((period * 9.1) / 10)
+      if ((clock_high != 1'b1) && (clock_negedge != 1'b1) && rst == 0)
+        lost_f <= 1;
+    end
+  end
+
+always @( lost_r or  lost_f or enable)
+begin
+  if (enable == 1)
+         lost = lost_r | lost_f;
+  else
+        lost = 0;
+end
+
+
+always @(posedge clock or negedge clock or posedge rst)
+  if (rst==1) begin
+           clock_low   <= 1'b0;
+           clock_high  <= 1'b0;
+           clock_posedge  <= 1'b0;
+           clock_negedge <= 1'b0;
+  end
+  else begin
+    if (clock ==1) begin
+           clock_low   <= 1'b0;
+           clock_high  <= 1'b1;
+           clock_posedge  <= 1'b0;
+           clock_negedge <= 1'b1;
+    end
+    else if (clock == 0) begin
+           clock_low   <= 1'b1;
+           clock_high  <= 1'b0;
+           clock_posedge  <= 1'b1;
+           clock_negedge <= 1'b0;
+    end
+end
+
+
+endmodule
diff --git a/fpga/usrp2/models/IBUFG.v b/fpga/usrp2/models/IBUFG.v
new file mode 100644
index 000000000..c21cc1dc8
--- /dev/null
+++ b/fpga/usrp2/models/IBUFG.v
@@ -0,0 +1,59 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFG.v,v 1.7 2007/05/23 21:43:34 patrickp Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Input Clock Buffer
+// /___/   /\     Filename : IBUFG.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:24 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    05/23/07 - Changed timescale to 1 ps / 1 ps.
+
+`timescale  1 ps / 1 ps
+
+
+module IBUFG (O, I);
+
+    parameter CAPACITANCE = "DONT_CARE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IOSTANDARD = "DEFAULT";
+
+    output O;
+    input  I;
+
+    buf B1 (O, I);
+    
+    initial begin
+	
+        case (CAPACITANCE)
+
+            "LOW", "NORMAL", "DONT_CARE" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFG instance %m is set to %s.  Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
+                          $finish;
+                      end
+
+        endcase
+
+
+	case (IBUF_DELAY_VALUE)
+
+            "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFG instance %m is set to %s.  Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
+                          $finish;
+                      end
+
+        endcase
+
+    end // initial begin
+    
+endmodule
diff --git a/fpga/usrp2/models/IBUFGDS.v b/fpga/usrp2/models/IBUFGDS.v
new file mode 100644
index 000000000..01c108c8d
--- /dev/null
+++ b/fpga/usrp2/models/IBUFGDS.v
@@ -0,0 +1,87 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IBUFGDS.v,v 1.8 2007/07/26 23:22:55 fphillip Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Differential Signaling Input Clock Buffer
+// /___/   /\     Filename : IBUFGDS.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:42:24 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+//    05/23/07 - Changed timescale to 1 ps / 1 ps.
+//    07/26/07 - Add else to handle x case for o_out (CR 424214).
+// End Revision
+
+
+`timescale  1 ps / 1 ps
+
+
+module IBUFGDS (O, I, IB);
+
+    parameter CAPACITANCE = "DONT_CARE";   
+    parameter DIFF_TERM = "FALSE";
+    parameter IBUF_DELAY_VALUE = "0";
+    parameter IOSTANDARD = "DEFAULT";
+   
+    output O;
+    input  I, IB;
+
+    reg o_out;
+
+    buf b_0 (O, o_out);
+
+    initial begin
+	
+        case (CAPACITANCE)
+
+            "LOW", "NORMAL", "DONT_CARE" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute CAPACITANCE on IBUFGDS instance %m is set to %s.  Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE);
+                          $finish;
+                      end
+
+        endcase
+
+	
+	case (DIFF_TERM)
+
+            "TRUE", "FALSE" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute DIFF_TERM on IBUFGDS instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", DIFF_TERM);
+                          $finish;
+                      end
+
+	endcase
+
+	
+	case (IBUF_DELAY_VALUE)
+
+            "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IBUFGDS instance %m is set to %s.  Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE);
+                          $finish;
+                      end
+
+        endcase
+	
+    end
+    
+    always @(I or IB) begin
+	if (I == 1'b1 && IB == 1'b0)
+	    o_out <= I;
+	else if (I == 1'b0 && IB == 1'b1)
+	    o_out <= I;
+        else if (I == 1'bx && IB == 1'bx)
+            o_out <= 1'bx;
+    end
+
+endmodule
+
+
diff --git a/fpga/usrp2/models/IDDR2.v b/fpga/usrp2/models/IDDR2.v
new file mode 100644
index 000000000..727f1c568
--- /dev/null
+++ b/fpga/usrp2/models/IDDR2.v
@@ -0,0 +1,172 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/IDDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Dual Data Rate Input D Flip-Flop
+// /___/   /\     Filename : IDDR2.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:43:51 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+
+`timescale  1 ps / 1 ps
+
+module IDDR2 (Q0, Q1, C0, C1, CE, D, R, S);
+    
+    output Q0;
+    output Q1;
+    
+    input C0;
+    input C1;
+    input CE;
+    input D;
+    tri0 GSR = glbl.GSR;
+    input R;
+    input S;
+
+    parameter DDR_ALIGNMENT = "NONE";
+    parameter INIT_Q0 = 1'b0;
+    parameter INIT_Q1 = 1'b0;
+    parameter SRTYPE = "SYNC";
+
+    reg q0_out, q1_out;
+    reg q0_out_int, q1_out_int;
+    reg q0_c1_out_int, q1_c0_out_int;
+    
+    buf buf_q0 (Q0, q0_out);
+    buf buf_q1 (Q1, q1_out);
+
+    
+    initial begin
+
+	if ((INIT_Q0 != 1'b0) && (INIT_Q0 != 1'b1)) begin
+	    $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q0);
+	    $finish;
+	end
+	
+    	if ((INIT_Q1 != 1'b0) && (INIT_Q1 != 1'b1)) begin
+	    $display("Attribute Syntax Error : The attribute INIT_Q0 on IDDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT_Q1);
+	    $finish;
+	end
+
+    	if ((DDR_ALIGNMENT != "C1") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "NONE")) begin
+	    $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on IDDR2 instance %m is set to %s.  Legal values for this attribute are C0, C1 or NONE.", DDR_ALIGNMENT);
+	    $finish;
+	end
+	
+	if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
+	    $display("Attribute Syntax Error : The attribute SRTYPE on IDDR2 instance %m is set to %s.  Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
+	    $finish;
+	end
+
+    end // initial begin
+
+
+    always @(GSR or R or S) begin
+
+	if (GSR == 1) begin
+
+	    assign q0_out_int = INIT_Q0;
+	    assign q1_out_int = INIT_Q1;
+	    assign q0_c1_out_int = INIT_Q0;
+	    assign q1_c0_out_int = INIT_Q1;
+
+	end
+	else begin
+	    
+	    deassign q0_out_int;
+	    deassign q1_out_int;
+	    deassign q0_c1_out_int;
+	    deassign q1_c0_out_int;
+	    
+	    if (SRTYPE == "ASYNC") begin
+		if (R == 1) begin
+		    assign q0_out_int = 0;
+		    assign q1_out_int = 0;
+		    assign q0_c1_out_int = 0;
+		    assign q1_c0_out_int = 0;
+		end
+		else if (R == 0 && S == 1) begin
+		    assign q0_out_int = 1;
+		    assign q1_out_int = 1;
+		    assign q0_c1_out_int = 1;
+		    assign q1_c0_out_int = 1;
+		end
+	    end // if (SRTYPE == "ASYNC")
+	    
+	end // if (GSR == 1'b0)
+	
+    end // always @ (GSR or R or S)
+
+	    
+    always @(posedge C0) begin
+ 	if (R == 1 && SRTYPE == "SYNC") begin
+	    q0_out_int <= 0;
+	    q1_c0_out_int <= 0;
+	end
+	else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
+	    q0_out_int <= 1;
+	    q1_c0_out_int <= 1;
+	end
+	else if (CE == 1 && R == 0 && S == 0) begin
+            q0_out_int <= D;
+	    q1_c0_out_int <= q1_out_int;
+	end
+    end // always @ (posedge C0)
+
+    
+    always @(posedge C1) begin
+ 	if (R == 1 && SRTYPE == "SYNC") begin
+	    q1_out_int <= 0;
+	    q0_c1_out_int <= 0;
+	end
+	else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
+	    q1_out_int <= 1;
+	    q0_c1_out_int <= 1;
+	end
+	else if (CE == 1 && R == 0 && S == 0) begin
+            q1_out_int <= D;
+	    q0_c1_out_int <= q0_out_int;
+	end
+    end // always @ (posedge C1)
+    
+    
+    always @(q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int) begin
+
+	case (DDR_ALIGNMENT)
+	    "NONE" : begin
+		       q0_out <= q0_out_int;
+		       q1_out <= q1_out_int;
+	             end
+	    "C0" : begin
+	               q0_out <= q0_out_int;
+	               q1_out <= q1_c0_out_int;
+	           end
+	    "C1" : begin
+		       q0_out <= q0_c1_out_int;
+                       q1_out <= q1_out_int;
+	           end
+	endcase // case(DDR_ALIGNMENT)
+
+    end // always @ (q0_out_int or q1_out_int or q1_c0_out_int or q0_c1_out_int)
+    
+
+    specify
+
+	if (C0) (C0 => Q0) = (100, 100);
+	if (C0) (C0 => Q1) = (100, 100);
+	if (C1) (C1 => Q1) = (100, 100);
+	if (C1) (C1 => Q0) = (100, 100);
+	specparam PATHPULSE$ = 0;
+
+    endspecify
+
+endmodule // IDDR2
+
diff --git a/fpga/usrp2/models/ODDR2.v b/fpga/usrp2/models/ODDR2.v
new file mode 100644
index 000000000..67e71761d
--- /dev/null
+++ b/fpga/usrp2/models/ODDR2.v
@@ -0,0 +1,157 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/spartan4/ODDR2.v,v 1.1 2004/06/21 21:45:36 wloo Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Functional Simulation Library Component
+//  /   /                  Dual Data Rate Output D Flip-Flop
+// /___/   /\     Filename : ODDR2.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:43:52 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/23/04 - Initial version.
+
+`timescale 1 ps / 1 ps
+
+module ODDR2 (Q, C0, C1, CE, D0, D1, R, S);
+    
+    output Q;
+
+    input C0;
+    input C1;
+    input CE;
+    input D0;
+    input D1;
+    tri0 GSR = glbl.GSR;
+    input R;
+    input S;
+
+    parameter DDR_ALIGNMENT = "NONE";    
+    parameter INIT = 1'b0;
+    parameter SRTYPE = "SYNC";
+
+    reg q_out, q_d0_c1_out_int, q_d1_c0_out_int;    
+    
+    buf buf_q (Q, q_out);
+
+
+    initial begin
+
+	if ((INIT != 1'b0) && (INIT != 1'b1)) begin
+	    $display("Attribute Syntax Error : The attribute INIT on ODDR2 instance %m is set to %d.  Legal values for this attribute are 0 or 1.", INIT);
+	    $finish;
+	end
+	
+    	if ((DDR_ALIGNMENT != "NONE") && (DDR_ALIGNMENT != "C0") && (DDR_ALIGNMENT != "C1")) begin
+	    $display("Attribute Syntax Error : The attribute DDR_ALIGNMENT on ODDR2 instance %m is set to %s.  Legal values for this attribute are NONE, C0 or C1.", DDR_ALIGNMENT);
+	    $finish;
+	end
+	
+	if ((SRTYPE != "ASYNC") && (SRTYPE != "SYNC")) begin
+	    $display("Attribute Syntax Error : The attribute SRTYPE on ODDR2 instance %m is set to %s.  Legal values for this attribute are ASYNC or SYNC.", SRTYPE);
+	    $finish;
+	end
+
+    end // initial begin
+    
+
+    always @(GSR or R or S) begin
+
+	if (GSR == 1) begin
+
+	    assign q_out = INIT;
+	    assign q_d0_c1_out_int = INIT;
+	    assign q_d1_c0_out_int = INIT;
+
+	end
+	else begin
+
+	    deassign q_out;
+	    deassign q_d0_c1_out_int;
+	    deassign q_d1_c0_out_int;
+	    
+	    if (SRTYPE == "ASYNC") begin
+		if (R == 1) begin
+		    assign q_out = 0;
+		    assign q_d0_c1_out_int = 0;
+		    assign q_d1_c0_out_int = 0;
+		end
+		else if (R == 0 && S == 1) begin
+		    assign q_out = 1;
+		    assign q_d0_c1_out_int = 1;
+		    assign q_d1_c0_out_int = 1;
+		end
+	    end // if (SRTYPE == "ASYNC")
+	    
+	end // if (GSR == 1'b0)
+	
+    end // always @ (GSR or R or S)
+
+    
+    always @(posedge C0) begin
+	
+ 	if (R == 1 && SRTYPE == "SYNC") begin
+	    q_out <= 0;
+	    q_d1_c0_out_int <= 0;
+	end
+	else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
+	    q_out <= 1;
+	    q_d1_c0_out_int <= 1;
+	end
+	else if (CE == 1 && R == 0 && S == 0) begin
+	    
+	    if (DDR_ALIGNMENT == "C1")
+		q_out <= q_d0_c1_out_int;
+	    else begin 
+		q_out <= D0;
+		
+		if (DDR_ALIGNMENT == "C0")
+		    q_d1_c0_out_int <= D1;
+	    end
+	    
+	end // if (CE == 1 && R == 0 && S == 0)
+	
+    end // always @ (posedge C0)
+    
+    
+    always @(posedge C1) begin
+	
+	if (R == 1 && SRTYPE == "SYNC") begin
+	    q_out <= 0;
+	    q_d0_c1_out_int <= 0;
+	end
+	else if (R == 0 && S == 1 && SRTYPE == "SYNC") begin
+	    q_out <= 1;
+	    q_d0_c1_out_int <= 1;
+	    end
+	else if (CE == 1 && R == 0 && S == 0) begin
+	    
+	    if (DDR_ALIGNMENT == "C0")
+		q_out <= q_d1_c0_out_int;
+	    else begin 
+		q_out <= D1;
+		
+		if (DDR_ALIGNMENT == "C1")
+		    q_d0_c1_out_int <= D0;
+	    end
+	    
+	end // if (CE == 1 && R == 0 && S == 0)
+	
+    end // always @ (negedge c_in)
+    
+    
+    specify
+
+	if (C0) (C0 => Q) = (100, 100);
+	if (C1) (C1 => Q) = (100, 100);
+	specparam PATHPULSE$ = 0;
+
+    endspecify
+
+endmodule // ODDR2
+
diff --git a/fpga/usrp2/models/PLL_ADV.v b/fpga/usrp2/models/PLL_ADV.v
new file mode 100644
index 000000000..d6a26e541
--- /dev/null
+++ b/fpga/usrp2/models/PLL_ADV.v
@@ -0,0 +1,2142 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/PLL_ADV.v,v 1.43.4.1 2007/12/07 01:25:16 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Function Simulation Library Component
+//  /   /                  Phase Lock Loop Clock
+// /___/   /\     Filename : PLL_ADV.v
+// \   \  /  \    Timestamp : Thu Mar 25 16:44:07 PST 2004
+//  \___\/\___\
+//
+// Revision:
+//    03/15/05 - Initial version.
+//    10/14/05 - Add REL pin.
+//    11/07/05 - Add PMCD.
+//    12/02/05 - Change parameter default values. Add DRP read/write.
+//    12/22/05 - CR 222805 222809 fix.
+//    01/03/06 - Change RST_DEASSER_CLK value to CLKIN1 and CLKFB (BT#735).
+//    01/11/06 - Remove GSR from reset logic of PLL (CR 223099).
+//    01/26/06 - Add reset to locked logic (CR224502).
+//    02/16/06 - Support -360 6o +360 phase shifting (CR 225765)
+//    03/10/06 - Add parameter type declaration (CR 226003)
+//    03/17/06 - Using assign/deassign to reset pll_locked_tmp2  and reduce
+//               lock time by MD (CR 224502).
+//    04/19/06 - Change i to i1 and i2 in clkvco_lk. (CR230260).
+//    07/17/06 - Remove i2 and first 4 clkvco_lk cycle generation (CR234931).
+//    08/23/06 - Use clkout_en_tmp to generate clkout_en0; Use block statement to 
+//               reset clock stop counter and flag. (CR422250)
+//    09/19/06 - md_product update (CR 424286).
+//    09/27/06 - Add error check for RESET_ON_LOSS_OF_LOCK (CR 425255).
+//    11/10/06 - Keep 3 digits for real in duty cycle check function. (CR 428703).
+//    01/12/07 - Add CLKOUT_DESKEW_ADJUST parameters (CR 432189).
+//    03/30/07 - Fix error message for CLKSEL change in RST=0 (CR 436927).
+//    04/09/07 - Enhance error message for RESET_ON_LOSS_OF_LOCK (CR 437405).
+//    04/10/07 - Using assign/deassign to reset signals with # delay (CR 437660).
+//    05/22/07 - Add setup check for REL (438781).
+//    06/04/07 - Add wire declaration to internal signal.
+//    06/8/07  - Generate clkfb_tst when GSR=0; 
+//             - Chang VCOCLK_FREQ_MAX and VCOCLK_FREQ_MIN to parameter for simprim (BT1485).
+//    06/18/07 - Improve error message for VCO (CR ). Initialize DRP mem (CR ).
+//             - Add CLKFBIN pulse width check (BT1476).
+//    06/28/07 - Initial DRP memory (CR 434042), Error message improve (CR 438250).
+//    07/11/07 - change daddr_in to 5 bits (CR 443757).
+//    08/02/07 - Remove numbers from CLKOUT DESKEW_ADJUST check (CR443161).
+//    08/21/07 - Not check CLKIN period when PMCD mode set (445101).
+//               Fix DUTY_CYCLE_MAX formula in case of divider larger than O_MAX_HT_LT (CR445945).
+//               Add warning if phase shift over pll ability (63 vco) (CR446037).
+//    09/20/07 - Seperate fb_delay and delay_edge to handle 0 fb_delay (CR448938)
+//    10/23/07 - Add warnings to initial phase shift calculation (CR448965)
+//    11/01/07 - Remove zero check for CLKOUTx dly register bit15-8 (CR434042)
+//    12/06/07 - Add I/O buf to simprim (CR456124)
+// End Revision
+
+
+`timescale  1 ps / 1 ps
+`define PLL_LOCK_TIME 7
+
+
+module PLL_ADV (
+        CLKFBDCM,
+        CLKFBOUT,
+        CLKOUT0,
+        CLKOUT1,
+        CLKOUT2,
+        CLKOUT3,
+        CLKOUT4,
+        CLKOUT5,
+        CLKOUTDCM0,
+        CLKOUTDCM1,
+        CLKOUTDCM2,
+        CLKOUTDCM3,
+        CLKOUTDCM4,
+        CLKOUTDCM5,
+        DO,
+        DRDY,
+        LOCKED,
+        CLKFBIN,
+        CLKIN1,
+        CLKIN2,
+        CLKINSEL,
+        DADDR,
+        DCLK,
+        DEN,
+        DI,
+        DWE,
+        REL,
+        RST
+);
+
+parameter BANDWIDTH = "OPTIMIZED";
+parameter CLKFBOUT_DESKEW_ADJUST = "NONE";
+parameter CLKOUT0_DESKEW_ADJUST = "NONE";
+parameter CLKOUT1_DESKEW_ADJUST = "NONE";
+parameter CLKOUT2_DESKEW_ADJUST = "NONE";
+parameter CLKOUT3_DESKEW_ADJUST = "NONE";
+parameter CLKOUT4_DESKEW_ADJUST = "NONE";
+parameter CLKOUT5_DESKEW_ADJUST = "NONE";
+parameter integer CLKFBOUT_MULT = 1;
+parameter real CLKFBOUT_PHASE = 0.0;
+parameter real CLKIN1_PERIOD = 0.000;
+parameter real CLKIN2_PERIOD = 0.000;
+parameter integer CLKOUT0_DIVIDE = 1;
+parameter real CLKOUT0_DUTY_CYCLE = 0.5;
+parameter real CLKOUT0_PHASE = 0.0;
+parameter integer CLKOUT1_DIVIDE = 1;
+parameter real CLKOUT1_DUTY_CYCLE = 0.5;
+parameter real CLKOUT1_PHASE = 0.0;
+parameter integer CLKOUT2_DIVIDE = 1;
+parameter real CLKOUT2_DUTY_CYCLE = 0.5;
+parameter real CLKOUT2_PHASE = 0.0;
+parameter integer CLKOUT3_DIVIDE = 1;
+parameter real CLKOUT3_DUTY_CYCLE = 0.5;
+parameter real CLKOUT3_PHASE = 0.0;
+parameter integer CLKOUT4_DIVIDE = 1;
+parameter real CLKOUT4_DUTY_CYCLE = 0.5;
+parameter real CLKOUT4_PHASE = 0.0;
+parameter integer CLKOUT5_DIVIDE = 1;
+parameter real CLKOUT5_DUTY_CYCLE = 0.5;
+parameter real CLKOUT5_PHASE = 0.0;
+parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
+parameter integer DIVCLK_DIVIDE = 1;
+parameter EN_REL = "FALSE";
+parameter PLL_PMCD_MODE = "FALSE";
+parameter real REF_JITTER = 0.100;
+parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
+parameter RST_DEASSERT_CLK = "CLKIN1";
+
+localparam VCOCLK_FREQ_MAX = 1100;
+localparam VCOCLK_FREQ_MIN = 400;
+
+output CLKFBDCM;
+output CLKFBOUT;
+output CLKOUT0;
+output CLKOUT1;
+output CLKOUT2;
+output CLKOUT3;
+output CLKOUT4;
+output CLKOUT5;
+output CLKOUTDCM0;
+output CLKOUTDCM1;
+output CLKOUTDCM2;
+output CLKOUTDCM3;
+output CLKOUTDCM4;
+output CLKOUTDCM5;
+output DRDY;
+output LOCKED;
+output [15:0] DO;
+
+input CLKFBIN;
+input CLKIN1;
+input CLKIN2;
+input CLKINSEL;
+input DCLK;
+input DEN;
+input DWE;
+input REL;
+input RST;
+input [15:0] DI;
+input [4:0] DADDR;
+
+localparam VCOCLK_FREQ_TARGET = 800;
+localparam CLKIN_FREQ_MAX = 1000;
+localparam CLKIN_FREQ_MIN = 1;    //need check speed file, current is TBD
+localparam CLKPFD_FREQ_MAX = 550;
+localparam CLKPFD_FREQ_MIN = 1;   //need check speed file, current is TBD
+localparam M_MIN = 1;
+localparam M_MAX = 74;
+localparam D_MIN = 1;
+localparam D_MAX = 52;
+localparam O_MIN = 1;
+localparam O_MAX = 128;
+localparam O_MAX_HT_LT = 64;
+localparam REF_CLK_JITTER_MAX = 350;
+localparam REF_CLK_JITTER_SCALE = 0.1;
+localparam MAX_FEEDBACK_DELAY = 10.0;
+localparam MAX_FEEDBACK_DELAY_SCALE = 1.0;
+
+tri0 GSR = glbl.GSR;
+
+reg [4:0] daddr_lat;
+reg valid_daddr;
+reg drdy_out;
+reg drp_lock, drp_lock1;
+reg [15:0] dr_sram [31:0];
+reg [160:0] tmp_string;
+
+wire CLKFBIN, CLKIN1, CLKIN2, CLKINSEL ;
+wire rst_in, RST, orig_rst_in ;
+wire locked_out;
+wire clkvco_lk_rst;
+
+reg clk0_out, clk1_out, clk2_out, clk3_out, clk4_out, clk5_out;
+reg clkfb_out, clkfbm1_out;
+reg clkout_en, clkout_en1, clkout_en0, clkout_en0_tmp;
+integer clkout_cnt, clkin_cnt, clkin_lock_cnt;
+integer clkout_en_time, locked_en_time, lock_cnt_max;
+reg clkvco_lk, clkvco_free, clkvco;
+reg fbclk_tmp;
+
+reg rst_in1, rst_unlock, rst_on_loss;
+time rst_edge, rst_ht;
+
+reg fb_delay_found, fb_delay_found_tmp;
+reg clkfb_tst;
+real fb_delay_max;
+time fb_delay, clkvco_delay, val_tmp, dly_tmp,  fbm1_comp_delay;
+time clkin_edge, delay_edge;
+
+real     period_clkin;
+integer  clkin_period [4:0];
+integer  period_vco, period_vco_half, period_vco_max, period_vco_min;
+integer  period_vco1, period_vco2, period_vco3, period_vco4;
+integer  period_vco5, period_vco6, period_vco7;
+integer  period_vco_target, period_vco_target_half;
+integer  period_fb, period_avg;
+
+real    clkvco_freq_init_chk, clkfbm1pm_rl;
+real    tmp_real;
+integer i, j, i1, i2;
+integer md_product, md_product_dbl, clkin_stop_max, clkfb_stop_max;
+
+time pll_locked_delay, clkin_dly_t, clkfb_dly_t;
+reg clkpll_dly, clkfbin_dly;
+wire pll_unlock;
+reg pll_locked_tmp1, pll_locked_tmp2;
+reg lock_period;
+reg pll_locked_tm, unlock_recover;
+reg clkin_stopped_p, clkin_stopped_n;
+reg clkfb_stopped_p, clkfb_stopped_n;
+wire clkin_stopped, clkfb_stopped;
+reg clkpll_jitter_unlock;
+integer clkstop_cnt_p, clkstop_cnt_n, clkfbstop_cnt_p, clkfbstop_cnt_n;
+integer  clkin_jit, REF_CLK_JITTER_MAX_tmp;
+
+wire REL, DWE, DEN, DCLK, rel_o_mux_clk_tmp, clka1_in, clkb1_in;
+wire init_trig, clkpll_tmp, clkpll, clk0in, clk1in, clk2in, clk3in, clk4in, clk5in;
+wire clkfbm1in, clkfbm1ps_en;
+
+
+reg clkout0_out;
+reg clkout1_out;
+reg clkout2_out;
+reg clkout3_out;
+reg clkout4_out;
+reg clkout5_out;
+
+reg clka1_out, clkb1_out, clka1d2_out, clka1d4_out, clka1d8_out;
+reg clkdiv_rel_rst, qrel_o_reg1, qrel_o_reg2, qrel_o_reg3, rel_o_mux_sel;
+reg pmcd_mode;
+reg chk_ok;
+
+wire rel_rst_o, rel_o_mux_clk;
+wire clk0ps_en, clk1ps_en, clk2ps_en, clk3ps_en, clk4ps_en, clk5ps_en;
+
+reg [7:0] clkout_mux;
+reg [2:0] clk0pm_sel, clk1pm_sel, clk2pm_sel, clk3pm_sel, clk4pm_sel, clk5pm_sel;
+reg [2:0] clkfbm1pm_sel;
+reg clk0_edge, clk1_edge, clk2_edge, clk3_edge, clk4_edge, clk5_edge;
+reg clkfbm1_edge, clkind_edge;
+reg clk0_nocnt, clk1_nocnt, clk2_nocnt, clk3_nocnt, clk4_nocnt, clk5_nocnt;
+reg clkfbm1_nocnt, clkind_nocnt;
+reg clkind_edget, clkind_nocntt; 
+reg [5:0] clk0_dly_cnt, clkout0_dly;
+reg [5:0] clk1_dly_cnt, clkout1_dly;
+reg [5:0] clk2_dly_cnt, clkout2_dly;
+reg [5:0] clk3_dly_cnt, clkout3_dly;
+reg [5:0] clk4_dly_cnt, clkout4_dly;
+reg [5:0] clk5_dly_cnt, clkout5_dly;
+reg [6:0] clk0_ht, clk0_lt;
+reg [6:0] clk1_ht, clk1_lt;
+reg [6:0] clk2_ht, clk2_lt;
+reg [6:0] clk3_ht, clk3_lt;
+reg [6:0] clk4_ht, clk4_lt;
+reg [6:0] clk5_ht, clk5_lt;
+reg [5:0] clkfbm1_dly_cnt, clkfbm1_dly;
+reg [6:0] clkfbm1_ht, clkfbm1_lt;
+reg [7:0] clkind_ht, clkind_lt;
+reg [7:0] clkind_htt, clkind_ltt;
+reg [7:0] clk0_ht1, clk0_cnt, clk0_div, clk0_div1;
+reg [7:0] clk1_ht1, clk1_cnt, clk1_div, clk1_div1;
+reg [7:0] clk2_ht1, clk2_cnt, clk2_div, clk2_div1;
+reg [7:0] clk3_ht1, clk3_cnt, clk3_div, clk3_div1;
+reg [7:0] clk4_ht1, clk4_cnt, clk4_div, clk4_div1;
+reg [7:0] clk5_ht1, clk5_cnt, clk5_div, clk5_div1;
+reg [7:0] clkfbm1_ht1, clkfbm1_cnt, clkfbm1_div, clkfbm1_div1;
+reg [7:0]  clkind_div;
+reg [3:0] pll_cp, pll_res;
+reg [1:0] pll_lfhf;
+reg [1:0] pll_cpres = 2'b01;
+
+reg notifier;
+wire [15:0] do_out, di_in;
+wire clkin1_in, clkin2_in, clkfb_in, clkinsel_in, dwe_in, den_in, dclk_in;
+wire [4:0] daddr_in;
+wire rel_in, gsr_in, rst_input;
+
+      assign #100 LOCKED = locked_out;
+      assign #100 DRDY = drdy_out;
+      assign #100 DO = do_out;
+      assign clkin1_in = CLKIN1;
+      assign clkin2_in = CLKIN2;
+      assign clkfb_in = CLKFBIN;
+      assign clkinsel_in = CLKINSEL;
+      assign rst_input = RST;
+      assign daddr_in = DADDR;
+      assign di_in = DI;
+      assign dwe_in = DWE;
+      assign den_in = DEN;
+      assign dclk_in = DCLK;
+      assign rel_in = REL;
+
+
+
+initial begin
+    #1;
+    if ($realtime == 0) begin
+	$display ("Simulator Resolution Error : Simulator resolution is set to a value greater than 1 ps.");
+	$display ("In order to simulate the PLL_ADV, the simulator resolution must be set to 1ps or smaller.");
+	$finish;
+    end
+end
+
+initial begin
+
+        case (COMPENSATION)
+                "SYSTEM_SYNCHRONOUS" : ;
+                "SOURCE_SYNCHRONOUS" : ;
+                "INTERNAL" : ;
+                "EXTERNAL" : ;
+                "DCM2PLL" : ;
+                "PLL2DCM" : ;
+                default : begin
+                        $display("Attribute Syntax Error : The Attribute COMPENSATION on PLL_ADV instance %m is set to %s.  Legal values for this attribute are SYSTEM_SYNCHRONOUS, SOURCE_SYNCHRONOUS, INTERNAL, EXTERNAL, DCM2PLL or PLL2DCM.", COMPENSATION);
+                        $finish;
+                end
+        endcase
+
+        case (BANDWIDTH)
+                "HIGH" : ;
+                "LOW" : ;
+                "OPTIMIZED" : ;
+                default : begin
+                        $display("Attribute Syntax Error : The Attribute BANDWIDTH on PLL_ADV instance %m is set to %s.  Legal values for this attribute are HIGH, LOW or OPTIMIZED.", BANDWIDTH);
+                        $finish;
+                end
+        endcase
+
+        case (CLKOUT0_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                default : begin
+                        $display("Attribute Syntax Error : The Attribute CLKOUT0_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC.", CLKOUT0_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+        case (CLKOUT1_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                 default : begin
+                         $display("Attribute Syntax Error : The Attribute CLKOUT1_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC .", CLKOUT1_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+        case (CLKOUT2_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                 default : begin
+                         $display("Attribute Syntax Error : The Attribute CLKOUT2_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC.", CLKOUT2_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+        case (CLKOUT3_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                 default : begin
+                         $display("Attribute Syntax Error : The Attribute CLKOUT3_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC.", CLKOUT3_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+        case (CLKOUT4_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                 default : begin
+                         $display("Attribute Syntax Error : The Attribute CLKOUT4_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC.", CLKOUT4_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+        case (CLKOUT5_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                 default : begin
+                         $display("Attribute Syntax Error : The Attribute CLKOUT5_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC.", CLKOUT5_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+        case (CLKFBOUT_DESKEW_ADJUST)
+                "NONE" : ; 
+                "PPC" : ;
+                 default : begin
+                         $display("Attribute Syntax Error : The Attribute CLKFBOUT_DESKEW_ADJUST on PLL_ADV instance %m is set to %s.  Legal values for this attribute are NONE or PPC.", CLKFBOUT_DESKEW_ADJUST);
+                        $finish;
+                end
+        endcase
+
+
+        case (PLL_PMCD_MODE)
+             "TRUE" : pmcd_mode = 1'b1;
+             "FALSE" : pmcd_mode = 1'b0;
+                default : begin
+                        $display("Attribute Syntax Error : The Attribute PLL_PMCD_MODE on PLL_ADV instance %m is set to %s.  Legal values for this attribute are FALSE or TRUE.", PLL_PMCD_MODE);
+                        $finish;
+                end
+        endcase
+
+        tmp_string = "CLKOUT0_DIVIDE"; 
+        chk_ok = para_int_pmcd_chk(CLKOUT0_DIVIDE, tmp_string, 1, 128, pmcd_mode, 8);
+        tmp_string = "CLKOUT0_PHASE";
+        chk_ok = para_real_pmcd_chk(CLKOUT0_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0);
+        tmp_string = "CLKOUT0_DUTY_CYCLE";
+        chk_ok = para_real_pmcd_chk(CLKOUT0_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5);
+
+        tmp_string = "CLKOUT1_DIVIDE";
+        chk_ok = para_int_pmcd_chk(CLKOUT1_DIVIDE, tmp_string, 1, 128, pmcd_mode, 4);
+        tmp_string = "CLKOUT1_PHASE";
+        chk_ok = para_real_pmcd_chk(CLKOUT1_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0);
+        tmp_string = "CLKOUT1_DUTY_CYCLE";
+        chk_ok = para_real_pmcd_chk(CLKOUT1_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5);
+
+        tmp_string = "CLKOUT2_DIVIDE";
+        chk_ok = para_int_pmcd_chk(CLKOUT2_DIVIDE, tmp_string, 1, 128, pmcd_mode, 2);
+        tmp_string = "CLKOUT2_PHASE";
+        chk_ok = para_real_pmcd_chk(CLKOUT2_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0);
+        tmp_string = "CLKOUT2_DUTY_CYCLE";
+        chk_ok = para_real_pmcd_chk(CLKOUT2_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5);
+
+        tmp_string = "CLKOUT3_DIVIDE";
+        chk_ok = para_int_pmcd_chk(CLKOUT3_DIVIDE, tmp_string, 1, 128, pmcd_mode, 1);
+        tmp_string = "CLKOUT3_PHASE";
+        chk_ok = para_real_pmcd_chk(CLKOUT3_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0);
+        tmp_string = "CLKOUT3_DUTY_CYCLE";
+        chk_ok = para_real_pmcd_chk(CLKOUT3_DUTY_CYCLE, tmp_string, 0.0, 1.0, pmcd_mode, 0.5);
+
+        tmp_string = "CLKOUT4_DIVIDE";
+        chk_ok = para_int_range_chk(CLKOUT4_DIVIDE, tmp_string,  1, 128);
+        tmp_string = "CLKOUT4_PHASE";
+        chk_ok = para_real_range_chk(CLKOUT4_PHASE, tmp_string,  -360.0, 360.0);
+        tmp_string = "CLKOUT4_DUTY_CYCLE";
+        chk_ok = para_real_range_chk(CLKOUT4_DUTY_CYCLE, tmp_string,  0.0, 1.0);
+
+        tmp_string = "CLKOUT5_DIVIDE";
+        chk_ok = para_int_range_chk (CLKOUT5_DIVIDE, tmp_string, 1, 128);
+        tmp_string = "CLKOUT5_PHASE";
+        chk_ok = para_real_range_chk(CLKOUT5_PHASE, tmp_string, -360.0, 360.0);
+        tmp_string = "CLKOUT5_DUTY_CYCLE";
+        chk_ok = para_real_range_chk (CLKOUT5_DUTY_CYCLE, tmp_string,  0.0, 1.0);
+
+        tmp_string = "CLKFBOUT_MULT";
+        chk_ok = para_int_pmcd_chk(CLKFBOUT_MULT, tmp_string, 1, 74, pmcd_mode, 1);
+        tmp_string = "CLKFBOUT_PHASE";
+        chk_ok = para_real_pmcd_chk(CLKFBOUT_PHASE, tmp_string, -360.0, 360.0, pmcd_mode, 0.0);
+        tmp_string = "DIVCLK_DIVIDE";
+        chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, 1, 52);
+
+        tmp_string = "REF_JITTER";
+        chk_ok = para_real_range_chk (REF_JITTER, tmp_string, 0.0, 0.999);
+        if (((CLKIN1_PERIOD < 1.0) || (CLKIN1_PERIOD > 52.630)) && (pmcd_mode == 0)) begin
+            $display("Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630.");
+        end 
+
+          if (((CLKIN2_PERIOD < 1.0) || (CLKIN2_PERIOD > 52.630)) && (pmcd_mode == 0)) begin
+            $display("Attribute Syntax Error : CLKIN1_PERIOD is not in range 1.0 ... 52.630.");
+         end 
+
+
+        case (RESET_ON_LOSS_OF_LOCK)
+                "FALSE" : rst_on_loss = 1'b0;
+//                "TRUE" : if (pmcd_mode) rst_on_loss = 1'b0; else rst_on_loss = 1'b1;
+                default : begin
+                        $display("Attribute Syntax Error : The Attribute RESET_ON_LOSS_OF_LOCK on PLL_ADV instance %m is set to %s.  This attribute must always be set to FALSE for X_PLL_ADV to function correctly. Please correct the setting for the attribute and re-run the simulation.", RESET_ON_LOSS_OF_LOCK);
+                        $finish;
+                end
+        endcase
+
+  case (CLKFBOUT_MULT)
+ 1  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1101; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b0101; pll_res = 4'b1111; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0101; pll_res = 4'b1111; pll_lfhf = 2'b11; end
+ 2  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1111; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1111; pll_lfhf = 2'b11; end
+ 3  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0111; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0110; pll_res = 4'b0101; pll_lfhf = 2'b11; end
+ 4  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1101; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b1001; pll_lfhf = 2'b11; end
+ 5  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b0101; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1001; pll_lfhf = 2'b11; end
+ 6  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0101; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0001; pll_lfhf = 2'b11; end
+ 7  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1001; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0001; pll_lfhf = 2'b11; end
+ 8  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1110; pll_lfhf = 2'b11; end
+ 9  : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0001; pll_lfhf = 2'b11; end
+ 10 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0001; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0001; pll_lfhf = 2'b11; end
+ 11 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0001; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ 12 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ 13 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ 14 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b0110; pll_lfhf = 2'b11; end
+ 15 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH === "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ 16 : if (BANDWIDTH === "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ 17 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ 18 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ 19 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ 20 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 21 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 22 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 23 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 24 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1101; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ 25 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 26 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 27 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1111; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ 28 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ 29 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ 30 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0001; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1110; pll_res = 4'b1100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ 31 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ 32 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b1100; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ 33 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b1111; pll_res = 4'b1010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 34 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 35 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 36 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0111; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 37 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0110; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 38 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0110; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 39 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 40 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 41 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 42 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 43 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 44 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0100; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 45 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 46 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 47 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0101; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 48 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0101; pll_res = 4'b0010; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 49 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 50 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 51 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 52 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 53 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 54 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 55 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 56 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0011; pll_res = 4'b0100; pll_lfhf = 2'b11; end
+ 57 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 58 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 59 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 60 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 61 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 62 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 63 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ 64 : if (BANDWIDTH == "LOW") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "HIGH") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+ else if (BANDWIDTH == "OPTIMIZED") begin pll_cp = 4'b0010; pll_res = 4'b1000; pll_lfhf = 2'b11; end
+  endcase
+
+
+   tmp_string = "DIVCLK_DIVIDE";
+   chk_ok = para_int_range_chk (DIVCLK_DIVIDE, tmp_string, D_MIN, D_MAX);
+
+   tmp_string = "CLKFBOUT_MULT";
+   chk_ok = para_int_range_chk (CLKFBOUT_MULT, tmp_string, M_MIN, M_MAX);
+
+   tmp_string = "CLKOUT0_DUTY_CYCLE";
+   chk_ok = clkout_duty_chk (CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE, tmp_string);
+   tmp_string = "CLKOUT1_DUTY_CYCLE";
+   chk_ok = clkout_duty_chk (CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE, tmp_string);
+   tmp_string = "CLKOUT2_DUTY_CYCLE";
+   chk_ok = clkout_duty_chk (CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE, tmp_string);
+   tmp_string = "CLKOUT3_DUTY_CYCLE";
+   chk_ok = clkout_duty_chk (CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE, tmp_string);
+   tmp_string = "CLKOUT4_DUTY_CYCLE";
+   chk_ok = clkout_duty_chk (CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE, tmp_string);
+   tmp_string = "CLKOUT5_DUTY_CYCLE";
+   chk_ok = clkout_duty_chk (CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE, tmp_string);
+
+   period_vco_max = 1000000 / VCOCLK_FREQ_MIN;
+   period_vco_min = 1000000 / VCOCLK_FREQ_MAX;
+   period_vco_target = 1000000 / VCOCLK_FREQ_TARGET;
+   period_vco_target_half = period_vco_target / 2;
+   fb_delay_max = MAX_FEEDBACK_DELAY * MAX_FEEDBACK_DELAY_SCALE;
+   md_product = CLKFBOUT_MULT * DIVCLK_DIVIDE;
+   md_product_dbl = md_product * 2;
+   clkout_en_time = `PLL_LOCK_TIME + 2; 
+//   locked_en_time = md_product_dbl +  clkout_en_time +2;  // for DCM 3 cycle reset requirement
+   locked_en_time = md_product +  clkout_en_time + 2;  // for DCM 3 cycle reset requirement
+   lock_cnt_max = locked_en_time + 6;
+   clkfb_stop_max = 3;
+   clkin_stop_max = DIVCLK_DIVIDE + 1;
+   REF_CLK_JITTER_MAX_tmp = REF_CLK_JITTER_MAX;
+
+   clk_out_para_cal (clk0_ht, clk0_lt, clk0_nocnt, clk0_edge, CLKOUT0_DIVIDE, CLKOUT0_DUTY_CYCLE);
+   clk_out_para_cal (clk1_ht, clk1_lt, clk1_nocnt, clk1_edge, CLKOUT1_DIVIDE, CLKOUT1_DUTY_CYCLE);
+   clk_out_para_cal (clk2_ht, clk2_lt, clk2_nocnt, clk2_edge, CLKOUT2_DIVIDE, CLKOUT2_DUTY_CYCLE);
+   clk_out_para_cal (clk3_ht, clk3_lt, clk3_nocnt, clk3_edge, CLKOUT3_DIVIDE, CLKOUT3_DUTY_CYCLE);
+   clk_out_para_cal (clk4_ht, clk4_lt, clk4_nocnt, clk4_edge, CLKOUT4_DIVIDE, CLKOUT4_DUTY_CYCLE);
+   clk_out_para_cal (clk5_ht, clk5_lt, clk5_nocnt, clk5_edge, CLKOUT5_DIVIDE, CLKOUT5_DUTY_CYCLE);
+   clk_out_para_cal (clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge, CLKFBOUT_MULT, 0.50);
+   clk_out_para_cal (clkind_ht, clkind_lt, clkind_nocnt, clkind_edge, DIVCLK_DIVIDE, 0.50);
+   tmp_string = "CLKOUT0_PHASE";
+   clkout_dly_cal (clkout0_dly, clk0pm_sel, CLKOUT0_DIVIDE, CLKOUT0_PHASE, tmp_string);
+   tmp_string = "CLKOUT1_PHASE";
+   clkout_dly_cal (clkout1_dly, clk1pm_sel, CLKOUT1_DIVIDE, CLKOUT1_PHASE, tmp_string);
+   tmp_string = "CLKOUT2_PHASE";
+   clkout_dly_cal (clkout2_dly, clk2pm_sel, CLKOUT2_DIVIDE, CLKOUT2_PHASE, tmp_string);
+   tmp_string = "CLKOUT3_PHASE";
+   clkout_dly_cal (clkout3_dly, clk3pm_sel, CLKOUT3_DIVIDE, CLKOUT3_PHASE, tmp_string);
+   tmp_string = "CLKOUT4_PHASE";
+   clkout_dly_cal (clkout4_dly, clk4pm_sel, CLKOUT4_DIVIDE, CLKOUT4_PHASE, tmp_string);
+   tmp_string = "CLKOUT5_PHASE";
+   clkout_dly_cal (clkout5_dly, clk5pm_sel, CLKOUT5_DIVIDE, CLKOUT5_PHASE, tmp_string);
+   tmp_string = "CLKFBOUT_PHASE";
+   clkout_dly_cal (clkfbm1_dly, clkfbm1pm_sel, CLKFBOUT_MULT, CLKFBOUT_PHASE, tmp_string);
+        
+   clkind_div = DIVCLK_DIVIDE;
+
+   dr_sram[5'b11100] = {8'bx, clk0_edge, clk0_nocnt, clkout0_dly[5:0]};
+   dr_sram[5'b11011] = {clk0pm_sel[2:0], 1'b1, clk0_ht[5:0], clk0_lt[5:0]};
+   dr_sram[5'b11010] = {8'bx, clk1_edge, clk1_nocnt, clkout1_dly[5:0]};
+   dr_sram[5'b11001] = {clk1pm_sel[2:0], 1'b1, clk1_ht[5:0], clk1_lt[5:0]};
+   dr_sram[5'b10111] = {8'bx, clk2_edge, clk2_nocnt, clkout2_dly[5:0]};
+   dr_sram[5'b10110] = {clk2pm_sel[2:0], 1'b1, clk2_ht[5:0], clk2_lt[5:0]};
+   dr_sram[5'b10101] = {8'bx, clk3_edge, clk3_nocnt, clkout3_dly[5:0]};
+   dr_sram[5'b10100] = {clk3pm_sel[2:0], 1'b1, clk3_ht[5:0], clk3_lt[5:0]};
+   dr_sram[5'b10011] = {8'bx, clk4_edge, clk4_nocnt, clkout4_dly[5:0]};
+   dr_sram[5'b10010] = {clk4pm_sel[2:0], 1'b1, clk4_ht[5:0], clk4_lt[5:0]};
+   dr_sram[5'b01111] = {8'bx, clk5_edge, clk5_nocnt, clkout5_dly[5:0]};
+   dr_sram[5'b01110] = {clk5pm_sel[2:0], 1'b1, clk5_ht[5:0], clk5_lt[5:0]};
+   dr_sram[5'b01101] = {8'bx, clkfbm1_edge, clkfbm1_nocnt, clkfbm1_dly[5:0]};
+   dr_sram[5'b01100] = {clkfbm1pm_sel[2:0], 1'b1, clkfbm1_ht[5:0], clkfbm1_lt[5:0]};
+   dr_sram[5'b00110] = {2'bx, clkind_edge, clkind_nocnt, clkind_ht[5:0], clkind_lt[5:0]};
+   dr_sram[5'b00001] = {8'bx, pll_lfhf, pll_cpres, pll_cp};
+   dr_sram[5'b00000] = {6'bx, pll_res, 6'bx};
+
+
+// **** PMCD *******
+
+//*** Clocks MUX
+
+        case (RST_DEASSERT_CLK)
+             "CLKIN1" : rel_o_mux_sel = 1'b1;
+             "CLKFBIN" : rel_o_mux_sel = 1'b0;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute RST_DEASSERT_CLK on PLL_ADV instance %m is set to %s.  Legal values for this attribute are CLKIN1 and CLKFBIN.", RST_DEASSERT_CLK);
+                          $finish;
+                      end
+        endcase
+
+//*** CLKDIV_RST
+        case (EN_REL)
+              "FALSE" : clkdiv_rel_rst = 1'b0;
+              "TRUE" : clkdiv_rel_rst = 1'b1;
+            default : begin
+                          $display("Attribute Syntax Error : The attribute EN_REL on PLL_ADV instance %m is set to %s.  Legal values for this attribute are TRUE or FALSE.", EN_REL);
+                          $finish;
+                      end
+        endcase
+
+
+end
+
+initial begin
+  rst_in1 = 0;
+  rst_unlock = 0;
+  clkin_period[0] = 0;
+  clkin_period[1] = 0;
+  clkin_period[2] = 0;
+  clkin_period[3] = 0;
+  clkin_period[4] = 0;
+  period_avg = 0;
+  period_fb = 0;
+  fb_delay = 0;
+  clkfbm1_div = 1;
+  clkfbm1_div1 = 0;
+  clkvco_delay = 0;
+  fbm1_comp_delay = 0;
+  clkfbm1pm_rl = 0;
+  period_vco = 0;
+  period_vco1 = 0;
+  period_vco2 = 0;
+  period_vco3 = 0;
+  period_vco4 = 0;
+  period_vco5 = 0;
+  period_vco6 = 0;
+  period_vco7 = 0;
+  period_vco_half = 0;
+  fb_delay_found = 0;
+  fb_delay_found_tmp = 0;
+  clkin_edge = 0;
+  delay_edge = 0;
+  clkvco_free = 0;
+  clkvco_lk = 0;
+  fbclk_tmp = 0;
+  clkfb_tst = 0;
+  clkout_cnt = 0;
+  clkout_en = 0;
+  clkout_en0 = 0;
+  clkout_en0_tmp = 0;
+  clkout_en1 = 0;
+  pll_locked_tmp1  = 0;
+  pll_locked_tmp2  = 0;
+  pll_locked_tm = 0;
+  pll_locked_delay = 0;
+  clkout_mux = 3'b0;
+  unlock_recover = 0;
+  clkstop_cnt_p = 0;
+  clkstop_cnt_n = 0;
+  clkpll_jitter_unlock = 0;
+  clkin_jit = 0;
+  clkin_cnt = 0;
+  clkin_lock_cnt = 0;
+  clkin_stopped_p = 0;
+  clkin_stopped_n = 0;
+  clkfb_stopped_p = 0;
+  clkfb_stopped_n = 0;
+  clkpll_dly = 0;
+  clkfbin_dly = 0;
+  clkfbstop_cnt_p = 0;
+  clkfbstop_cnt_n = 0;
+  lock_period = 0;
+  rst_edge = 0;
+  rst_ht = 0;
+  drdy_out = 0;
+  drp_lock = 0;
+  clkout0_out = 0;
+  clkout1_out = 0;
+  clkout2_out = 0;
+  clkout3_out = 0;
+  clkout4_out = 0;
+  clkout5_out = 0;
+  clka1_out = 1'b0;
+  clkb1_out = 1'b0;         
+  clka1d2_out = 1'b0;
+  clka1d4_out = 1'b0;
+  clka1d8_out = 1'b0;
+  qrel_o_reg1 = 1'b0;
+  qrel_o_reg2 = 1'b0;
+  qrel_o_reg3 = 1'b0;
+  clk0_dly_cnt = 6'b0;
+  clk1_dly_cnt = 6'b0;
+  clk2_dly_cnt = 6'b0;
+  clk3_dly_cnt = 6'b0;
+  clk4_dly_cnt = 6'b0;
+  clk5_dly_cnt = 6'b0;
+  clkfbm1_dly_cnt = 6'b0;
+  clk0_cnt = 8'b0;
+  clk1_cnt = 8'b0;
+  clk2_cnt = 8'b0;
+  clk3_cnt = 8'b0;
+  clk4_cnt = 8'b0;
+  clk5_cnt = 8'b0;
+  clkfbm1_cnt = 8'b0;
+  clk0_out = 0;
+  clk1_out = 0;
+  clk2_out = 0;
+  clk3_out = 0;
+  clk4_out = 0;
+  clk5_out = 0;
+  clkfb_out = 0;
+  clkfbm1_out = 0;
+end
+
+// PMCD function
+
+//*** asyn RST
+    always @(orig_rst_in) 
+        if (orig_rst_in == 1'b1) begin
+            assign qrel_o_reg1 = 1'b1;
+            assign qrel_o_reg2 = 1'b1;
+            assign qrel_o_reg3 = 1'b1;
+        end
+        else if (orig_rst_in == 1'b0) begin
+            deassign qrel_o_reg1;
+            deassign qrel_o_reg2;
+            deassign qrel_o_reg3;
+        end
+
+//*** Clocks MUX
+
+    assign rel_o_mux_clk_tmp = rel_o_mux_sel ? clkin1_in : clkfb_in;
+    assign rel_o_mux_clk = (pmcd_mode) ? rel_o_mux_clk_tmp : 0;
+    assign clka1_in = (pmcd_mode) ? clkin1_in : 0;
+    assign clkb1_in = (pmcd_mode) ? clkfb_in : 0;
+
+
+//*** Rel and Rst
+    always @(posedge rel_o_mux_clk) 
+        qrel_o_reg1 <= 1'b0;
+
+    always @(negedge rel_o_mux_clk) 
+        qrel_o_reg2 <= qrel_o_reg1;
+
+    always @(posedge rel_in) 
+        qrel_o_reg3 <= 1'b0;
+
+    assign rel_rst_o = clkdiv_rel_rst ? (qrel_o_reg3 || qrel_o_reg1) : qrel_o_reg1;
+
+//*** CLKA
+    always @(clka1_in or qrel_o_reg2)
+        if (qrel_o_reg2 == 1'b1)
+            clka1_out <= 1'b0;
+        else if (qrel_o_reg2 == 1'b0)
+            clka1_out <= clka1_in;
+
+//*** CLKB   
+    always @(clkb1_in or qrel_o_reg2)
+        if (qrel_o_reg2 == 1'b1)
+            clkb1_out <= 1'b0;
+        else if (qrel_o_reg2 == 1'b0)
+            clkb1_out <= clkb1_in;
+
+
+//*** Clock divider
+    always @(posedge clka1_in or posedge rel_rst_o)
+        if (rel_rst_o == 1'b1)
+            clka1d2_out <= 1'b0;
+        else if (rel_rst_o == 1'b0)
+            clka1d2_out <= ~clka1d2_out;
+
+    always @(posedge clka1d2_out or posedge rel_rst_o)
+        if (rel_rst_o == 1'b1)
+            clka1d4_out <= 1'b0;
+        else if (rel_rst_o == 1'b0)
+            clka1d4_out <= ~clka1d4_out;
+
+    always @(posedge clka1d4_out or posedge rel_rst_o)
+        if (rel_rst_o == 1'b1)
+            clka1d8_out <= 1'b0;
+        else if (rel_rst_o == 1'b0)
+            clka1d8_out <= ~clka1d8_out;
+
+   assign CLKOUT5 = (pmcd_mode) ? 0 : clkout5_out;
+   assign CLKOUT4 = (pmcd_mode) ? 0 : clkout4_out;
+   assign CLKOUT3 = (pmcd_mode) ? clka1_out : clkout3_out;
+   assign CLKOUT2 = (pmcd_mode) ? clka1d2_out : clkout2_out;
+   assign CLKOUT1 = (pmcd_mode) ? clka1d4_out : clkout1_out;
+   assign CLKOUT0 = (pmcd_mode) ? clka1d8_out : clkout0_out;
+   assign CLKFBOUT = (pmcd_mode) ? clkb1_out : clkfb_out;
+   assign CLKOUTDCM5 = (pmcd_mode) ? 0 : clkout5_out;
+   assign CLKOUTDCM4 = (pmcd_mode) ? 0 : clkout4_out;
+   assign CLKOUTDCM3 = (pmcd_mode) ? clka1_out : clkout3_out;
+   assign CLKOUTDCM2 = (pmcd_mode) ? clka1d2_out : clkout2_out;
+   assign CLKOUTDCM1 = (pmcd_mode) ? clka1d4_out : clkout1_out;
+   assign CLKOUTDCM0 = (pmcd_mode) ? clka1d8_out : clkout0_out;
+   assign CLKFBDCM = (pmcd_mode) ? clkb1_out : clkfb_out;
+
+// PLL  function
+
+always @(clkinsel_in ) 
+ if (pmcd_mode != 1) begin
+  if ($time >1 && rst_in != 1'b1) begin
+      $display("Input Error : PLL input clock can only be switched when RST=1.  CLKINSEL on instance %m at time %t changed when RST low, should change at RST high.", $time);
+      $finish;
+  end
+  if (clkinsel_in ==1) begin
+    if (CLKIN1_PERIOD > (1000.0 /CLKIN_FREQ_MIN) || CLKIN1_PERIOD < (1000.0 / CLKIN_FREQ_MAX)) begin
+     $display (" Attribute Syntax Error : The attribute CLKIN1_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN1_PERIOD, 1000.0/CLKIN_FREQ_MAX, 1000.0/CLKIN_FREQ_MIN);
+     $finish;
+   end
+  end 
+  else if (clkinsel_in ==0) begin
+    if (CLKIN2_PERIOD > (1000.0 /CLKIN_FREQ_MIN) || CLKIN2_PERIOD < (1000.0 / CLKIN_FREQ_MAX)) begin
+     $display (" Attribute Syntax Error : The attribute CLKIN2_PERIOD is set to %f ns and out the allowed range %f ns to %f ns.", CLKIN2_PERIOD, 1000.0/CLKIN_FREQ_MAX, 1000.0/CLKIN_FREQ_MIN);
+     $finish;
+   end
+  end
+
+  period_clkin =  (clkinsel_in) ? CLKIN1_PERIOD : CLKIN2_PERIOD;
+  clkvco_freq_init_chk =  1000.0 * CLKFBOUT_MULT / (period_clkin  * DIVCLK_DIVIDE);
+
+   if (clkvco_freq_init_chk > VCOCLK_FREQ_MAX || clkvco_freq_init_chk < VCOCLK_FREQ_MIN) begin
+     $display (" Attribute Syntax Error : The calculation of VCO frequency=%f Mhz. This exceeds the permitted VCO frequency range of %f Mhz to %f Mhz. The VCO frequency is calculated with formula: VCO frequency =  CLKFBOUT_MULT / (DIVCLK_DIVIDE * CLKIN_PERIOD). Please adjust the attributes to the permitted VCO frequency range.", clkvco_freq_init_chk, VCOCLK_FREQ_MIN, VCOCLK_FREQ_MAX);
+     $finish;
+   end
+end
+
+ assign  init_trig = 1;
+
+   
+  assign clkpll_tmp = (clkinsel_in) ? clkin1_in : clkin2_in;
+  assign clkpll = (pmcd_mode) ? 0 : clkpll_tmp;
+
+  assign orig_rst_in =  rst_input; 
+
+always @(posedge clkpll or posedge orig_rst_in)
+  if (orig_rst_in)
+     rst_in1 <= 1;
+  else
+     rst_in1 <= orig_rst_in;
+
+  assign rst_in = (rst_in1 || rst_unlock);
+  
+  always @(posedge pll_unlock)
+  if (rst_on_loss ) begin
+     rst_unlock <= 1'b1;
+     rst_unlock <= #10000 1'b0;
+  end
+
+always @(rst_input )
+  if (rst_input==1)
+     rst_edge = $time;
+  else if (rst_input==0 && rst_edge > 1) begin
+     rst_ht = $time - rst_edge;
+     if (rst_ht < 10000) 
+        $display("Input Error : RST on instance %m at time %t must be asserted at least for 10 ns.", $time);
+  end 
+
+//
+// DRP port read and write
+//
+
+  assign do_out = dr_sram[daddr_lat];
+
+always @(posedge dclk_in or posedge gsr_in)
+  if (gsr_in == 1) begin
+       drp_lock <= 0;
+    end
+  else begin
+    if (den_in == 1) begin
+        valid_daddr = addr_is_valid(daddr_in);
+        if (drp_lock == 1) begin
+          $display(" Warning : DEN is high at PLL_ADV instance %m at time %t. Need wait for DRDY signal before next read/write operation through DRP. ", $time);
+          $finish;
+        end
+        else begin
+          drp_lock <= 1;
+          daddr_lat <= daddr_in;
+        end
+ 
+        if (valid_daddr && ( daddr_in == 5'b00110 || daddr_in == 5'b00001 || daddr_in == 5'b00000 ||
+                         (daddr_in >= 5'b01100 && daddr_in <= 5'b11100 && daddr_in != 5'b10000 && 
+                                  daddr_in != 5'b10001 && daddr_in != 5'b11000 ))) begin
+              end
+        else begin
+                  $display(" Warning : Address DADDR=%b is unsupported at PLL_ADV instance %m at time %t.  ",  DADDR, $time);
+        end
+
+        if (dwe_in == 1) begin          // write process
+          if (rst_input == 1) begin
+             if (valid_daddr && ( daddr_in == 5'b00110 || daddr_in == 5'b00001 || daddr_in == 5'b00000 ||
+                                  (daddr_in >= 5'b01100 && daddr_in <= 5'b11100 && daddr_in != 5'b10000 && 
+                                  daddr_in != 5'b10001 && daddr_in != 5'b11000 ))) begin
+                  dr_sram[daddr_in] <= di_in;
+              end
+
+             if (daddr_in == 5'b11100) 
+                 clkout_delay_para_drp (clkout0_dly, clk0_nocnt, clk0_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b11011)
+                 clkout_hl_para_drp (clk0_lt, clk0_ht, clk0pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b11010) 
+                 clkout_delay_para_drp (clkout1_dly, clk1_nocnt, clk1_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b11001)
+                 clkout_hl_para_drp (clk1_lt, clk1_ht, clk1pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b10111) 
+                 clkout_delay_para_drp (clkout2_dly, clk2_nocnt, clk2_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b10110)
+                 clkout_hl_para_drp (clk2_lt, clk2_ht, clk2pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b10101) 
+                 clkout_delay_para_drp (clkout3_dly, clk3_nocnt, clk3_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b10100)
+                 clkout_hl_para_drp (clk3_lt, clk3_ht, clk3pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b10011) 
+                 clkout_delay_para_drp (clkout4_dly, clk4_nocnt, clk4_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b10010)
+                 clkout_hl_para_drp (clk4_lt, clk4_ht, clk4pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b01111) 
+                 clkout_delay_para_drp (clkout5_dly, clk5_nocnt, clk5_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b01110)
+                 clkout_hl_para_drp (clk5_lt, clk5_ht, clk5pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b01101) 
+                 clkout_delay_para_drp (clkfbm1_dly, clkfbm1_nocnt, clkfbm1_edge, di_in, daddr_in);
+
+             if (daddr_in == 5'b01100)
+                 clkout_hl_para_drp (clkfbm1_lt, clkfbm1_ht, clkfbm1pm_sel, di_in, daddr_in);
+
+             if (daddr_in == 5'b00110) begin
+                 clkind_lt <= di_in[5:0];
+                 clkind_ht <= di_in[11:6];
+                 if ( di_in[5:0] == 6'b0 && di_in[11:6] == 6'b0 )
+                     clkind_div <= 8'b10000000;
+                 else if (di_in[5:0] == 6'b0 && di_in[11:6] != 6'b0 )
+                     clkind_div <= 64 + di_in[11:6];
+                 else if (di_in[5:0] == 6'b0 && di_in[11:6] != 6'b0 )
+                     clkind_div <= 64 + di_in[5:0];
+                 else
+                      clkind_div <= di_in[5:0] + di_in[11:6];
+                 clkind_nocnt <= di_in[12];
+                 clkind_edge <= di_in[13];
+             end
+
+          end
+          else begin
+                  $display(" Error : RST is low at PLL_ADV instance %m at time %t. RST need to be high when change X_PLL_ADV paramters through DRP. ", $time);
+          end
+
+        end //DWE
+                  
+    end  //DEN
+    if ( drp_lock == 1) begin
+          drp_lock <= 0;
+          drp_lock1 <= 1;
+    end
+    if (drp_lock1 == 1) begin
+         drp_lock1 <= 0;
+         drdy_out <= 1;
+    end 
+    if (drdy_out == 1)
+        drdy_out <= 0;
+end
+
+function addr_is_valid;
+input [6:0] daddr_funcin;
+begin
+  addr_is_valid = 1;
+  for (i=0; i<=6; i=i+1)
+    if ( daddr_funcin[i] != 0 && daddr_funcin[i] != 1)
+       addr_is_valid = 0;
+end
+endfunction
+
+
+// end process drp;
+
+
+//
+// determine clock period
+//
+
+  always @(posedge clkpll or posedge rst_in)
+   if (rst_in)
+   begin
+     clkin_period[0] <= period_vco_target;
+     clkin_period[1] <= period_vco_target;
+     clkin_period[2] <= period_vco_target;
+     clkin_period[3] <= period_vco_target;
+     clkin_period[4] <= period_vco_target;
+     clkin_jit <= 0;
+     clkin_lock_cnt <= 0;
+     pll_locked_tm <= 0;
+     lock_period <= 0;
+     pll_locked_tmp1 <= 0;
+     clkout_en0_tmp <= 0;
+     unlock_recover <= 0;
+     clkin_edge <= 0;
+   end
+   else  begin
+       clkin_edge <= $time;
+       clkin_period[4] <= clkin_period[3];
+       clkin_period[3] <= clkin_period[2];
+       clkin_period[2] <= clkin_period[1];
+       clkin_period[1] <= clkin_period[0];
+       if (clkin_edge != 0 && clkin_stopped_p == 0 && clkin_stopped_n == 0) 
+          clkin_period[0] <= $time - clkin_edge;
+  
+       if (pll_unlock == 0)
+          clkin_jit <=  $time - clkin_edge - clkin_period[0];
+       else
+          clkin_jit <= 0;
+
+      if ( (clkin_lock_cnt < lock_cnt_max) && fb_delay_found && pll_unlock == 0)
+            clkin_lock_cnt <= clkin_lock_cnt + 1;
+      else if (pll_unlock == 1 && rst_on_loss ==0 && pll_locked_tmp1 ==1 ) begin
+            clkin_lock_cnt <= locked_en_time;
+            unlock_recover <= 1;
+      end
+
+      if ( clkin_lock_cnt >= `PLL_LOCK_TIME && pll_unlock == 0)
+        pll_locked_tm <= 1;
+
+      if ( clkin_lock_cnt == 6 )
+        lock_period <= 1;
+
+      if (clkin_lock_cnt >= clkout_en_time) begin
+         clkout_en0_tmp <= 1;
+      end
+
+      if (clkin_lock_cnt >= locked_en_time)
+        pll_locked_tmp1 <= 1;
+
+      if (unlock_recover ==1 && clkin_lock_cnt  >= lock_cnt_max)
+        unlock_recover <= 0;
+  end
+
+   always @(clkout_en0_tmp)
+   if (clkout_en0_tmp==0)
+        clkout_en0 = 0;
+   else
+      @(negedge clkpll)
+        clkout_en0 <= #(clkin_period[0]/2) clkout_en0_tmp;
+
+  always @(clkout_en0)
+       clkout_en <= #(clkvco_delay) clkout_en0;
+
+  always @(pll_locked_tmp1 )
+  if (pll_locked_tmp1==0)
+         pll_locked_tmp2 =  pll_locked_tmp1;
+  else begin
+         pll_locked_tmp2 <= #pll_locked_delay  pll_locked_tmp1;
+  end
+
+
+  always @(rst_in)
+  if (rst_in) begin
+     assign pll_locked_tmp2 = 0;
+     assign clkout_en0 = 0;
+     assign clkout_en = 0;
+  end
+  else begin
+    deassign pll_locked_tmp2;
+    deassign clkout_en0;
+    deassign clkout_en;
+  end
+    
+  assign locked_out = (pll_locked_tm && pll_locked_tmp2 && ~pll_unlock && !unlock_recover) ? 1 : 0;
+
+
+  always @(clkin_period[0] or clkin_period[1] or clkin_period[2] or 
+                 clkin_period[3] or clkin_period[4] or period_avg)
+    if ( clkin_period[0] != period_avg) 
+          period_avg = (clkin_period[0] + clkin_period[1] + clkin_period[2] 
+                       + clkin_period[3] + clkin_period[4])/5;
+
+  always @(period_avg or clkind_div or clkfbm1_div) begin
+   period_fb = period_avg * clkind_div;
+   period_vco = period_fb / clkfbm1_div;
+   period_vco_half = period_vco /2;
+   pll_locked_delay = period_fb * clkfbm1_div;
+   clkin_dly_t =  period_avg * (clkind_div + 1.25);
+   clkfb_dly_t = period_fb * 2.25 ;
+   period_vco1 = period_vco / 8;
+   period_vco2 = period_vco / 4;
+   period_vco3 = period_vco * 3/ 8;
+   period_vco4 = period_vco / 2;
+   period_vco5 = period_vco * 5 / 8;
+   period_vco6 = period_vco *3 / 4;
+   period_vco7 = period_vco * 7 / 8;
+   md_product = clkind_div * clkfbm1_div;
+   md_product_dbl = clkind_div * clkfbm1_div * 2;
+  end
+
+  assign clkvco_lk_rst = ( rst_in == 1  ||  pll_unlock == 1 || pll_locked_tm == 0) ? 1 : 0;
+  
+  always @(clkvco_lk_rst)
+   if (clkvco_lk_rst)
+      assign  clkvco_lk = 0;
+   else
+      deassign clkvco_lk;
+
+
+//  always @(posedge clkpll or posedge rst_in or  posedge pll_unlock) 
+//   if ( rst_in == 1  ||  pll_unlock == 1 || pll_locked_tm == 0) begin
+//        clkvco_lk <= 0;
+//   end
+//   else begin
+  always @(posedge clkpll) 
+     if (pll_locked_tm ==1) begin
+       clkvco_lk <= 1;
+        for (i1=1; i1 < md_product_dbl; i1=i1+1)
+               #(period_vco_half) clkvco_lk <= ~clkvco_lk;
+     end
+
+
+  always @(fb_delay or period_vco or clkfbm1_dly or clkfbm1pm_rl) begin
+     val_tmp = period_vco * md_product;
+     fbm1_comp_delay = period_vco *(clkfbm1_dly  + clkfbm1pm_rl );
+     dly_tmp = fb_delay + fbm1_comp_delay;
+    if (fb_delay == 0)
+        clkvco_delay = 0;
+    else if ( dly_tmp < val_tmp)
+       clkvco_delay = val_tmp - dly_tmp;
+    else
+     clkvco_delay = val_tmp - dly_tmp % val_tmp ;
+  end
+
+  always @(clkfbm1pm_sel)
+   case (clkfbm1pm_sel)
+     3'b000 : clkfbm1pm_rl = 0.0;
+     3'b001 : clkfbm1pm_rl = 0.125;
+     3'b010 : clkfbm1pm_rl = 0.25;
+     3'b011 : clkfbm1pm_rl = 0.375;
+     3'b100 : clkfbm1pm_rl = 0.50;
+     3'b101 : clkfbm1pm_rl = 0.625;
+     3'b110 : clkfbm1pm_rl = 0.75;
+     3'b111 : clkfbm1pm_rl = 0.875;
+   endcase
+
+  always @(clkvco_free )
+    if (pmcd_mode != 1 && pll_locked_tm == 0)
+      clkvco_free <= #period_vco_target_half ~clkvco_free;
+  
+  always @(clkvco_lk or clkvco_free or pll_locked_tm)
+   if ( pll_locked_tm)
+       clkvco <=  #clkvco_delay clkvco_lk;
+   else
+       clkvco <=  #clkvco_delay clkvco_free;
+
+  always @(clk0_ht or clk0_lt or clk0_nocnt or init_trig)
+   clkout_pm_cal(clk0_ht1, clk0_div, clk0_div1, clk0_ht, clk0_lt, clk0_nocnt, clk0_edge);
+
+  always @(clk1_ht or clk1_lt or clk1_nocnt or init_trig)
+   clkout_pm_cal(clk1_ht1, clk1_div, clk1_div1, clk1_ht, clk1_lt, clk1_nocnt, clk1_edge);
+
+  always @(clk2_ht or clk2_lt or clk2_nocnt or init_trig)
+   clkout_pm_cal(clk2_ht1, clk2_div, clk2_div1, clk2_ht, clk2_lt, clk2_nocnt, clk2_edge);
+
+  always @(clk3_ht or clk3_lt or clk3_nocnt or init_trig)
+   clkout_pm_cal(clk3_ht1, clk3_div, clk3_div1, clk3_ht, clk3_lt, clk3_nocnt, clk3_edge);
+
+  always @(clk4_ht or clk4_lt or clk4_nocnt or init_trig)
+   clkout_pm_cal(clk4_ht1, clk4_div, clk4_div1, clk4_ht, clk4_lt, clk4_nocnt, clk4_edge);
+
+  always @(clk5_ht or clk5_lt or clk5_nocnt or init_trig)
+   clkout_pm_cal(clk5_ht1, clk5_div, clk5_div1, clk5_ht, clk5_lt, clk5_nocnt, clk5_edge);
+
+  always @(clkfbm1_ht or clkfbm1_lt or clkfbm1_nocnt or init_trig)
+   clkout_pm_cal(clkfbm1_ht1, clkfbm1_div, clkfbm1_div1, clkfbm1_ht, clkfbm1_lt, clkfbm1_nocnt, clkfbm1_edge);
+
+  always @(rst_in)
+  if (rst_in)
+    assign clkout_mux = 8'b0;
+  else 
+    deassign clkout_mux;
+
+ always @(clkvco or clkout_en ) 
+  if (clkout_en) begin
+   clkout_mux[0] <= clkvco;
+   clkout_mux[1] <= #(period_vco1) clkvco;
+   clkout_mux[2] <= #(period_vco2) clkvco;
+   clkout_mux[3] <= #(period_vco3) clkvco;
+   clkout_mux[4] <= #(period_vco4) clkvco;
+   clkout_mux[5] <= #(period_vco5) clkvco;
+   clkout_mux[6] <= #(period_vco6) clkvco;
+   clkout_mux[7] <= #(period_vco7) clkvco;
+ end
+   
+ assign clk0in = clkout_mux[clk0pm_sel];
+ assign clk1in = clkout_mux[clk1pm_sel];
+ assign clk2in = clkout_mux[clk2pm_sel];
+ assign clk3in = clkout_mux[clk3pm_sel];
+ assign clk4in = clkout_mux[clk4pm_sel];
+ assign clk5in = clkout_mux[clk5pm_sel];
+ assign clkfbm1in = clkout_mux[clkfbm1pm_sel];
+
+ assign clk0ps_en = (clk0_dly_cnt == clkout0_dly) ? clkout_en : 0;
+ assign clk1ps_en = (clk1_dly_cnt == clkout1_dly) ? clkout_en : 0;
+ assign clk2ps_en = (clk2_dly_cnt == clkout2_dly) ? clkout_en : 0;
+ assign clk3ps_en = (clk3_dly_cnt == clkout3_dly) ? clkout_en : 0;
+ assign clk4ps_en = (clk4_dly_cnt == clkout4_dly) ? clkout_en : 0;
+ assign clk5ps_en = (clk5_dly_cnt == clkout5_dly) ? clkout_en : 0;
+ assign clkfbm1ps_en = (clkfbm1_dly_cnt == clkfbm1_dly) ? clkout_en : 0;
+
+ always  @(negedge clk0in or posedge rst_in) 
+     if (rst_in)
+        clk0_dly_cnt <= 6'b0;
+     else
+       if (clk0_dly_cnt < clkout0_dly && clkout_en ==1)
+          clk0_dly_cnt <= clk0_dly_cnt + 1;
+
+ always  @(negedge clk1in or posedge rst_in)
+     if (rst_in)
+        clk1_dly_cnt <= 6'b0;
+     else
+       if (clk1_dly_cnt < clkout1_dly && clkout_en ==1)
+          clk1_dly_cnt <= clk1_dly_cnt + 1;
+
+ always  @(negedge clk2in or posedge rst_in)
+     if (rst_in)
+        clk2_dly_cnt <= 6'b0;
+     else
+       if (clk2_dly_cnt < clkout2_dly && clkout_en ==1)
+          clk2_dly_cnt <= clk2_dly_cnt + 1;
+
+ always  @(negedge clk3in or posedge rst_in)
+     if (rst_in)
+        clk3_dly_cnt <= 6'b0;
+     else
+       if (clk3_dly_cnt < clkout3_dly && clkout_en ==1)
+          clk3_dly_cnt <= clk3_dly_cnt + 1;
+
+ always  @(negedge clk4in or posedge rst_in)
+     if (rst_in)
+        clk4_dly_cnt <= 6'b0;
+     else
+       if (clk4_dly_cnt < clkout4_dly && clkout_en ==1)
+          clk4_dly_cnt <= clk4_dly_cnt + 1;
+
+ always  @(negedge clk5in or posedge rst_in)
+     if (rst_in)
+        clk5_dly_cnt <= 6'b0;
+     else
+       if (clk5_dly_cnt < clkout5_dly && clkout_en ==1)
+          clk5_dly_cnt <= clk5_dly_cnt + 1;
+
+ always  @(negedge clkfbm1in or posedge rst_in)
+     if (rst_in)
+        clkfbm1_dly_cnt <= 6'b0;
+     else
+       if (clkfbm1_dly_cnt < clkfbm1_dly && clkout_en ==1)
+          clkfbm1_dly_cnt <= clkfbm1_dly_cnt + 1;
+
+  always @(posedge clk0in or negedge clk0in or posedge rst_in)
+     if (rst_in) begin
+        clk0_cnt <= 8'b0;
+        clk0_out <= 0;
+     end
+     else if (clk0ps_en) begin
+          if (clk0_cnt < clk0_div1)
+                clk0_cnt <= clk0_cnt + 1;
+             else
+                clk0_cnt <= 8'b0; 
+
+           if (clk0_cnt < clk0_ht1)
+               clk0_out <= 1;
+           else
+               clk0_out <= 0;
+     end
+     else begin
+        clk0_cnt <= 8'b0;
+        clk0_out <= 0;
+     end
+
+  always @(posedge clk1in or negedge clk1in or posedge rst_in)
+     if (rst_in) begin
+        clk1_cnt <= 8'b0;
+        clk1_out <= 0;
+     end
+     else if (clk1ps_en) begin
+          if (clk1_cnt < clk1_div1)
+                clk1_cnt <= clk1_cnt + 1;
+             else
+                clk1_cnt <= 8'b0;
+
+           if (clk1_cnt < clk1_ht1)
+               clk1_out <= 1;
+           else
+               clk1_out <= 0;
+     end
+     else begin
+        clk1_cnt <= 8'b0;
+        clk1_out <= 0;
+     end
+
+  always @(posedge clk2in or negedge clk2in or posedge rst_in)
+     if (rst_in) begin
+        clk2_cnt <= 8'b0;
+        clk2_out <= 0;
+     end
+     else if (clk2ps_en) begin
+          if (clk2_cnt < clk2_div1)
+                clk2_cnt <= clk2_cnt + 1;
+             else
+                clk2_cnt <= 8'b0;
+
+           if (clk2_cnt < clk2_ht1)
+               clk2_out <= 1;
+           else
+               clk2_out <= 0;
+     end
+     else begin
+        clk2_cnt <= 8'b0;
+        clk2_out <= 0;
+     end
+
+  always @(posedge clk3in or negedge clk3in or posedge rst_in)
+     if (rst_in) begin
+        clk3_cnt <= 8'b0;
+        clk3_out <= 0;
+     end
+     else if (clk3ps_en) begin
+          if (clk3_cnt < clk3_div1)
+                clk3_cnt <= clk3_cnt + 1;
+             else
+                clk3_cnt <= 8'b0;
+
+           if (clk3_cnt < clk3_ht1)
+               clk3_out <= 1;
+           else
+               clk3_out <= 0;
+     end
+     else begin
+        clk3_cnt <= 8'b0;
+        clk3_out <= 0;
+     end
+
+
+  always @(posedge clk4in or negedge clk4in or posedge rst_in)
+     if (rst_in) begin
+        clk4_cnt <= 8'b0;
+        clk4_out <= 0;
+     end
+     else if (clk4ps_en) begin
+          if (clk4_cnt < clk4_div1)
+                clk4_cnt <= clk4_cnt + 1;
+             else
+                clk4_cnt <= 8'b0;
+
+           if (clk4_cnt < clk4_ht1)
+               clk4_out <= 1;
+           else
+               clk4_out <= 0;
+     end
+     else begin
+        clk4_cnt <= 8'b0;
+        clk4_out <= 0;
+     end
+
+
+  always @(posedge clk5in or negedge clk5in or posedge rst_in)
+     if (rst_in) begin
+        clk5_cnt <= 8'b0;
+        clk5_out <= 0;
+     end
+     else if (clk5ps_en) begin
+          if (clk5_cnt < clk5_div1)
+                clk5_cnt <= clk5_cnt + 1;
+             else
+                clk5_cnt <= 8'b0;
+
+           if (clk5_cnt < clk5_ht1)
+               clk5_out <= 1;
+           else
+               clk5_out <= 0;
+     end
+     else begin
+        clk5_cnt <= 8'b0;
+        clk5_out <= 0;
+     end
+
+
+  always @(posedge clkfbm1in or negedge clkfbm1in or posedge rst_in)
+     if (rst_in) begin
+        clkfbm1_cnt <= 8'b0;
+        clkfbm1_out <= 0;
+     end
+     else if (clkfbm1ps_en) begin
+          if (clkfbm1_cnt < clkfbm1_div1)
+                clkfbm1_cnt <= clkfbm1_cnt + 1;
+             else
+                clkfbm1_cnt <= 8'b0;
+
+           if (clkfbm1_cnt < clkfbm1_ht1)
+               clkfbm1_out <= 1;
+           else
+               clkfbm1_out <= 0;
+     end
+     else begin
+        clkfbm1_cnt <= 8'b0;
+        clkfbm1_out <= 0;
+     end
+
+
+
+   always @(clk0_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkout0_out =  clk0_out;
+    else
+          clkout0_out = clkfb_tst;
+
+   always @(clk1_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkout1_out =  clk1_out;
+    else
+          clkout1_out = clkfb_tst;
+
+   always @(clk2_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkout2_out =  clk2_out;
+    else
+          clkout2_out = clkfb_tst;
+
+   always @(clk3_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkout3_out =  clk3_out;
+    else
+          clkout3_out = clkfb_tst;
+
+   always @(clk4_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkout4_out =  clk4_out;
+    else
+          clkout4_out = clkfb_tst;
+
+   always @(clk5_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkout5_out =  clk5_out;
+    else
+          clkout5_out = clkfb_tst;
+
+   always @(clkfbm1_out or clkfb_tst or fb_delay_found)
+    if (fb_delay_found == 1)
+          clkfb_out =  clkfbm1_out;
+    else
+          clkfb_out = clkfb_tst;
+
+//
+// determine feedback delay
+//
+
+always @(rst_in1)
+  if (rst_in1)
+      assign clkfb_tst = 0;
+  else
+      deassign clkfb_tst;
+
+always @(posedge clkpll )
+    if (fb_delay_found_tmp == 0 && GSR == 0 && rst_in1 == 0) begin
+         clkfb_tst <=  1'b1;
+    end
+    else
+         clkfb_tst <=  1'b0;
+
+  
+always @( posedge clkfb_tst or posedge rst_in1 )
+  if (rst_in1)
+    delay_edge  <= 0;
+  else 
+    delay_edge <= $time;
+
+always @(posedge clkfb_in or posedge rst_in1 ) 
+  if (rst_in1) begin
+    fb_delay  <= 0;
+    fb_delay_found_tmp <= 0;
+  end
+ else 
+   if (fb_delay_found_tmp ==0 ) begin
+     if ( delay_edge != 0)
+      fb_delay <= ($time - delay_edge);
+     else
+      fb_delay <= 0;
+     fb_delay_found_tmp <=  1;
+   end
+
+always @(rst_in1)
+  if (rst_in1)
+     assign fb_delay_found = 0;
+  else
+     deassign fb_delay_found;
+
+always @(fb_delay_found_tmp or clkvco_delay )
+        fb_delay_found <= #(clkvco_delay) fb_delay_found_tmp;
+
+
+always @(fb_delay)
+  if (rst_in1==0 && (fb_delay/1000.0 > fb_delay_max)) begin
+            $display("Warning : The feedback delay on PLL_ADV instance %m at time %t is %f ns. It is over the maximun value %f ns.", $time, fb_delay / 1000.0, fb_delay_max);
+        end
+
+//
+// generate unlock signal
+//
+
+always @(clkpll) 
+  clkpll_dly <= #clkin_dly_t clkpll;
+
+always @(clkfb_in)
+  if (pmcd_mode != 1)
+     clkfbin_dly <= #clkfb_dly_t clkfb_in;
+  else 
+      clkfbin_dly = 0;
+
+always @( posedge clkpll_dly or negedge clkpll or posedge rst_in)
+  if (rst_in || clkpll == 0) begin
+      clkstop_cnt_p = 0;
+      clkin_stopped_p = 0;
+  end
+  else   
+    if (fb_delay_found && pll_locked_tmp2) begin 
+      if (clkpll && clkpll_jitter_unlock == 0)
+            clkstop_cnt_p <= clkstop_cnt_p +1;
+      else
+            clkstop_cnt_p = 0;
+
+      if (clkstop_cnt_p > clkin_stop_max)
+            clkin_stopped_p <= 1;
+      else
+            clkin_stopped_p = 0;
+     end
+    else begin
+      clkstop_cnt_p = 0;
+      clkin_stopped_p = 0;
+   end
+
+always @( posedge clkpll_dly or posedge clkpll or posedge rst_in)
+  if (rst_in || clkpll == 1) begin
+      clkstop_cnt_n = 0;
+      clkin_stopped_n = 0;
+  end
+  else
+    if (fb_delay_found && pll_locked_tmp2) begin
+      if (clkpll==0 && clkpll_jitter_unlock == 0)
+            clkstop_cnt_n <= clkstop_cnt_n +1;
+      else
+            clkstop_cnt_n = 0;
+
+      if (clkstop_cnt_n > clkin_stop_max)
+            clkin_stopped_n <= 1;
+      else
+            clkin_stopped_n = 0;
+     end
+    else begin
+      clkstop_cnt_n = 0;
+      clkin_stopped_n = 0;
+   end
+
+
+always @( posedge clkfbin_dly or negedge clkfb_in or posedge rst_in)
+  if (rst_in || clkfb_in == 0) begin
+      clkfbstop_cnt_p = 0;
+      clkfb_stopped_p = 0;
+  end
+  else   
+    if (fb_delay_found && pll_locked_tmp2) begin 
+      if (clkfb_in && clkpll_jitter_unlock == 0)
+            clkfbstop_cnt_p <= clkfbstop_cnt_p +1;
+      else
+            clkfbstop_cnt_p = 0;
+
+      if (clkfbstop_cnt_p > clkfb_stop_max)
+            clkfb_stopped_p <= 1;
+      else
+            clkfb_stopped_p = 0;
+     end
+    else begin
+      clkfbstop_cnt_p = 0;
+      clkfb_stopped_p = 0;
+   end
+
+always @( posedge clkfbin_dly or posedge clkfb_in or posedge rst_in)
+  if (rst_in==1 || clkfb_in == 1) begin
+      clkfbstop_cnt_n = 0;
+      clkfb_stopped_n = 0;
+  end
+  else   
+    if (fb_delay_found && pll_locked_tmp2) begin
+      if (clkfb_in==0 && clkpll_jitter_unlock == 0)
+            clkfbstop_cnt_n <= clkfbstop_cnt_n +1;
+      else
+            clkfbstop_cnt_n = 0;
+
+      if (clkfbstop_cnt_n > clkfb_stop_max)
+            clkfb_stopped_n <= 1;
+      else
+            clkfb_stopped_n = 0;
+     end
+    else begin
+      clkfbstop_cnt_n = 0;
+      clkfb_stopped_n = 0;
+   end
+
+always @(clkin_jit or rst_in )
+  if (rst_in)
+      clkpll_jitter_unlock = 0;
+  else
+   if (  pll_locked_tmp2 && clkfb_stopped == 0 && clkin_stopped == 0) begin
+      if ((clkin_jit > REF_CLK_JITTER_MAX_tmp) || (clkin_jit < -REF_CLK_JITTER_MAX_tmp))
+        clkpll_jitter_unlock = 1;
+      else
+         clkpll_jitter_unlock = 0;
+   end
+   else
+         clkpll_jitter_unlock = 0;
+      
+  assign  clkin_stopped = (clkin_stopped_p || clkin_stopped_n) ? 1 : 0;
+  assign  clkfb_stopped = (clkfb_stopped_p ||clkfb_stopped_n) ? 1 : 0;
+  assign pll_unlock = (clkin_stopped || clkfb_stopped || clkpll_jitter_unlock) ? 1 : 0; 
+
+// tasks
+
+
+task clkout_dly_cal;
+output [5:0] clkout_dly;
+output [2:0] clkpm_sel;
+input  clkdiv;
+input  clk_ps;
+input reg [160:0] clk_ps_name;
+
+integer clkdiv;
+real clk_ps;
+real clk_ps_rl;
+
+real clk_dly_rl, clk_dly_rem;
+integer clkout_dly_tmp;
+
+begin
+
+ if (clk_ps < 0.0)
+    clk_dly_rl = (360.0 + clk_ps) * clkdiv / 360.0; 
+ else
+   clk_dly_rl = clk_ps * clkdiv / 360.0;
+
+   clkout_dly_tmp =  $rtoi(clk_dly_rl);
+
+  if (clkout_dly_tmp > 63) begin
+    $display(" Warning : Attribute %s of PLL_ADV on instance %m is set to %f. Required phase shifting can not be reached since it is over the maximum phase shifting ability of X_PLL_ADV", clk_ps_name, clk_ps);
+    clkout_dly = 6'b111111;
+    end
+   else
+     clkout_dly = clkout_dly_tmp;
+
+    clk_dly_rem = clk_dly_rl - clkout_dly;
+
+    if (clk_dly_rem < 0.125)
+        clkpm_sel =  0;
+    else if (clk_dly_rem >=  0.125 && clk_dly_rem < 0.25)
+        clkpm_sel =  1;
+    else if (clk_dly_rem >=  0.25 && clk_dly_rem < 0.375)
+        clkpm_sel =  2;
+    else if (clk_dly_rem >=  0.375 && clk_dly_rem < 0.5)
+        clkpm_sel =  3;
+    else if (clk_dly_rem >=  0.5 && clk_dly_rem < 0.625)
+        clkpm_sel =  4;
+    else if (clk_dly_rem >=  0.625 && clk_dly_rem < 0.75)
+        clkpm_sel =  5;
+    else if (clk_dly_rem >=  0.75 && clk_dly_rem < 0.875)
+        clkpm_sel =  6;
+    else if (clk_dly_rem >=  0.875 )
+        clkpm_sel =  7;
+
+    if (clk_ps < 0.0)
+       clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel)* 360.0 / clkdiv - 360.0;
+    else
+       clk_ps_rl = (clkout_dly + 0.125 * clkpm_sel) * 360.0 / clkdiv;
+
+    if (((clk_ps_rl- clk_ps) > 0.001) || ((clk_ps_rl- clk_ps) < -0.001))
+    $display(" Warning : Attribute %s of PLL_ADV on instance %m is set to %f. Real phase shifting is %f. Required phase shifting can not be reached.", clk_ps_name, clk_ps, clk_ps_rl);
+
+end
+endtask
+
+
+task   clk_out_para_cal;
+output [6:0] clk_ht;
+output [6:0] clk_lt; 
+output clk_nocnt;
+output clk_edge; 
+input  CLKOUT_DIVIDE;
+input  CLKOUT_DUTY_CYCLE;
+
+integer CLKOUT_DIVIDE;
+real  CLKOUT_DUTY_CYCLE;
+
+real tmp_value;
+integer tmp_value1;
+real tmp_value2;
+
+begin
+   tmp_value = CLKOUT_DIVIDE * CLKOUT_DUTY_CYCLE;
+   tmp_value1 = $rtoi(tmp_value * 2) % 2;
+   tmp_value2 = CLKOUT_DIVIDE - tmp_value;
+   
+
+   if ((tmp_value) >= O_MAX_HT_LT) begin
+//       clk_ht = O_MAX_HT_LT;
+       clk_ht = 7'b1000000;
+   end
+   else begin
+       if  (tmp_value < 1.0)
+          clk_ht = 1;
+       else  
+          if ( tmp_value1  != 0)
+             clk_ht = $rtoi(tmp_value) + 1; 
+          else
+             clk_ht = $rtoi(tmp_value);
+   end
+
+   if ( (CLKOUT_DIVIDE -  clk_ht) >= O_MAX_HT_LT)
+       clk_lt = 7'b1000000;
+   else 
+      clk_lt =  CLKOUT_DIVIDE -  clk_ht;
+
+   clk_nocnt = (CLKOUT_DIVIDE ==1) ? 1 : 0;
+   if ( tmp_value < 1.0)
+     clk_edge = 1;
+   else if (tmp_value1 != 0)
+     clk_edge = 1;
+   else
+     clk_edge = 0;
+end
+endtask
+
+
+function  clkout_duty_chk;
+   input  CLKOUT_DIVIDE;
+   input  CLKOUT_DUTY_CYCLE;
+   input reg [160:0] CLKOUT_DUTY_CYCLE_N; 
+
+   integer CLKOUT_DIVIDE, step_tmp;
+   real CLKOUT_DUTY_CYCLE;
+
+   real CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX, CLK_DUTY_CYCLE_STEP;
+   real CLK_DUTY_CYCLE_MIN_rnd;
+   reg clk_duty_tmp_int;
+   
+begin
+
+   if (CLKOUT_DIVIDE > O_MAX_HT_LT) begin
+      CLK_DUTY_CYCLE_MIN = (CLKOUT_DIVIDE - O_MAX_HT_LT)/CLKOUT_DIVIDE;
+      CLK_DUTY_CYCLE_MAX = (O_MAX_HT_LT + 0.5)/CLKOUT_DIVIDE;
+      CLK_DUTY_CYCLE_MIN_rnd = CLK_DUTY_CYCLE_MIN;
+   end
+   else begin
+    if (CLKOUT_DIVIDE == 1) begin
+        CLK_DUTY_CYCLE_MIN = 0.0;
+        CLK_DUTY_CYCLE_MIN_rnd = 0.0;
+     end
+     else begin
+      step_tmp = 1000 / CLKOUT_DIVIDE;
+      CLK_DUTY_CYCLE_MIN_rnd = step_tmp / 1000.0;
+      CLK_DUTY_CYCLE_MIN = 1.0 /CLKOUT_DIVIDE;
+     end
+    CLK_DUTY_CYCLE_MAX = 1.0;
+   end
+
+   if (CLKOUT_DUTY_CYCLE > CLK_DUTY_CYCLE_MAX || CLKOUT_DUTY_CYCLE < CLK_DUTY_CYCLE_MIN_rnd) begin
+     $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is not in the allowed range %f to %f.", CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE, CLK_DUTY_CYCLE_MIN, CLK_DUTY_CYCLE_MAX );
+   end
+
+    clk_duty_tmp_int = 0;
+    CLK_DUTY_CYCLE_STEP = 0.5 / CLKOUT_DIVIDE;
+    for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
+        if (((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) > -0.001 && 
+             ((CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j) - CLKOUT_DUTY_CYCLE) < 0.001)
+            clk_duty_tmp_int = 1;
+
+   if ( clk_duty_tmp_int != 1) begin
+    $display(" Attribute Syntax Warning : %s is set to %f on instance %m and is  not an allowed value. Allowed values are:",  CLKOUT_DUTY_CYCLE_N, CLKOUT_DUTY_CYCLE);
+    for (j = 0; j < (2 * CLKOUT_DIVIDE - CLK_DUTY_CYCLE_MIN/CLK_DUTY_CYCLE_STEP); j = j + 1)
+       $display("%f", CLK_DUTY_CYCLE_MIN + CLK_DUTY_CYCLE_STEP * j);
+  end
+
+  clkout_duty_chk = 1'b1;
+end
+endfunction
+
+
+function  para_int_pmcd_chk;
+   input  para_in;
+   input reg [160:0] para_name;
+   input  range_low;
+   input  range_high;
+   input  pmcd_mode;
+   input  pmcd_value;
+
+    integer para_in;
+    integer range_low;
+    integer range_high;
+    integer pmcd_value;
+begin
+
+        if (para_in < range_low || para_in > range_high)
+        begin
+            $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d.  Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high);
+            $finish;
+        end
+        else if (pmcd_mode == 1 && para_in != pmcd_value) begin
+            $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d when attribute PLL_PMCD_MODE is set to TRUE.  Legal values for this attribute is %d when PLL in PMCD MODE.", para_name, para_in, pmcd_value);
+            $finish;
+        end
+
+   para_int_pmcd_chk = 1'b1;
+end
+endfunction
+
+function  para_real_pmcd_chk;
+   input  para_in;
+   input reg [160:0] para_name;
+   input  range_low;
+   input  range_high;
+   input  pmcd_mode;
+   input  pmcd_value;
+
+    real para_in;
+    real range_low;
+    real range_high;
+    real pmcd_value;
+begin
+
+        if (para_in < range_low || para_in > range_high)
+        begin
+            $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f.  Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high);
+            $finish;
+        end
+        else if (pmcd_mode == 1 && para_in != pmcd_value) begin
+            $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f when attribute PLL_PMCD_MODE is set to TRUE.  Legal values for this attribute is %f when PLL in PMCD MODE.", para_name, para_in, pmcd_value);
+            $finish;
+        end
+ 
+    para_real_pmcd_chk = 1'b0;
+end
+endfunction
+
+function  para_int_range_chk;
+   input  para_in; 
+   input reg [160:0] para_name;
+   input  range_low;
+   input  range_high;
+
+    integer para_in;
+    integer range_low;
+    integer  range_high;
+begin
+        if ( para_in < range_low || para_in > range_high) begin
+           $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %d.  Legal values for this attribute are %d to %d.", para_name, para_in, range_low, range_high);
+           $finish;
+          end
+        para_int_range_chk = 1'b1;
+end
+endfunction
+
+function  para_real_range_chk;
+   input  para_in;
+   input reg [160:0] para_name;
+   input  range_low;
+   input  range_high;
+
+   real para_in;
+   real range_low;
+   real range_high;
+begin
+        if ( para_in < range_low || para_in > range_high) begin
+           $display("Attribute Syntax Error : The Attribute %s on PLL_ADV instance %m is set to %f.  Legal values for this attribute are %f to %f.", para_name, para_in, range_low, range_high);
+           $finish;
+          end
+
+        para_real_range_chk = 1'b0;
+end
+endfunction
+
+task clkout_pm_cal;
+   output [7:0] clk_ht1;
+   output [7:0] clk_div;
+   output [7:0] clk_div1;
+   input [6:0] clk_ht;
+   input [6:0] clk_lt;
+   input clk_nocnt;
+   input clk_edge;
+
+begin
+    if (clk_nocnt ==1) begin
+        clk_div = 8'b00000001;
+         clk_div1 = 8'b00000001;
+        clk_ht1 = 8'b00000001;
+    end
+    else begin
+       if ( clk_edge == 1)
+               clk_ht1 = 2 * clk_ht -1;
+          else
+               clk_ht1 = 2 * clk_ht;
+       clk_div = clk_ht  + clk_lt ;
+       clk_div1 = 2 * clk_div -1;
+    end
+end
+endtask
+
+task clkout_delay_para_drp;
+  output [5:0] clkout_dly;
+  output clk_nocnt;
+  output clk_edge;
+  input [15:0]  di_in;
+  input [4:0] daddr_in;
+begin
+
+//     if (di_in[15:8] != 8'h00) begin
+//          $display(" Error : PLL_ADV on instance %m input DI[15:8] is set to %h and need to be set to 00h at address DADDR=%b at time %t.", di_in[15:8], daddr_in, $time); 
+//          $finish;
+//     end
+     clkout_dly = di_in[5:0];
+     clk_nocnt = di_in[6];
+     clk_edge = di_in[7];
+end
+endtask
+
+task clkout_hl_para_drp;
+  output  [6:0] clk_lt;
+  output  [6:0] clk_ht;
+  output  [2:0] clkpm_sel;
+  input [15:0] di_in_tmp;
+  input [4:0] daddr_in_tmp;
+begin
+    if (di_in_tmp[12] != 1) begin
+         $display(" Error : PLL_ADV on instance %m input DI is %h at address DADDR=%b at time %t. The bit 12 need to be set to 1 .", di_in_tmp, daddr_in_tmp, $time); 
+//         $finish;
+    end
+    if ( di_in_tmp[5:0] == 6'b0)
+       clk_lt = 7'b1000000;
+    else
+        clk_lt = { 1'b0, di_in[5:0]};
+    if (di_in_tmp[11:6] == 6'b0)
+      clk_ht = 7'b1000000;
+    else
+       clk_ht = { 1'b0, di_in_tmp[11:6]};
+    clkpm_sel = di_in_tmp[15:13];
+end
+endtask
+
+
+
+endmodule
diff --git a/fpga/usrp2/models/PLL_BASE.v b/fpga/usrp2/models/PLL_BASE.v
new file mode 100644
index 000000000..f2180a25a
--- /dev/null
+++ b/fpga/usrp2/models/PLL_BASE.v
@@ -0,0 +1,150 @@
+// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/rainier/PLL_BASE.v,v 1.5 2006/03/13 21:53:44 yanx Exp $
+///////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995/2004 Xilinx, Inc.
+// All Right Reserved.
+///////////////////////////////////////////////////////////////////////////////
+//   ____  ____
+//  /   /\/   /
+// /___/  \  /    Vendor : Xilinx
+// \   \   \/     Version : 10.1
+//  \   \         Description : Xilinx Timing Simulation Library Component
+//  /   /                  Phase Lock Loop Clock
+// /___/   /\     Filename : PLL_BASE.v
+// \   \  /  \    Timestamp : 
+//  \___\/\___\
+//
+// Revision:
+//    12/02/05 - Initial version.
+//    02/24/06 - Add real/integer to parameter.
+// End Revision
+
+
+`timescale 1 ps / 1 ps 
+
+module PLL_BASE (
+	CLKFBOUT,
+	CLKOUT0,
+	CLKOUT1,
+	CLKOUT2,
+	CLKOUT3,
+	CLKOUT4,
+	CLKOUT5,
+	LOCKED,
+	CLKFBIN,
+	CLKIN,
+	RST
+
+);
+
+parameter BANDWIDTH = "OPTIMIZED";
+parameter integer CLKFBOUT_MULT = 1;
+parameter real CLKFBOUT_PHASE = 0.0;
+parameter real CLKIN_PERIOD = 0.000;
+parameter integer CLKOUT0_DIVIDE = 1;
+parameter real CLKOUT0_DUTY_CYCLE = 0.5;
+parameter real CLKOUT0_PHASE = 0.0;
+parameter integer CLKOUT1_DIVIDE = 1;
+parameter real CLKOUT1_DUTY_CYCLE = 0.5;
+parameter real CLKOUT1_PHASE = 0.0;
+parameter integer CLKOUT2_DIVIDE = 1;
+parameter real CLKOUT2_DUTY_CYCLE = 0.5;
+parameter real CLKOUT2_PHASE = 0.0;
+parameter integer CLKOUT3_DIVIDE = 1;
+parameter real CLKOUT3_DUTY_CYCLE = 0.5;
+parameter real CLKOUT3_PHASE = 0.0;
+parameter integer CLKOUT4_DIVIDE = 1;
+parameter real CLKOUT4_DUTY_CYCLE = 0.5;
+parameter real CLKOUT4_PHASE = 0.0;
+parameter integer CLKOUT5_DIVIDE = 1;
+parameter real CLKOUT5_DUTY_CYCLE = 0.5;
+parameter real CLKOUT5_PHASE = 0.0;
+parameter COMPENSATION = "SYSTEM_SYNCHRONOUS";
+parameter integer DIVCLK_DIVIDE = 1;
+parameter real REF_JITTER = 0.100;
+parameter RESET_ON_LOSS_OF_LOCK = "FALSE";
+
+
+output CLKFBOUT;
+output CLKOUT0;
+output CLKOUT1;
+output CLKOUT2;
+output CLKOUT3;
+output CLKOUT4;
+output CLKOUT5;
+output LOCKED;
+
+input CLKFBIN;
+input CLKIN;
+input RST;
+
+
+wire OPEN_CLKFBDCM;
+wire OPEN_CLKOUTDCM0;
+wire OPEN_CLKOUTDCM1;
+wire OPEN_CLKOUTDCM2;
+wire OPEN_CLKOUTDCM3;
+wire OPEN_CLKOUTDCM4;
+wire OPEN_CLKOUTDCM5;
+wire OPEN_DRDY;
+wire [15:0] OPEN_DO;
+
+PLL_ADV pll_adv_1 (
+	.CLKFBDCM (OPEN_CLKFBDCM),
+	.CLKFBIN (CLKFBIN),
+	.CLKFBOUT (CLKFBOUT),
+	.CLKIN1 (CLKIN),
+	.CLKIN2 (1'b0),
+	.CLKOUT0 (CLKOUT0),
+	.CLKOUT1 (CLKOUT1),
+	.CLKOUT2 (CLKOUT2),
+	.CLKOUT3 (CLKOUT3),
+	.CLKOUT4 (CLKOUT4),
+	.CLKOUT5 (CLKOUT5),
+	.CLKOUTDCM0 (OPEN_CLKOUTDCM0),
+	.CLKOUTDCM1 (OPEN_CLKOUTDCM1),
+	.CLKOUTDCM2 (OPEN_CLKOUTDCM2),
+	.CLKOUTDCM3 (OPEN_CLKOUTDCM3),
+	.CLKOUTDCM4 (OPEN_CLKOUTDCM4),
+	.CLKOUTDCM5 (OPEN_CLKOUTDCM5),
+	.DADDR (5'b0),
+	.DCLK (1'b0),
+	.DEN (1'b0),
+	.DI (16'b0),
+	.DO (OPEN_DO),
+	.DRDY (OPEN_DRDY),
+	.DWE (1'b0),
+	.LOCKED (LOCKED),
+        .CLKINSEL(1'b1),
+	.REL (1'b0),
+	.RST (RST)
+);
+
+defparam pll_adv_1.BANDWIDTH = BANDWIDTH;
+defparam pll_adv_1.CLKFBOUT_MULT = CLKFBOUT_MULT;
+defparam pll_adv_1.CLKFBOUT_PHASE = CLKFBOUT_PHASE;
+defparam pll_adv_1.CLKIN1_PERIOD = CLKIN_PERIOD;
+defparam pll_adv_1.CLKIN2_PERIOD = 10.0;
+defparam pll_adv_1.CLKOUT0_DIVIDE = CLKOUT0_DIVIDE;
+defparam pll_adv_1.CLKOUT0_DUTY_CYCLE = CLKOUT0_DUTY_CYCLE;
+defparam pll_adv_1.CLKOUT0_PHASE = CLKOUT0_PHASE;
+defparam pll_adv_1.CLKOUT1_DIVIDE = CLKOUT1_DIVIDE;
+defparam pll_adv_1.CLKOUT1_DUTY_CYCLE = CLKOUT1_DUTY_CYCLE;
+defparam pll_adv_1.CLKOUT1_PHASE = CLKOUT1_PHASE;
+defparam pll_adv_1.CLKOUT2_DIVIDE = CLKOUT2_DIVIDE;
+defparam pll_adv_1.CLKOUT2_DUTY_CYCLE = CLKOUT2_DUTY_CYCLE;
+defparam pll_adv_1.CLKOUT2_PHASE = CLKOUT2_PHASE;
+defparam pll_adv_1.CLKOUT3_DIVIDE = CLKOUT3_DIVIDE;
+defparam pll_adv_1.CLKOUT3_DUTY_CYCLE = CLKOUT3_DUTY_CYCLE;
+defparam pll_adv_1.CLKOUT3_PHASE = CLKOUT3_PHASE;
+defparam pll_adv_1.CLKOUT4_DIVIDE = CLKOUT4_DIVIDE;
+defparam pll_adv_1.CLKOUT4_DUTY_CYCLE = CLKOUT4_DUTY_CYCLE;
+defparam pll_adv_1.CLKOUT4_PHASE = CLKOUT4_PHASE;
+defparam pll_adv_1.CLKOUT5_DIVIDE = CLKOUT5_DIVIDE;
+defparam pll_adv_1.CLKOUT5_DUTY_CYCLE = CLKOUT5_DUTY_CYCLE;
+defparam pll_adv_1.CLKOUT5_PHASE = CLKOUT5_PHASE;
+defparam pll_adv_1.COMPENSATION = COMPENSATION;
+defparam pll_adv_1.DIVCLK_DIVIDE = DIVCLK_DIVIDE;
+defparam pll_adv_1.REF_JITTER = REF_JITTER;
+defparam pll_adv_1.RESET_ON_LOSS_OF_LOCK = RESET_ON_LOSS_OF_LOCK;
+
+endmodule
diff --git a/fpga/usrp2/top/B100/B100.v b/fpga/usrp2/top/B100/B100.v
index dcda974b4..cb4efa4fa 100644
--- a/fpga/usrp2/top/B100/B100.v
+++ b/fpga/usrp2/top/B100/B100.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -50,6 +50,8 @@ module B100
    // /////////////////////////////////////////////////////////////////////////
    // Clocking
    wire  clk_fpga, clk_fpga_in, reset;
+   wire gpif_clk = IFCLK;
+   wire gpif_rst;
    
    IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
    clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
@@ -57,6 +59,7 @@ module B100
    BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
    
    reset_sync reset_sync(.clk(clk_fpga), .reset_in((~reset_n) | (~ext_reset)), .reset_out(reset));
+   reset_sync reset_sync_gpif(.clk(gpif_clk), .reset_in((~reset_n) | (~ext_reset)), .reset_out(gpif_rst));
    
    // /////////////////////////////////////////////////////////////////////////
    // SPI
@@ -105,6 +108,7 @@ module B100
    // /////////////////////////////////////////////////////////////////////////
    // RX ADC -- handles deinterleaving
 
+   wire rxsync_0, rxsync_1;
    reg [11:0] rx_i, rx_q;
    wire [11:0] rx_a, rx_b;
    
@@ -151,24 +155,60 @@ module B100
 	  rx_i <= rx_a;
 	  rx_q <= rx_b;
        end
-   
+
    // /////////////////////////////////////////////////////////////////////////
-   // Main U1E Core
-   u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
-		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
-		     .debug_txd(), .debug_rxd(1'b1),
-		     
-		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_pktend(GPIF_PKTEND),
-		     .gpif_sloe(GPIF_SLOE), .gpif_slwr(GPIF_SLWR), .gpif_slrd(GPIF_SLRD),
-		     .gpif_fifoadr(GPIF_ADR), .gpif_clk(IFCLK),
-
-		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
-		     .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
-		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
-		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
-		     .io_tx(io_tx), .io_rx(io_rx),
-		     .tx_i(tx_i), .tx_q(tx_q), 
-		     .rx_i(rx_i), .rx_q(rx_q),
-		     .pps_in(PPS_IN) );
+   // Main Core
+   wire [35:0] rx_data, tx_data, ctrl_data, resp_data;
+   wire rx_src_rdy, rx_dst_rdy, tx_src_rdy, tx_dst_rdy, resp_src_rdy, resp_dst_rdy, ctrl_src_rdy, ctrl_dst_rdy;
+   wire dsp_rx_run, dsp_tx_run;
+   wire [7:0] sen8;
+   assign {SEN_CODEC,SEN_TX_DB,SEN_RX_DB} = sen8[2:0];
+    wire [31:0] core_debug;
+
+   assign debug_led = {dsp_tx_run, dsp_rx_run, cgen_st_ld};
+   wire cgen_sync;
+   assign { cgen_sync_b, cgen_ref_sel } = {~cgen_sync, 1'b1};
+
+   u1plus_core #(
+        .NUM_RX_DSPS(1),
+        .DSP_RX_XTRA_FIFOSIZE(11),
+        .DSP_TX_XTRA_FIFOSIZE(12),
+        .USE_PACKET_PADDER(1)
+    ) core(
+         .clk(clk_fpga), .reset(reset),
+         .debug(core_debug), .debug_clk(debug_clk),
+
+         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+         .dsp_rx_run(dsp_rx_run), .dsp_tx_run(dsp_tx_run),
+         .clock_sync(cgen_sync),
+
+         .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
+         .sclk(sclk), .sen(sen8), .mosi(mosi), .miso(miso),
+         .io_tx(io_tx), .io_rx(io_rx),
+         .tx_i(tx_i), .tx_q(tx_q),
+         .rx_i(rx_i), .rx_q(rx_q),
+         .pps_in(PPS_IN) );
+
+    // /////////////////////////////////////////////////////////////////////////
+    // Interface from host to/from GPIF
+    wire [31:0] gpif_debug;
+    slave_fifo slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(GPIF_D),
+         .gpif_ctl(GPIF_CTL), .sloe(GPIF_SLOE), .slwr(GPIF_SLWR), .slrd(GPIF_SLRD),
+         .pktend(GPIF_PKTEND), .fifoadr(GPIF_ADR),
+
+         .fifo_clk(clk_fpga), .fifo_rst(reset),
+         .rx_data(rx_data), .rx_src_rdy(rx_src_rdy), .rx_dst_rdy(rx_dst_rdy),
+         .tx_data(tx_data), .tx_src_rdy(tx_src_rdy), .tx_dst_rdy(tx_dst_rdy),
+         .ctrl_data(ctrl_data), .ctrl_src_rdy(ctrl_src_rdy), .ctrl_dst_rdy(ctrl_dst_rdy),
+         .resp_data(resp_data), .resp_src_rdy(resp_src_rdy), .resp_dst_rdy(resp_dst_rdy),
+
+         .debug(gpif_debug));
+
+    //assign debug = gpif_debug;
+    assign debug = core_debug;
 
 endmodule // B100
diff --git a/fpga/usrp2/top/B100/Makefile b/fpga/usrp2/top/B100/Makefile
deleted file mode 100644
index 3ddef1024..000000000
--- a/fpga/usrp2/top/B100/Makefile
+++ /dev/null
@@ -1,14 +0,0 @@
-#
-# Copyright 2011 Ettus Research LLC
-#
-
-all: B100
-	find -name "*.twr" | xargs grep constraint | grep met
-
-clean:
-	rm -rf build*
-
-B100:
-	make -f Makefile.$@ bin
-
-.PHONY: all clean
diff --git a/fpga/usrp2/top/B100/core_compile b/fpga/usrp2/top/B100/core_compile
index b62cbaee0..2192bfa94 100755
--- a/fpga/usrp2/top/B100/core_compile
+++ b/fpga/usrp2/top/B100/core_compile
@@ -1 +1 @@
-iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v  2>&1   | grep -v timescale | grep -v coregen | grep -v models
+iverilog -Wall -y. -y ../../control_lib/ -y ../../custom/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac B100.v  2>&1   | grep -v timescale | grep -v coregen | grep -v models
diff --git a/fpga/usrp2/top/B100/timing.ucf b/fpga/usrp2/top/B100/timing.ucf
index 96c47cf2c..c4404e1d0 100644
--- a/fpga/usrp2/top/B100/timing.ucf
+++ b/fpga/usrp2/top/B100/timing.ucf
@@ -5,10 +5,15 @@ NET "IFCLK" TNM_NET = "IFCLK";
 TIMESPEC "TS_IFCLK" = PERIOD "IFCLK" 20833 ps HIGH 50 %;
 
 #constrain FX2 IO
-NET "GPIF_D<*>" MAXDELAY = 5.5 ns;
-NET "GPIF_CTL<*>" MAXDELAY = 5.5 ns;
-NET "GPIF_ADR<*>" MAXDELAY = 5.5ns;
-NET "GPIF_SLWR" MAXDELAY = 5.5 ns;
-NET "GPIF_SLRD" MAXDELAY = 5.5 ns;
-NET "GPIF_SLOE" MAXDELAY = 5.5 ns;
-NET "GPIF_PKTEND" MAXDELAY = 5.5 ns;
+INST "GPIF_D<*>" TNM = gpif_net_in;
+INST "GPIF_CTL<*>" TNM = gpif_net_in;
+
+INST "GPIF_D<*>" TNM = gpif_net_out;
+INST "GPIF_ADR<*>" TNM = gpif_net_out;
+INST "GPIF_SLWR" TNM = gpif_net_out;
+INST "GPIF_SLOE" TNM = gpif_net_out;
+INST "GPIF_SLRD" TNM = gpif_net_out;
+INST "GPIF_PKTEND" TNM = gpif_net_out;
+
+TIMEGRP "gpif_net_in" OFFSET = IN 7 ns VALID 14 ns BEFORE "IFCLK" RISING;
+TIMEGRP "gpif_net_out" OFFSET = OUT 7 ns AFTER "IFCLK" RISING;
diff --git a/fpga/usrp2/top/B100/u1plus.ucf b/fpga/usrp2/top/B100/u1plus.ucf
deleted file mode 100644
index 3ecc4daf2..000000000
--- a/fpga/usrp2/top/B100/u1plus.ucf
+++ /dev/null
@@ -1,203 +0,0 @@
-## Main Clock
-NET "CLK_FPGA_P"  LOC = "R7"  ;
-NET "CLK_FPGA_N"  LOC = "T7"  ;
-
-## UART
-NET "FPGA_TXD"  LOC = "H16"  ;
-NET "FPGA_RXD"  LOC = "H12"  ;
-
-## I2C
-NET "SDA_FPGA"  LOC = "T13"  ;
-NET "SCL_FPGA"  LOC = "R13"  ;
-
-## CGEN
-NET "cgen_st_ld"  LOC = "M13"  ;
-NET "cgen_st_refmon"  LOC = "J14"  ;
-NET "cgen_st_status"  LOC = "P6"  ;
-NET "cgen_ref_sel"  LOC = "T2"  ;
-NET "cgen_sync_b"  LOC = "H15"  ;
-
-## FPGA Config
-#NET "fpga_cfg_din"  LOC = "T14"  ;
-#NET "fpga_cfg_cclk"  LOC = "R14"  ;
-#NET "fpga_cfg_init_b"  LOC = "T12"  ;
-
-## MISC
-#NET "mystery_bus<2>"  LOC = "T11"  ;
-#NET "mystery_bus<1>"  LOC = "C4"  ;
-#NET "mystery_bus<0>"  LOC = "E7"  ;
-NET "reset_n"  LOC = "D5"  ;
-NET "PPS_IN"  LOC = "M14"  ;
-NET "reset_codec"  LOC = "B14"  ;
-
-## GPIF
-NET "GPIF_D<15>"  LOC = "P7"  ;
-NET "GPIF_D<14>"  LOC = "N8"  ;
-NET "GPIF_D<13>"  LOC = "T5"  ;
-NET "GPIF_D<12>"  LOC = "T6"  ;
-NET "GPIF_D<11>"  LOC = "N6"  ;
-NET "GPIF_D<10>"  LOC = "P5"  ;
-NET "GPIF_D<9>"  LOC = "R3"  ;
-NET "GPIF_D<8>"  LOC = "T3"  ;
-NET "GPIF_D<7>"  LOC = "N12"  ;
-NET "GPIF_D<6>"  LOC = "P13"  ;
-NET "GPIF_D<5>"  LOC = "P11"  ;
-NET "GPIF_D<4>"  LOC = "R9"  ;
-NET "GPIF_D<3>"  LOC = "T9"  ;
-NET "GPIF_D<2>"  LOC = "N9"  ;
-NET "GPIF_D<1>"  LOC = "P9"  ;
-NET "GPIF_D<0>"  LOC = "P8"  ;
-
-NET "GPIF_CTL<3>"  LOC = "N5"  ;
-NET "GPIF_CTL<2>"  LOC = "M11"  ;
-NET "GPIF_CTL<1>"  LOC = "M9"  ;
-NET "GPIF_CTL<0>"  LOC = "M7"  ;
-
-NET "GPIF_RDY<3>"  LOC = "N11"  ;
-NET "GPIF_RDY<2>"  LOC = "T10"  ;
-NET "GPIF_RDY<1>"  LOC = "T4"  ;
-NET "GPIF_RDY<0>"  LOC = "R5"  ;
-
-NET "FX2_PA7_FLAGD"  LOC = "P12"  ;
-NET "FX2_PA6_PKTEND"  LOC = "R11"  ;
-NET "FX2_PA2_SLOE"  LOC = "P10"  ;
-
-NET "IFCLK"  LOC = "T8"  ;
-
-## LEDs
-NET "debug_led<2>"  LOC = "R2"  ;
-NET "debug_led<1>"  LOC = "N4"  ;
-NET "debug_led<0>"  LOC = "P4"  ;
-
-## Debug bus
-NET "debug_clk<0>"  LOC = "K15"  ;
-NET "debug_clk<1>"  LOC = "K14"  ;
-NET "debug<0>"  LOC = "K16"  ;
-NET "debug<1>"  LOC = "J16"  ;
-NET "debug<2>"  LOC = "C16"  ;
-NET "debug<3>"  LOC = "C15"  ;
-NET "debug<4>"  LOC = "E13"  ;
-NET "debug<5>"  LOC = "D14"  ;
-NET "debug<6>"  LOC = "D16"  ;
-NET "debug<7>"  LOC = "D15"  ;
-NET "debug<8>"  LOC = "E14"  ;
-NET "debug<9>"  LOC = "F13"  ;
-NET "debug<10>"  LOC = "G13"  ;
-NET "debug<11>"  LOC = "F14"  ;
-NET "debug<12>"  LOC = "E16"  ;
-NET "debug<13>"  LOC = "F15"  ;
-NET "debug<14>"  LOC = "H13"  ;
-NET "debug<15>"  LOC = "G14"  ;
-NET "debug<16>"  LOC = "G16"  ;
-NET "debug<17>"  LOC = "F16"  ;
-NET "debug<18>"  LOC = "J12"  ;
-NET "debug<19>"  LOC = "J13"  ;
-NET "debug<20>"  LOC = "L14"  ;
-NET "debug<21>"  LOC = "L16"  ;
-NET "debug<22>"  LOC = "M15"  ;
-NET "debug<23>"  LOC = "M16"  ;
-NET "debug<24>"  LOC = "L13"  ;
-NET "debug<25>"  LOC = "K13"  ;
-NET "debug<26>"  LOC = "P16"  ;
-NET "debug<27>"  LOC = "N16"  ;
-NET "debug<28>"  LOC = "R15"  ;
-NET "debug<29>"  LOC = "P15"  ;
-NET "debug<30>"  LOC = "N13"  ;
-NET "debug<31>"  LOC = "N14"  ;
-
-## ADC
-NET "adc<11>"  LOC = "B15"  ;
-NET "adc<10>"  LOC = "A8"  ;
-NET "adc<9>"  LOC = "B8"  ;
-NET "adc<8>"  LOC = "C8"  ;
-NET "adc<7>"  LOC = "D8"  ;
-NET "adc<6>"  LOC = "C9"  ;
-NET "adc<5>"  LOC = "A9"  ;
-NET "adc<4>"  LOC = "C10"  ;
-NET "adc<3>"  LOC = "D9"  ;
-NET "adc<2>"  LOC = "A3"  ;
-NET "adc<1>"  LOC = "B3"  ;
-NET "adc<0>"  LOC = "A4"  ;
-NET "RXSYNC"  LOC = "D10"  ;
-
-## DAC
-NET "TXBLANK"  LOC = "K1"  ;
-NET "TXSYNC"  LOC = "J2"  ;
-NET "dac<0>"  LOC = "J1"  ;
-NET "dac<1>"  LOC = "H3"  ;
-NET "dac<2>"  LOC = "J3"  ;
-NET "dac<3>"  LOC = "G2"  ;
-NET "dac<4>"  LOC = "H1"  ;
-NET "dac<5>"  LOC = "N3"  ;
-NET "dac<6>"  LOC = "M4"  ;
-NET "dac<7>"  LOC = "R1"  ;
-NET "dac<8>"  LOC = "P2"  ;
-NET "dac<9>"  LOC = "P1"  ;
-NET "dac<10>"  LOC = "M1"  ;
-NET "dac<11>"  LOC = "N1"  ;
-NET "dac<12>"  LOC = "M3"  ;
-NET "dac<13>"  LOC = "L4"  ;
-
-## TX DB
-NET "io_tx<0>"  LOC = "K4"  ;
-NET "io_tx<1>"  LOC = "L3"  ;
-NET "io_tx<2>"  LOC = "L2"  ;
-NET "io_tx<3>"  LOC = "F1"  ;
-NET "io_tx<4>"  LOC = "F3"  ;
-NET "io_tx<5>"  LOC = "G3"  ;
-NET "io_tx<6>"  LOC = "E3"  ;
-NET "io_tx<7>"  LOC = "E2"  ;
-NET "io_tx<8>"  LOC = "E4"  ;
-NET "io_tx<9>"  LOC = "F4"  ;
-NET "io_tx<10>"  LOC = "D1"  ;
-NET "io_tx<11>"  LOC = "E1"  ;
-NET "io_tx<12>"  LOC = "D4"  ;
-NET "io_tx<13>"  LOC = "D3"  ;
-NET "io_tx<14>"  LOC = "C2"  ;
-NET "io_tx<15>"  LOC = "C1"  ;
-
-## RX DB
-NET "io_rx<0>"  LOC = "D7"  ;
-NET "io_rx<1>"  LOC = "C6"  ;
-NET "io_rx<2>"  LOC = "A6"  ;
-NET "io_rx<3>"  LOC = "B6"  ;
-NET "io_rx<4>"  LOC = "E9"  ;
-NET "io_rx<5>"  LOC = "A7"  ;
-NET "io_rx<6>"  LOC = "C7"  ;
-NET "io_rx<7>"  LOC = "B10"  ;
-NET "io_rx<8>"  LOC = "A10"  ;
-NET "io_rx<9>"  LOC = "C11"  ;
-NET "io_rx<10>"  LOC = "A11"  ;
-NET "io_rx<11>"  LOC = "D11"  ;
-NET "io_rx<12>"  LOC = "B12"  ;
-NET "io_rx<13>"  LOC = "A12"  ;
-NET "io_rx<14>"  LOC = "A14"  ;
-NET "io_rx<15>"  LOC = "A13"  ;
-
-## SPI
-#NET "SEN_AUX"  LOC = "C12"  ;
-#NET "SCLK_AUX"  LOC = "D12"  ;
-#NET "MISO_AUX"  LOC = "J5"  ;
-NET "SCLK_CODEC"  LOC = "K3"  ;
-NET "SEN_CODEC"  LOC = "D13"  ;
-NET "MOSI_CODEC"  LOC = "C13"  ;
-NET "MISO_CODEC"  LOC = "G4"  ;
-
-NET "MISO_RX_DB"  LOC = "E6"  ;
-NET "SEN_RX_DB"  LOC = "B4"  ;
-NET "MOSI_RX_DB"  LOC = "A5"  ;
-NET "SCLK_RX_DB"  LOC = "C5"  ;
-
-NET "MISO_TX_DB"  LOC = "J4"  ;
-NET "SEN_TX_DB"  LOC = "N2"  ;
-NET "MOSI_TX_DB"  LOC = "L1"  ;
-NET "SCLK_TX_DB"  LOC = "G1"  ;
-
-## Dedicated pins
-#NET "TMS"  LOC = "B2"  ;
-#NET "TDO"  LOC = "B16"  ;
-#NET "TDI"  LOC = "B1"  ;
-#NET "TCK"  LOC = "A15"  ;
-
-#NET "fpga_cfg_prog_b"  LOC = "A2"  ;
-#NET "fpga_cfg_done"  LOC = "T15"  ;
diff --git a/fpga/usrp2/top/B100/u1plus.v b/fpga/usrp2/top/B100/u1plus.v
deleted file mode 100644
index 5e3200580..000000000
--- a/fpga/usrp2/top/B100/u1plus.v
+++ /dev/null
@@ -1,173 +0,0 @@
-//
-// Copyright 2011 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-`timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-
-module u1plus
-  (input CLK_FPGA_P, input CLK_FPGA_N,  // Diff
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   output FPGA_TXD, input FPGA_RXD,
-
-   // GPIF
-   inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
-   output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE,
-   input IFCLK,
-   
-   inout SDA_FPGA, inout SCL_FPGA, // I2C
-
-   output SCLK_TX_DB, output SEN_TX_DB, output MOSI_TX_DB, input MISO_TX_DB,   // DB TX SPI
-   output SCLK_RX_DB, output SEN_RX_DB, output MOSI_RX_DB, input MISO_RX_DB,   // DB TX SPI
-   output SCLK_CODEC, output SEN_CODEC, output MOSI_CODEC, input MISO_CODEC,   // AD9862 main SPI
-
-   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,
-   
-   inout [15:0] io_tx, inout [15:0] io_rx,
-
-   output [13:0] dac, output TXSYNC, output TXBLANK,
-   input [11:0] adc, input RXSYNC,
-  
-   input PPS_IN,
-   input reset_n, output reset_codec
-   );
-
-   assign reset_codec = 1;  // Believed to be active low
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Clocking
-   wire  clk_fpga, clk_fpga_in, reset;
-   
-   IBUFGDS #(.IOSTANDARD("LVDS_33"), .DIFF_TERM("TRUE")) 
-   clk_fpga_pin (.O(clk_fpga_in),.I(CLK_FPGA_P),.IB(CLK_FPGA_N));
-
-   BUFG clk_fpga_BUFG (.I(clk_fpga_in), .O(clk_fpga));
-   
-   reset_sync reset_sync(.clk(clk_fpga), .reset_in(~reset_n), .reset_out(reset));
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // SPI
-   wire  mosi, sclk, miso;
-   assign { SCLK_TX_DB, MOSI_TX_DB } = ~SEN_TX_DB ? {sclk,mosi} : 2'b0;
-   assign { SCLK_RX_DB, MOSI_RX_DB } = ~SEN_RX_DB ? {sclk,mosi} : 2'b0;
-   assign { SCLK_CODEC, MOSI_CODEC } = ~SEN_CODEC ? {sclk,mosi} : 2'b0;
-   assign miso = (~SEN_TX_DB & MISO_TX_DB) | (~SEN_RX_DB & MISO_RX_DB) |
-		 (~SEN_CODEC & MISO_CODEC);
-
-   // /////////////////////////////////////////////////////////////////////////
-   // TX DAC -- handle the interleaved data bus to DAC, with clock doubling DLL
-
-   assign TXBLANK = 0;
-   wire [13:0] tx_i, tx_q;
-
-   genvar i;
-   generate
-      for(i=0;i<14;i=i+1)
-	begin : gen_dacout
-	   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
-		   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
-		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-	   ODDR2_inst (.Q(dac[i]),      // 1-bit DDR output data
-		       .C0(clk_fpga),  // 1-bit clock input
-		       .C1(~clk_fpga), // 1-bit clock input
-		       .CE(1'b1),      // 1-bit clock enable input
-		       .D0(tx_i[i]),   // 1-bit data input (associated with C0)
-		       .D1(tx_q[i]),   // 1-bit data input (associated with C1)
-		       .R(1'b0),       // 1-bit reset input
-		       .S(1'b0));      // 1-bit set input
-	end // block: gen_dacout
-      endgenerate
-   ODDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1" 
-	   .INIT(1'b0),            // Sets initial state of the Q output to 1'b0 or 1'b1
-	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-   ODDR2_txsnc (.Q(TXSYNC),      // 1-bit DDR output data
-		.C0(clk_fpga),  // 1-bit clock input
-		.C1(~clk_fpga), // 1-bit clock input
-		.CE(1'b1),      // 1-bit clock enable input
-		.D0(1'b0),   // 1-bit data input (associated with C0)
-		.D1(1'b1),   // 1-bit data input (associated with C1)
-		.R(1'b0),       // 1-bit reset input
-		.S(1'b0));      // 1-bit set input
-
-   // /////////////////////////////////////////////////////////////////////////
-   // RX ADC -- handles deinterleaving
-
-   reg [11:0] rx_i, rx_q;
-   wire [11:0] rx_a, rx_b;
-   
-   genvar      j;
-   generate
-      for(j=0;j<12;j=j+1)
-	begin : gen_adcin
-	   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
-		   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
-		   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
-		   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-	   IDDR2_inst (.Q0(rx_a[j]),      // 1-bit output captured with C0 clock
-		       .Q1(rx_b[j]),      // 1-bit output captured with C1 clock
-		       .C0(clk_fpga),     // 1-bit clock input
-		       .C1(~clk_fpga),    // 1-bit clock input
-		       .CE(1'b1),         // 1-bit clock enable input
-		       .D(adc[j]),        // 1-bit DDR data input
-		       .R(1'b0),          // 1-bit reset input
-		       .S(1'b0));         // 1-bit set input
-	end // block: gen_adcin
-   endgenerate
-   
-   IDDR2 #(.DDR_ALIGNMENT("NONE"), // Sets output alignment to "NONE", "C0" or "C1"
-	   .INIT_Q0(1'b0),         // Sets initial state of the Q0 output to 1’b0 or 1’b1
-	   .INIT_Q1(1'b0),         // Sets initial state of the Q1 output to 1’b0 or 1’b1
-	   .SRTYPE("SYNC"))        // Specifies "SYNC" or "ASYNC" set/reset
-   IDDR2_sync (.Q0(rxsync_0),      // 1-bit output captured with C0 clock
-	       .Q1(rxsync_1),      // 1-bit output captured with C1 clock
-	       .C0(clk_fpga),     // 1-bit clock input
-	       .C1(~clk_fpga),    // 1-bit clock input
-	       .CE(1'b1),         // 1-bit clock enable input
-	       .D(RXSYNC),        // 1-bit DDR data input
-	       .R(1'b0),          // 1-bit reset input
-	       .S(1'b0));         // 1-bit set input
-
-   always @(posedge clk_fpga)
-     if(rxsync_0)
-       begin
-	  rx_i <= rx_b;
-	  rx_q <= rx_a;
-       end
-     else
-       begin
-	  rx_i <= rx_a;
-	  rx_q <= rx_b;
-       end
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Main U1E Core
-   u1plus_core u1p_c(.clk_fpga(clk_fpga), .rst_fpga(reset),
-		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
-		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
-		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
-		     .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}),
-		     .gpif_clk(IFCLK),
-
-		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
-		     .sclk(sclk), .sen({SEN_CODEC,SEN_TX_DB,SEN_RX_DB}), .mosi(mosi), .miso(miso),
-		     .cgen_st_status(cgen_st_status), .cgen_st_ld(cgen_st_ld),.cgen_st_refmon(cgen_st_refmon), 
-		     .cgen_sync_b(cgen_sync_b), .cgen_ref_sel(cgen_ref_sel),
-		     .io_tx(io_tx), .io_rx(io_rx),
-		     .tx_i(tx_i), .tx_q(tx_q), 
-		     .rx_i(rx_i), .rx_q(rx_q),
-		     .pps_in(PPS_IN) );
-
-endmodule // u1plus
diff --git a/fpga/usrp2/top/B100/u1plus_core.v b/fpga/usrp2/top/B100/u1plus_core.v
index e5af189cc..691ad1f75 100644
--- a/fpga/usrp2/top/B100/u1plus_core.v
+++ b/fpga/usrp2/top/B100/u1plus_core.v
@@ -18,435 +18,332 @@
 
 
 module u1plus_core
-  (input clk_fpga, input rst_fpga,
-   output [2:0] debug_led, output [31:0] debug, output [1:0] debug_clk,
-   output debug_txd, input debug_rxd,
-   
-   // GPIF
-   inout [15:0] gpif_d, input [3:0] gpif_ctl, output gpif_sloe,
-   output gpif_slwr, output gpif_slrd, output gpif_pktend, output [1:0] gpif_fifoadr,
-   input gpif_clk,
-   
+#(
+    parameter NUM_RX_DSPS = 2,
+    parameter CTRL_ACK_SID = 20,      //needed for reply
+
+    parameter DSP_TX_FIFOSIZE = 10,     //4K MTU
+    parameter DSP_RX_FIFOSIZE = 10,     //4K MTU
+
+    parameter DSP_RX_XTRA_FIFOSIZE = 11,
+    parameter DSP_TX_XTRA_FIFOSIZE = 11,
+
+    parameter USE_PACKET_PADDER = 0
+)
+  (input clk, input reset,
+   output [31:0] debug, output [1:0] debug_clk,
+
+   // Host Interface
+   input [35:0] tx_data, input tx_src_rdy, output tx_dst_rdy,
+   output [35:0] rx_data, output rx_src_rdy, input rx_dst_rdy,
+   input [35:0] ctrl_data, input ctrl_src_rdy, output ctrl_dst_rdy,
+   output [35:0] resp_data, output resp_src_rdy, input resp_dst_rdy,
+
+   output dsp_rx_run, output dsp_tx_run, output clock_sync,
+
    inout db_sda, inout db_scl,
-   output sclk, output [15:0] sen, output mosi, input miso,
+   output sclk, output [7:0] sen, output mosi, input miso,
 
-   input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel,   
-   inout [15:0] io_tx, inout [15:0] io_rx, 
-   output [13:0] tx_i, output [13:0] tx_q, 
-   input [11:0] rx_i, input [11:0] rx_q, 
+   inout [15:0] io_tx, inout [15:0] io_rx,
+   output [13:0] tx_i, output [13:0] tx_q,
+   input [11:0] rx_i, input [11:0] rx_q,
    input pps_in
    );
 
-   localparam TXFIFOSIZE = 11;
-   localparam RXFIFOSIZE = 12;
-
-   // 64 total regs in address space
-   localparam SR_RX_CTRL0 = 0;       // 9 regs (+0 to +8)
-   localparam SR_RX_DSP0 = 10;       // 4 regs (+0 to +3)
-   localparam SR_RX_CTRL1 = 16;      // 9 regs (+0 to +8)
-   localparam SR_RX_DSP1 = 26;       // 4 regs (+0 to +3)
-   localparam SR_TX_CTRL = 32;       // 4 regs (+0 to +3)
-   localparam SR_TX_DSP = 38;        // 3 regs (+0 to +2)
-
-   localparam SR_TIME64 = 42;        // 6 regs (+0 to +5)
-   localparam SR_RX_FRONT = 48;      // 5 regs (+0 to +4)
-   localparam SR_TX_FRONT = 54;      // 5 regs (+0 to +4)
-
-   localparam SR_REG_TEST32 = 60;    // 1 reg
-   localparam SR_CLEAR_FIFO = 61;    // 1 reg
-   localparam SR_GLOBAL_RESET = 63;  // 1 reg
-   localparam SR_USER_REGS = 64;     // 2 regs
-
-   localparam SR_GPIO = 128;         // 5 regs
-   
-   wire 	wb_clk = clk_fpga;
-   wire 	wb_rst, global_reset;
-
-   wire 	pps_int;
-   wire [63:0] 	vita_time, vita_time_pps;
-   reg [15:0] 	reg_cgen_ctrl, reg_test;
-
-   wire [7:0]  set_addr, set_addr_user;
-   wire [31:0] set_data, set_data_user;
-   wire        set_stb, set_stb_user;
-
-   wire [31:0]  debug0;
-   wire [31:0]  debug1;
-
-   wire [31:0] 	debug_vt;
-   wire 	gpif_rst;
-   
-   reg [7:0] 	frames_per_packet;
-   
-   wire 	rx_overrun_dsp0, rx_overrun_dsp1, rx_overrun_gpif, tx_underrun_dsp, tx_underrun_gpif;
-   wire 	rx_overrun = rx_overrun_gpif | rx_overrun_dsp0 | rx_overrun_dsp1;
-   wire 	tx_underrun = tx_underrun_gpif | tx_underrun_dsp;
-   
-   setting_reg #(.my_addr(SR_GLOBAL_RESET), .width(1)) sr_reset
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(global_reset));
-
-   reset_sync reset_sync_wb(.clk(wb_clk), .reset_in(rst_fpga | global_reset), .reset_out(wb_rst));
-   reset_sync reset_sync_gp(.clk(gpif_clk), .reset_in(rst_fpga | global_reset), .reset_out(gpif_rst));
-   
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // GPIF Slave to Wishbone Master
-   localparam dw = 16;
-   localparam aw = 11;
-   localparam sw = 2;
-   
-   wire [dw-1:0] m0_dat_mosi, m0_dat_miso;
-   wire [aw-1:0] m0_adr;
-   wire [sw-1:0] m0_sel;
-   wire 	 m0_cyc, m0_stb, m0_we, m0_ack, m0_err, m0_rty;
-
-   wire [31:0] 	 debug_gpif;
-
-   wire [35:0] 	 tx_data, rx_data, tx_err_data;
-   wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
-		 tx_err_src_rdy, tx_err_dst_rdy;
-
-   wire 	 clear_fifo;
-
-   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(1)) sr_clear_fifo
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_fifo));
-
-   wire 	 run_rx0, run_rx1;
-
-   slave_fifo #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
-   slave_fifo (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), .gpif_d(gpif_d),
-	 .gpif_ctl(gpif_ctl), .sloe(gpif_sloe), .slwr(gpif_slwr), .slrd(gpif_slrd),
-     .pktend(gpif_pktend), .fifoadr(gpif_fifoadr),
-	 
-	 .wb_clk(wb_clk), .wb_rst(wb_rst),
-	 .wb_adr_o(m0_adr), .wb_dat_mosi(m0_dat_mosi), .wb_dat_miso(m0_dat_miso),
-	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
-	 .wb_ack_i(m0_ack), .triggers(8'd0),
-	 
-	 .dsp_rx_run(run_rx0 | run_rx1),
-	 
-	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_fifo), .clear_rx(clear_fifo),
-	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
-	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
-	 .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy),
-	 
-	 .tx_underrun(tx_underrun_gpif), .rx_overrun(rx_overrun_gpif),
-
-	 .test_len(0), .test_rate(0), .test_ctrl(0),
-	 .debug0(debug0), .debug1(debug1));
+    localparam SR_MISC         = 0;      // 5
+    localparam SR_USER_REGS    = 5;      // 2
+    localparam SR_PADDER       = 10;     // 2
+
+    localparam SR_TX_CTRL      = 32;     // 6
+    localparam SR_TX_DSP       = 40;     // 5
+    localparam SR_TX_FE        = 48;     // 5
+
+    localparam SR_RX_CTRL0     = 96;      // 9
+    localparam SR_RX_DSP0      = 106;     // 7
+    localparam SR_RX_FE        = 114;     // 5
+
+    localparam SR_RX_CTRL1     = 128;     // 9
+    localparam SR_RX_DSP1      = 138;     // 7
+
+    localparam SR_TIME64       = 192;     // 6
+    localparam SR_SPI          = 208;     // 3
+    localparam SR_I2C          = 216;     // 1
+    localparam SR_GPIO         = 224;     // 5
+
+    //compatibility number -> increment when the fpga has been sufficiently altered
+    localparam compat_num = {16'd11, 16'd0}; //major, minor
+
+    //assign run signals used for ATR logic
+    wire [NUM_RX_DSPS-1:0] run_rx_n;
+    wire run_tx;
+    wire run_rx = |(run_rx_n);
+    assign dsp_rx_run = run_rx;
+    assign dsp_tx_run = run_tx;
+
+    //shared time core signals
+    wire [63:0] vita_time, vita_time_pps;
+
+    //shared settings bus signals
+    wire set_stb, set_stb_user;
+    wire [31:0] set_data, set_data_user;
+    wire [7:0] set_addr, set_addr_user;
+
+    //shared SPI core signals
+    wire [31:0] spi_readback;
+    wire spi_ready;
+
+    //shared I2C core signals
+    wire [31:0] i2c_readback;
+    wire i2c_ready;
+
+    //shared GPIO core signals
+    wire [31:0] gpio_readback;
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Misc Registers - persistent across resets
+    ///////////////////////////////////////////////////////////////////////////
+    wire [31:0] config_word0;
+    setting_reg #(.my_addr(SR_MISC+0), .width(32)) sr_misc_config0
+     (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word0));
+    wire [31:0] config_word1;
+    setting_reg #(.my_addr(SR_MISC+1), .width(32)) sr_misc_config1
+     (.clk(clk), .rst(1'b0/*reset*/), .strobe(set_stb), .addr(set_addr), .in(set_data), .out(config_word1));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Settings Bus and Readback
+    ///////////////////////////////////////////////////////////////////////////
+    user_settings #(.BASE(SR_USER_REGS)) user_settings
+     (.clk(clk),.rst(reset),
+      .set_stb(set_stb), .set_addr(set_addr),.set_data(set_data),
+      .set_addr_user(set_addr_user),.set_data_user(set_data_user), .set_stb_user(set_stb_user) );
+
+    wire [35:0] ctrl_out_data, ctrl_int_data;
+    wire ctrl_out_src_rdy, ctrl_out_dst_rdy;
+    wire ctrl_int_src_rdy, ctrl_int_dst_rdy;
+
+    fifo_cascade #(.WIDTH(36), .SIZE(9)) ctrl_fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .datain(ctrl_data), .src_rdy_i(ctrl_src_rdy), .dst_rdy_o(ctrl_dst_rdy), .space(),
+      .dataout(ctrl_int_data), .src_rdy_o(ctrl_int_src_rdy), .dst_rdy_i(ctrl_int_dst_rdy), .occupied());
+
+    wire [31:0] num_rx_dsps_rb = NUM_RX_DSPS;
+
+    wire [31:0] sfc_debug;
+    settings_fifo_ctrl #(.PROT_HDR(0), .ACK_SID(CTRL_ACK_SID), .XPORT_HDR(0)) sfc
+    (
+        .clock(clk), .reset(reset), .clear(1'b0),
+        .vita_time(vita_time), .perfs_ready(spi_ready & i2c_ready),
+        .in_data(ctrl_int_data), .in_valid(ctrl_int_src_rdy), .in_ready(ctrl_int_dst_rdy),
+        .out_data(ctrl_out_data), .out_valid(ctrl_out_src_rdy), .out_ready(ctrl_out_dst_rdy),
+        .strobe(set_stb), .addr(set_addr), .data(set_data),
+        .word00(spi_readback),.word01(compat_num),.word02(i2c_readback),.word03(gpio_readback),
+        .word04(config_word0),.word05(config_word1),.word06(num_rx_dsps_rb),.word07(32'hffff_ffff),
+        .word08(32'hffff_ffff),.word09(32'hffff_ffff),.word10(vita_time[63:32]),
+        .word11(vita_time[31:0]),.word12(32'hffff_ffff),.word13(32'hffff_ffff),
+        .word14(vita_time_pps[63:32]),.word15(vita_time_pps[31:0]),
+        .debug(sfc_debug)
+    );
+
+    ///////////////////////////////////////////////////////////////////////////
+    // Time Core
+    ///////////////////////////////////////////////////////////////////////////
+    time_64bit #(.BASE(SR_TIME64)) time_64bit
+     (.clk(clk), .rst(reset), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps),
+      .exp_time_in(0));
+    assign clock_sync = 1'b0;
+
+    ///////////////////////////////////////////////////////////////////////////
+    // SPI Core
+    ///////////////////////////////////////////////////////////////////////////
+    simple_spi_core #(.BASE(SR_SPI), .WIDTH(8), .CLK_IDLE(0), .SEN_IDLE(8'hff))
+    simple_spi_core (.clock(clk), .reset(reset),
+        .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+        .readback(spi_readback), .ready(spi_ready),
+        .sen(sen), .sclk(sclk), .mosi(mosi), .miso(miso));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // I2C Core
+    ///////////////////////////////////////////////////////////////////////////
+    wire scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
+    simple_i2c_core #(.BASE(SR_I2C)) i2c_core
+     (.clock(clk),.reset(reset),
+      .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
+      .readback(i2c_readback), .ready(i2c_ready),
+      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
+      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
+
+    // I2C -- Don't use external transistors for open drain, the FPGA implements this
+    IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
+    IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
+
+    ///////////////////////////////////////////////////////////////////////////
+    // GPIO Core
+    ///////////////////////////////////////////////////////////////////////////
+    gpio_atr #(.BASE(SR_GPIO), .WIDTH(32))
+    gpio_atr(.clk(clk),.reset(reset),
+        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+        .rx(run_rx), .tx(run_tx), .gpio({io_tx, io_rx}), .gpio_readback(gpio_readback) );
 
    // /////////////////////////////////////////////////////////////////////////
    // RX ADC Frontend, does IQ Balance, DC Offset, muxing
 
    wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
 
-   rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
-     (.clk(wb_clk),.rst(wb_rst),
+   rx_frontend #(.BASE(SR_RX_FE)) rx_frontend
+     (.clk(clk),.rst(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_a({rx_i,4'b00}),.adc_ovf_a(0),
       .adc_b({rx_q,4'b00}),.adc_ovf_b(0),
-      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx0 | run_rx1), .debug());
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // DSP RX 0
-
-   wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0, clear_rx0;
-   wire [35:0] 	 vita_rx_data0;
-   wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
-   
-   ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(wb_clk), .rst(wb_rst), .clr(clear_rx0),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
-      .debug() );
+      .i_out(rx_fe_i), .q_out(rx_fe_q), .run(run_rx), .debug());
 
-   vita_rx_chain #(.BASE(SR_RX_CTRL0), .UNIT(0), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(0)) vita_rx_chain0
-     (.clk(wb_clk),.reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time), .overrun(rx_overrun_dsp0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
-      .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
-      .debug() );
-   
    // /////////////////////////////////////////////////////////////////////////
-   // DSP RX 1
-
-   wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1, clear_rx1;
-   wire [35:0] 	 vita_rx_data1;
-   wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
-   
-   ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(wb_clk),.rst(wb_rst), .clr(clear_rx1),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
-      .debug() );
-
-   vita_rx_chain #(.BASE(SR_RX_CTRL1), .UNIT(1), .FIFOSIZE(10), .PROT_ENG_FLAGS(0), .DSP_NUMBER(1)) vita_rx_chain1
-     (.clk(wb_clk),.reset(wb_rst),
-      .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-      .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
-      .vita_time(vita_time), .overrun(rx_overrun_dsp1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
-      .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
-      .debug() );
+   // DSP RX *
+
+    wire [35:0] rx_int2_data [NUM_RX_DSPS-1:0];
+    wire rx_int2_src_rdy [NUM_RX_DSPS-1:0];
+    wire rx_int2_dst_rdy [NUM_RX_DSPS-1:0];
+
+    genvar dspno;
+    generate
+    for(dspno = 0; dspno < NUM_RX_DSPS; dspno = dspno + 1) begin:gen_rx_dsps
+
+        wire [31:0] sample_rx;
+        wire strobe_rx, clear_rx;
+        wire [35:0] vita_rx_data;
+        wire vita_rx_src_rdy, vita_rx_dst_rdy;
+        wire [35:0] int_rx_data;
+        wire int_rx_src_rdy, int_rx_dst_rdy;
+
+       ddc_chain #(.BASE(SR_RX_DSP0+dspno*32), .DSPNO(dspno)) ddc_chain
+         (.clk(clk), .rst(reset), .clr(clear_rx),
+          .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+          .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
+          .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx),
+          .debug() );
+
+        vita_rx_chain #(.BASE(SR_RX_CTRL0+dspno*32), .UNIT(dspno), .FIFOSIZE(DSP_RX_FIFOSIZE), .PROT_ENG_FLAGS(0), .DSP_NUMBER(dspno)) vita_rx_chain
+         (.clk(clk),.reset(reset),
+          .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+          .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
+          .vita_time(vita_time), .overrun(),
+          .sample(sample_rx), .run(run_rx_n[dspno]), .strobe(strobe_rx), .clear_o(clear_rx),
+          .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy),
+          .debug() );
+
+        fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE+1)) rx_data_fifo
+         (.clk(clk), .reset(reset), .clear(1'b0),
+          .datain(vita_rx_data), .src_rdy_i(vita_rx_src_rdy), .dst_rdy_o(vita_rx_dst_rdy), .space(),
+          .dataout(int_rx_data), .src_rdy_o(int_rx_src_rdy), .dst_rdy_i(int_rx_dst_rdy), .occupied());
+
+        if (dspno == 0) begin
+            assign rx_int2_data[dspno] = int_rx_data;
+            assign rx_int2_src_rdy[dspno] = int_rx_src_rdy;
+            assign int_rx_dst_rdy = rx_int2_dst_rdy[dspno];
+        end
+        else begin
+            fifo36_mux #(.prio(0)) // No priority, fair sharing
+            combine_rx_dsps (
+                .clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
+                .data0_i(rx_int2_data[dspno-1]), .src0_rdy_i(rx_int2_src_rdy[dspno-1]), .dst0_rdy_o(rx_int2_dst_rdy[dspno-1]),
+                .data1_i(int_rx_data), .src1_rdy_i(int_rx_src_rdy), .dst1_rdy_o(int_rx_dst_rdy),
+                .data_o(rx_int2_data[dspno]), .src_rdy_o(rx_int2_src_rdy[dspno]), .dst_rdy_i(rx_int2_dst_rdy[dspno])
+            );
+        end
+
+    end
+    endgenerate
 
    // /////////////////////////////////////////////////////////////////////////
    // RX Stream muxing
 
-   fifo36_mux #(.prio(0)) mux_data_streams
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_fifo),
-      .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
-      .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
-      .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+    wire [35:0] rx_int3_data;
+    wire rx_int3_src_rdy, rx_int3_dst_rdy;
+
+    fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_XTRA_FIFOSIZE)) rx_data_fifo_combined
+         (.clk(clk), .reset(reset), .clear(1'b0),
+          .datain(rx_int2_data[NUM_RX_DSPS-1]), .src_rdy_i(rx_int2_src_rdy[NUM_RX_DSPS-1]), .dst_rdy_o(rx_int2_dst_rdy[NUM_RX_DSPS-1]), .space(),
+          .dataout(rx_int3_data), .src_rdy_o(rx_int3_src_rdy), .dst_rdy_i(rx_int3_dst_rdy), .occupied());
+
+    generate
+    if (USE_PACKET_PADDER) begin
+    packet_padder36 #(.BASE(SR_PADDER)) packet_padder_rx_data36(
+        .clk(clk), .reset(reset),
+        .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+        .data_i(rx_int3_data), .src_rdy_i(rx_int3_src_rdy), .dst_rdy_o(rx_int3_dst_rdy),
+        .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy),
+        .always_flush(~dsp_rx_run));
+    end
+    else begin
+        assign rx_data = rx_int3_data;
+        assign rx_src_rdy = rx_int3_src_rdy;
+        assign rx_int3_dst_rdy = rx_dst_rdy;
+    end
+    endgenerate
+
+    ///////////////////////////////////////////////////////////////////////////
+    // MUX for TX async and resp data
+    ///////////////////////////////////////////////////////////////////////////
+    wire [35:0] tx_err_data, resp_data_int;
+    wire tx_err_src_rdy, resp_src_rdy_int;
+    wire tx_err_dst_rdy, resp_dst_rdy_int;
+
+    fifo36_mux #(.prio(0)) // No priority, fair sharing
+    combine_async_and_resp (
+        .clk(clk), .reset(reset), .clear(1'b0/*noclear*/),
+        .data0_i(ctrl_out_data), .src0_rdy_i(ctrl_out_src_rdy), .dst0_rdy_o(ctrl_out_dst_rdy),
+        .data1_i(tx_err_data), .src1_rdy_i(tx_err_src_rdy), .dst1_rdy_o(tx_err_dst_rdy),
+        .data_o(resp_data_int), .src_rdy_o(resp_src_rdy_int), .dst_rdy_i(resp_dst_rdy_int)
+    );
+
+    fifo_cascade #(.WIDTH(36), .SIZE(9)) resp_fifo
+     (.clk(clk), .reset(reset), .clear(1'b0),
+      .datain(resp_data_int), .src_rdy_i(resp_src_rdy_int), .dst_rdy_o(resp_dst_rdy_int), .space(),
+      .dataout(resp_data), .src_rdy_o(resp_src_rdy), .dst_rdy_i(resp_dst_rdy), .occupied());
 
    // ///////////////////////////////////////////////////////////////////////////////////
    // DSP TX
 
-   wire 	 run_tx;
    wire [23:0] 	 tx_fe_i, tx_fe_q;
    wire [31:0]   sample_tx;
    wire strobe_tx, clear_tx;
 
-   vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
+   vita_tx_chain #(.BASE(SR_TX_CTRL),
+		   .FIFOSIZE(DSP_TX_FIFOSIZE),
+		   .POST_ENGINE_FIFOSIZE(DSP_TX_XTRA_FIFOSIZE),
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
 		   .PROT_ENG_FLAGS(0), .USE_TRANS_HEADER(0),
-		   .DSP_NUMBER(0)) 
+		   .DSP_NUMBER(0))
    vita_tx_chain
-     (.clk(wb_clk), .reset(wb_rst),
+     (.clk(clk), .reset(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time),
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(tx_underrun_dsp), .run(run_tx), .clear_o(clear_tx),
-      .debug(debug_vt));
+      .underrun(), .run(run_tx), .clear_o(clear_tx),
+      .debug());
 
    duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(wb_clk), .rst(wb_rst), .clr(clear_tx),
+     (.clk(clk), .rst(reset), .clr(clear_tx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
       .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
       .debug() );
 
-   tx_frontend #(.BASE(SR_TX_FRONT), .WIDTH_OUT(14)) tx_frontend
-     (.clk(wb_clk), .rst(wb_rst),
+   tx_frontend #(.BASE(SR_TX_FE), .WIDTH_OUT(14)) tx_frontend
+     (.clk(clk), .rst(reset),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .tx_i(tx_fe_i), .tx_q(tx_fe_q), .run(1'b1),
       .dac_a(tx_i), .dac_b(tx_q));
 
    // /////////////////////////////////////////////////////////////////////////////////////
-   // Wishbone Intercon, single master
-   wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,
-		 s4_dat_mosi, s5_dat_mosi, s4_dat_miso, s5_dat_miso, s6_dat_mosi, s7_dat_mosi, s6_dat_miso, s7_dat_miso,
-		 s8_dat_mosi, s9_dat_mosi, s8_dat_miso, s9_dat_miso, sa_dat_mosi, sb_dat_mosi, sa_dat_miso, sb_dat_miso,
-		 sc_dat_mosi, sd_dat_mosi, sc_dat_miso, sd_dat_miso, se_dat_mosi, sf_dat_mosi, se_dat_miso, sf_dat_miso;
-   wire [aw-1:0] s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr;
-   wire [aw-1:0] s8_adr,s9_adr,sa_adr,sb_adr,sc_adr, sd_adr, se_adr, sf_adr;
-   wire [sw-1:0] s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel;
-   wire [sw-1:0] s8_sel,s9_sel,sa_sel,sb_sel,sc_sel, sd_sel, se_sel, sf_sel;
-   wire 	 s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack;
-   wire 	 s8_ack,s9_ack,sa_ack,sb_ack,sc_ack, sd_ack, se_ack, sf_ack;
-   wire 	 s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb;
-   wire 	 s8_stb,s9_stb,sa_stb,sb_stb,sc_stb, sd_stb, se_stb, sf_stb;
-   wire 	 s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc;
-   wire 	 s8_cyc,s9_cyc,sa_cyc,sb_cyc,sc_cyc, sd_cyc, se_cyc, sf_cyc;
-   wire 	 s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we;
-   wire 	 s8_we,s9_we,sa_we,sb_we,sc_we,sd_we, se_we, sf_we;
-   
-   wb_1master #(.dw(dw), .aw(aw), .sw(sw), .decode_w(4),
-		.s0_addr(4'h0), .s0_mask(4'hF), // Misc Regs
-		.s1_addr(4'h1), .s1_mask(4'hF), // Unused
-		.s2_addr(4'h2), .s2_mask(4'hF),	// SPI
-		.s3_addr(4'h3), .s3_mask(4'hF), // I2C
-		.s4_addr(4'h4), .s4_mask(4'hF),	// Unused
-		.s5_addr(4'h5), .s5_mask(4'hF), // Unused on B1x0, Async Msg on E1x0
-		.s6_addr(4'h6), .s6_mask(4'hF),	// Unused
-		.s7_addr(4'h7), .s7_mask(4'hF), // Readback MUX
-		.s8_addr(4'h8), .s8_mask(4'h8), // Setting Regs -- slave 8 is 8 slaves wide
-		// slaves 9-f alias to slave 1, all are unused
-		.s9_addr(4'h1), .s9_mask(4'hF),
-		.sa_addr(4'h1), .sa_mask(4'hF),	.sb_addr(4'h1), .sb_mask(4'hF),
-		.sc_addr(4'h1), .sc_mask(4'hF),	.sd_addr(4'h1), .sd_mask(4'hF),
-		.se_addr(4'h1), .se_mask(4'hF),	.sf_addr(4'h1), .sf_mask(4'hF))
-   wb_1master
-     (.clk_i(wb_clk),.rst_i(wb_rst),       
-      .m0_dat_o(m0_dat_miso),.m0_ack_o(m0_ack),.m0_err_o(m0_err),.m0_rty_o(m0_rty),.m0_dat_i(m0_dat_mosi),
-      .m0_adr_i(m0_adr),.m0_sel_i(m0_sel),.m0_we_i(m0_we),.m0_cyc_i(m0_cyc),.m0_stb_i(m0_stb),
-      .s0_dat_o(s0_dat_mosi),.s0_adr_o(s0_adr),.s0_sel_o(s0_sel),.s0_we_o(s0_we),.s0_cyc_o(s0_cyc),.s0_stb_o(s0_stb),
-      .s0_dat_i(s0_dat_miso),.s0_ack_i(s0_ack),.s0_err_i(0),.s0_rty_i(0),
-      .s1_dat_o(s1_dat_mosi),.s1_adr_o(s1_adr),.s1_sel_o(s1_sel),.s1_we_o(s1_we),.s1_cyc_o(s1_cyc),.s1_stb_o(s1_stb),
-      .s1_dat_i(s1_dat_miso),.s1_ack_i(s1_ack),.s1_err_i(0),.s1_rty_i(0),
-      .s2_dat_o(s2_dat_mosi),.s2_adr_o(s2_adr),.s2_sel_o(s2_sel),.s2_we_o(s2_we),.s2_cyc_o(s2_cyc),.s2_stb_o(s2_stb),
-      .s2_dat_i(s2_dat_miso),.s2_ack_i(s2_ack),.s2_err_i(0),.s2_rty_i(0),
-      .s3_dat_o(s3_dat_mosi),.s3_adr_o(s3_adr),.s3_sel_o(s3_sel),.s3_we_o(s3_we),.s3_cyc_o(s3_cyc),.s3_stb_o(s3_stb),
-      .s3_dat_i(s3_dat_miso),.s3_ack_i(s3_ack),.s3_err_i(0),.s3_rty_i(0),
-      .s4_dat_o(s4_dat_mosi),.s4_adr_o(s4_adr),.s4_sel_o(s4_sel),.s4_we_o(s4_we),.s4_cyc_o(s4_cyc),.s4_stb_o(s4_stb),
-      .s4_dat_i(s4_dat_miso),.s4_ack_i(s4_ack),.s4_err_i(0),.s4_rty_i(0),
-      .s5_dat_o(s5_dat_mosi),.s5_adr_o(s5_adr),.s5_sel_o(s5_sel),.s5_we_o(s5_we),.s5_cyc_o(s5_cyc),.s5_stb_o(s5_stb),
-      .s5_dat_i(s5_dat_miso),.s5_ack_i(s5_ack),.s5_err_i(0),.s5_rty_i(0),
-      .s6_dat_o(s6_dat_mosi),.s6_adr_o(s6_adr),.s6_sel_o(s6_sel),.s6_we_o(s6_we),.s6_cyc_o(s6_cyc),.s6_stb_o(s6_stb),
-      .s6_dat_i(s6_dat_miso),.s6_ack_i(s6_ack),.s6_err_i(0),.s6_rty_i(0),
-      .s7_dat_o(s7_dat_mosi),.s7_adr_o(s7_adr),.s7_sel_o(s7_sel),.s7_we_o(s7_we),.s7_cyc_o(s7_cyc),.s7_stb_o(s7_stb),
-      .s7_dat_i(s7_dat_miso),.s7_ack_i(s7_ack),.s7_err_i(0),.s7_rty_i(0),
-      .s8_dat_o(s8_dat_mosi),.s8_adr_o(s8_adr),.s8_sel_o(s8_sel),.s8_we_o(s8_we),.s8_cyc_o(s8_cyc),.s8_stb_o(s8_stb),
-      .s8_dat_i(s8_dat_miso),.s8_ack_i(s8_ack),.s8_err_i(0),.s8_rty_i(0),
-      .s9_dat_o(s9_dat_mosi),.s9_adr_o(s9_adr),.s9_sel_o(s9_sel),.s9_we_o(s9_we),.s9_cyc_o(s9_cyc),.s9_stb_o(s9_stb),
-      .s9_dat_i(s9_dat_miso),.s9_ack_i(s9_ack),.s9_err_i(0),.s9_rty_i(0),
-      .sa_dat_o(sa_dat_mosi),.sa_adr_o(sa_adr),.sa_sel_o(sa_sel),.sa_we_o(sa_we),.sa_cyc_o(sa_cyc),.sa_stb_o(sa_stb),
-      .sa_dat_i(sa_dat_miso),.sa_ack_i(sa_ack),.sa_err_i(0),.sa_rty_i(0),
-      .sb_dat_o(sb_dat_mosi),.sb_adr_o(sb_adr),.sb_sel_o(sb_sel),.sb_we_o(sb_we),.sb_cyc_o(sb_cyc),.sb_stb_o(sb_stb),
-      .sb_dat_i(sb_dat_miso),.sb_ack_i(sb_ack),.sb_err_i(0),.sb_rty_i(0),
-      .sc_dat_o(sc_dat_mosi),.sc_adr_o(sc_adr),.sc_sel_o(sc_sel),.sc_we_o(sc_we),.sc_cyc_o(sc_cyc),.sc_stb_o(sc_stb),
-      .sc_dat_i(sc_dat_miso),.sc_ack_i(sc_ack),.sc_err_i(0),.sc_rty_i(0),
-      .sd_dat_o(sd_dat_mosi),.sd_adr_o(sd_adr),.sd_sel_o(sd_sel),.sd_we_o(sd_we),.sd_cyc_o(sd_cyc),.sd_stb_o(sd_stb),
-      .sd_dat_i(sd_dat_miso),.sd_ack_i(sd_ack),.sd_err_i(0),.sd_rty_i(0),
-      .se_dat_o(se_dat_mosi),.se_adr_o(se_adr),.se_sel_o(se_sel),.se_we_o(se_we),.se_cyc_o(se_cyc),.se_stb_o(se_stb),
-      .se_dat_i(se_dat_miso),.se_ack_i(se_ack),.se_err_i(0),.se_rty_i(0),
-      .sf_dat_o(sf_dat_mosi),.sf_adr_o(sf_adr),.sf_sel_o(sf_sel),.sf_we_o(sf_we),.sf_cyc_o(sf_cyc),.sf_stb_o(sf_stb),
-      .sf_dat_i(sf_dat_miso),.sf_ack_i(sf_ack),.sf_err_i(0),.sf_rty_i(0) );
-
-   assign s1_ack = 0;   assign s4_ack = 0;   assign s5_ack = 0;   assign s6_ack = 0;
-   assign s9_ack = 0;   assign sa_ack = 0;   assign sb_ack = 0;
-   assign sc_ack = 0;   assign sd_ack = 0;   assign se_ack = 0;   assign sf_ack = 0;
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Slave 0, Misc LEDs, Switches, controls
-   
-   localparam REG_CGEN_CTRL = 7'd4;    // out
-   localparam REG_CGEN_ST = 7'd6;      // in
-   localparam REG_TEST = 7'd8;         // out
-   localparam REG_RX_FRAMELEN = 7'd10; // in
-   localparam REG_TX_FRAMELEN = 7'd12; // out
-   
-   always @(posedge wb_clk)
-     if(wb_rst)
-       begin
-	  reg_cgen_ctrl <= 2'b11;
-	  reg_test <= 0;
-	  frames_per_packet <= 0;
-       end
-     else
-       if(s0_cyc & s0_stb & s0_we) 
-	 case(s0_adr[6:0])
-	   REG_CGEN_CTRL :
-	     reg_cgen_ctrl <= s0_dat_mosi;
-	   REG_TEST :
-	     reg_test <= s0_dat_mosi;
-	   REG_RX_FRAMELEN :
-	     frames_per_packet <= s0_dat_mosi[7:0];
-	 endcase // case (s0_adr[6:0])
-
-   assign debug_led = {run_tx, (run_rx0 | run_rx1), cgen_st_ld};
-   assign { cgen_sync_b, cgen_ref_sel } = reg_cgen_ctrl;
-   
-   assign s0_dat_miso = (s0_adr[6:0] == REG_CGEN_CTRL) ? reg_cgen_ctrl :
-			(s0_adr[6:0] == REG_CGEN_ST) ? {13'b0,cgen_st_status,cgen_st_ld,cgen_st_refmon} :
-			(s0_adr[6:0] == REG_TEST) ? reg_test :
-			16'hBEEF;
-   
-   assign s0_ack = s0_stb & s0_cyc;
-
-   // /////////////////////////////////////////////////////////////////////////////////////
-   // Slave 2, SPI
-
-   spi_top16 shared_spi
-     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.wb_adr_i(s2_adr[4:0]),.wb_dat_i(s2_dat_mosi),
-      .wb_dat_o(s2_dat_miso),.wb_sel_i(s2_sel),.wb_we_i(s2_we),.wb_stb_i(s2_stb),
-      .wb_cyc_i(s2_cyc),.wb_ack_o(s2_ack),.wb_err_o(),.wb_int_o(),
-      .ss_pad_o(sen), .sclk_pad_o(sclk), .mosi_pad_o(mosi), .miso_pad_i(miso) );
-   
-   // /////////////////////////////////////////////////////////////////////////
-   // Slave 3, I2C
-
-   wire 	scl_pad_i, scl_pad_o, scl_pad_oen_o, sda_pad_i, sda_pad_o, sda_pad_oen_o;
-   i2c_master_top #(.ARST_LVL(1)) i2c 
-     (.wb_clk_i(wb_clk),.wb_rst_i(wb_rst),.arst_i(1'b0), 
-      .wb_adr_i(s3_adr[3:1]),.wb_dat_i(s3_dat_mosi[7:0]),.wb_dat_o(s3_dat_miso[7:0]),
-      .wb_we_i(s3_we),.wb_stb_i(s3_stb),.wb_cyc_i(s3_cyc),
-      .wb_ack_o(s3_ack),.wb_inta_o(),
-      .scl_pad_i(scl_pad_i),.scl_pad_o(scl_pad_o),.scl_padoen_o(scl_pad_oen_o),
-      .sda_pad_i(sda_pad_i),.sda_pad_o(sda_pad_o),.sda_padoen_o(sda_pad_oen_o) );
-
-   assign 	 s3_dat_miso[15:8] = 8'd0;
-
-   // I2C -- Don't use external transistors for open drain, the FPGA implements this
-   IOBUF scl_pin(.O(scl_pad_i), .IO(db_scl), .I(scl_pad_o), .T(scl_pad_oen_o));
-   IOBUF sda_pin(.O(sda_pad_i), .IO(db_sda), .I(sda_pad_o), .T(sda_pad_oen_o));
-
-   // /////////////////////////////////////////////////////////////////////////
-   // GPIOs
-
-   wire [31:0] gpio_readback;
-   
-   gpio_atr #(.BASE(SR_GPIO), .WIDTH(32)) 
-   gpio_atr(.clk(wb_clk),.reset(wb_rst),
-	    .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
-	    .rx(run_rx0 | run_rx1), .tx(run_tx),
-	    .gpio({io_tx,io_rx}), .gpio_readback(gpio_readback) );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Settings Bus -- Slave #8 + 9
-
-   // only have 64 regs, 32 bits each with current setup...
-   settings_bus_16LE #(.AWIDTH(11),.RWIDTH(8)) settings_bus_16LE
-     (.wb_clk(wb_clk),.wb_rst(wb_rst),.wb_adr_i(s8_adr),.wb_dat_i(s8_dat_mosi),
-      .wb_stb_i(s8_stb),.wb_we_i(s8_we),.wb_ack_o(s8_ack),
-      .strobe(set_stb),.addr(set_addr),.data(set_data) );
-
-   user_settings #(.BASE(SR_USER_REGS)) user_settings
-     (.clk(wb_clk),.rst(wb_rst),.set_stb(set_stb),
-      .set_addr(set_addr),.set_data(set_data),
-      .set_addr_user(set_addr_user),.set_data_user(set_data_user),
-      .set_stb_user(set_stb_user) );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // Readback mux 32 -- Slave #7
-
-   //compatibility number -> increment when the fpga has been sufficiently altered
-   localparam compat_num = {16'd10, 16'd0}; //major, minor
-
-   wire [31:0] reg_test32;
-
-   setting_reg #(.my_addr(SR_REG_TEST32)) sr_reg_test32
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(reg_test32),.changed());
-
-   wb_readback_mux_16LE readback_mux_32
-     (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb),
-      .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack),
-
-      .word00(vita_time[63:32]),        .word01(vita_time[31:0]),
-      .word02(vita_time_pps[63:32]),    .word03(vita_time_pps[31:0]),
-      .word04(reg_test32),              .word05(32'b0),
-      .word06(compat_num),              .word07(gpio_readback),
-      .word08(32'b0),                   .word09(32'b0),
-      .word10(32'b0),                   .word11(32'b0),
-      .word12(32'b0),                   .word13(32'b0),
-      .word14(32'b0),                   .word15(32'b0)
-      );
-
-   // /////////////////////////////////////////////////////////////////////////
-   // VITA Timing
-
-   time_64bit #(.BASE(SR_TIME64)) time_64bit
-     (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
-      .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int),
-      .exp_time_in(0));
-   
-   // /////////////////////////////////////////////////////////////////////////////////////
    // Debug circuitry
 
-   assign debug_clk = 2'b00; // { gpif_clk, clk_fpga };
-   assign debug = 0;
-   
+   assign debug_clk = 2'b11;
+   assign debug = 32'hffffffff;
+
 endmodule // u1plus_core