fifo_ctrl: clear settings reg, and flow control

3 files changed, 17 insertions, 10 deletions

diff --git a/usrp2/control_lib/settings_bus_crossclock.v b/usrp2/control_lib/settings_bus_crossclock.v
index 9c5912042..a61ee8fad 100644
--- a/usrp2/control_lib/settings_bus_crossclock.v
+++ b/usrp2/control_lib/settings_bus_crossclock.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
@@ -22,16 +22,17 @@
 // the system or dsp clock on the output side
 
 module settings_bus_crossclock
+  #(parameter FLOW_CTRL=0)
   (input clk_i, input rst_i, input set_stb_i, input [7:0] set_addr_i, input [31:0] set_data_i,
-   input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o);
+   input clk_o, input rst_o, output set_stb_o, output [7:0] set_addr_o, output [31:0] set_data_o, input blocked);
 
    wire  full, empty;
    
    fifo_xlnx_16x40_2clk settings_fifo
      (.rst(rst_i),
       .wr_clk(clk_i), .din({set_addr_i,set_data_i}), .wr_en(set_stb_i & ~full), .full(full),
-      .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(~empty), .empty(empty));
+      .rd_clk(clk_o), .dout({set_addr_o,set_data_o}), .rd_en(set_stb_o), .empty(empty));
 
-   assign set_stb_o = ~empty;
+   assign set_stb_o = ~empty & (~blocked | ~FLOW_CTRL);
 
 endmodule // settings_bus_crossclock
diff --git a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
index 89efd2203..24c618d79 100644
--- a/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
+++ b/usrp2/control_lib/settings_readback_bus_fifo_ctrl.v
@@ -251,7 +251,8 @@ module settings_readback_bus_fifo_ctrl
             end
 
             WAIT_CMD: begin
-                if (now || late) out_state <= ACTION_EVENT;
+                if (clear) out_state <= LOAD_CMD;
+                else if (now || late) out_state <= ACTION_EVENT;
             end
 
             ACTION_EVENT: begin // poking and peeking happens here!
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 6b915698a..27a5af833 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -488,12 +488,13 @@ module u2plus_core
 
    //mux settings_bus_crossclock and settings_readback_bus_fifo_ctrl with prio
    assign set_stb_dsp = set_stb_dsp0 | set_stb_dsp1;
-   assign set_addr_dsp = set_stb_dsp0? set_addr_dsp0 : set_addr_dsp1;
-   assign set_data_dsp = set_stb_dsp0? set_data_dsp0 : set_data_dsp1;
+   assign set_addr_dsp = set_stb_dsp1? set_addr_dsp1 : set_addr_dsp0;
+   assign set_data_dsp = set_stb_dsp1? set_data_dsp1 : set_data_dsp0;
 
-   settings_bus_crossclock settings_bus_crossclock
+   settings_bus_crossclock #(.FLOW_CTRL(1/*on*/)) settings_bus_crossclock
      (.clk_i(wb_clk), .rst_i(wb_rst), .set_stb_i(set_stb), .set_addr_i(set_addr), .set_data_i(set_data),
-      .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0));
+      .clk_o(dsp_clk), .rst_o(dsp_rst), .set_stb_o(set_stb_dsp0), .set_addr_o(set_addr_dsp0), .set_data_o(set_data_dsp0),
+      .blocked(set_stb_dsp1));
 
    user_settings #(.BASE(SR_USER_REGS)) user_settings
      (.clk(dsp_clk),.rst(dsp_rst),.set_stb(set_stb_dsp),
@@ -505,9 +506,10 @@ module u2plus_core
    // Settings + Readback Bus -- FIFO controlled
 
     wire [31:0] srb_debug;
+    wire srb_clear;
     settings_readback_bus_fifo_ctrl #(.PROT_DEST(3)) srb
     (
-        .clock(dsp_clk), .reset(dsp_rst), .clear(0),
+        .clock(dsp_clk), .reset(dsp_rst), .clear(srb_clear),
         .vita_time(vita_time),
         .in_data(srb_rd_data), .in_valid(srb_rd_valid), .in_ready(srb_rd_ready),
         .out_data(srb_wr_data), .out_valid(srb_wr_valid), .out_ready(srb_wr_ready),
@@ -520,6 +522,9 @@ module u2plus_core
         .debug(srb_debug)
     );
 
+    setting_reg #(.my_addr(SR_BUF_POOL+1/*same as packet dispatcher*/),.width(1)) sr_clear_srb
+     (.clk(dsp_clk),.rst(dsp_rst),.strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),.changed(srb_clear));
+
    // Output control lines
    wire [7:0] 	 clock_outs, serdes_outs, adc_outs;
    assign 	 {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];