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| author | Matt Ettus <matt@ettus.com> | 2010-08-25 19:00:02 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-08-25 19:00:02 -0700 |
| commit | 9e2e78642251ee9e024461becfd70a75b11d818a (patch) | |
| tree | 4dd389161082c2ca4add7137af4d8004e63ed2a4 | |
| parent | 2e526a8411f97654a2e87bdd1e524729da71315e (diff) | |
| download | uhd-9e2e78642251ee9e024461becfd70a75b11d818a.tar.gz uhd-9e2e78642251ee9e024461becfd70a75b11d818a.tar.bz2 uhd-9e2e78642251ee9e024461becfd70a75b11d818a.zip | |
SWAP DAC A and B, invert B to match schematics
| -rw-r--r-- | usrp2/top/u2plus/u2plus.v | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/usrp2/top/u2plus/u2plus.v b/usrp2/top/u2plus/u2plus.v index d330e336b..db31b4a68 100644 --- a/usrp2/top/u2plus/u2plus.v +++ b/usrp2/top/u2plus/u2plus.v @@ -298,10 +298,11 @@ module u2plus */ wire [15:0] dac_a_int, dac_b_int; + // DAC A and B are swapped in schematic to facilitate clean layout + // DAC A is also inverted in schematic to facilitate clean layout + always @(negedge dsp_clk) DACA <= ~dac_b_int; + always @(negedge dsp_clk) DACB <= dac_a_int; - always @(negedge dsp_clk) DACA <= dac_a_int; - always @(negedge dsp_clk) DACB <= dac_b_int; - u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), |