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| author | Matt Ettus <matt@ettus.com> | 2009-12-11 18:31:17 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-12-11 18:31:17 -0800 |
| commit | 5810c31b4ef73c97ea3ffb0a1ecccb254e141645 (patch) | |
| tree | 621b10785522a1ad7e73b37b1337a0f29c363a80 | |
| parent | 5f54616b4f8456a6dab879ebd8fc9bca287987b9 (diff) | |
| download | uhd-5810c31b4ef73c97ea3ffb0a1ecccb254e141645.tar.gz uhd-5810c31b4ef73c97ea3ffb0a1ecccb254e141645.tar.bz2 uhd-5810c31b4ef73c97ea3ffb0a1ecccb254e141645.zip | |
only pull from input fifo when really consuming or pushing into the next fifo
| -rw-r--r-- | vrt/vita_tx_deframer.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/vrt/vita_tx_deframer.v b/vrt/vita_tx_deframer.v index 470ba3f3e..a06d9ce2f 100644 --- a/vrt/vita_tx_deframer.v +++ b/vrt/vita_tx_deframer.v @@ -177,7 +177,7 @@ module vita_tx_deframer // sob, eob, has_secs (send_at) ignored on all lines except first assign fifo_i = {sample_d,sample_c,sample_b,sample_a,has_secs_reg,is_sob_reg,is_eob_reg,eop,send_time}; - assign dst_rdy_o = (vita_state != VITA_PAYLOAD); + assign dst_rdy_o = ~(vita_state == VITA_PAYLOAD) & ~((vita_state==VITA_STORE)& ~fifo_space) ; assign debug = { { 8'b0 }, { 8'b0 }, |