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author | Josh Blum <josh@joshknows.com> | 2012-10-05 14:11:42 -0700 |
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committer | Josh Blum <josh@joshknows.com> | 2012-10-05 14:11:42 -0700 |
commit | f83847318fa60bbc55c7dba2e2bfc01fb7ca2fdc (patch) | |
tree | 24cba2f04e272d91f5cd3b06a52cd7f3de2cf6f0 | |
parent | 8cfb73ed7d3b8b687509349ad6452886ce6d028b (diff) | |
download | uhd-f83847318fa60bbc55c7dba2e2bfc01fb7ca2fdc.tar.gz uhd-f83847318fa60bbc55c7dba2e2bfc01fb7ca2fdc.tar.bz2 uhd-f83847318fa60bbc55c7dba2e2bfc01fb7ca2fdc.zip |
b100/e100: bump compat for inversion fix on master
-rw-r--r-- | usrp2/top/B100/u1plus_core.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v index ef0ce51f7..423282153 100644 --- a/usrp2/top/B100/u1plus_core.v +++ b/usrp2/top/B100/u1plus_core.v @@ -71,7 +71,7 @@ module u1plus_core localparam SR_GPIO = 224; // 5 //compatibility number -> increment when the fpga has been sufficiently altered - localparam compat_num = {16'd11, 16'd0}; //major, minor + localparam compat_num = {16'd11, 16'd1}; //major, minor //assign run signals used for ATR logic wire [NUM_RX_DSPS-1:0] run_rx_n; |