dsp rework: pass vita clears into dsp modules, unified fifo clears

14 files changed, 76 insertions, 81 deletions

diff --git a/usrp2/custom/custom_dsp_rx.v b/usrp2/custom/custom_dsp_rx.v
index b90cd54e9..2ceda7481 100644
--- a/usrp2/custom/custom_dsp_rx.v
+++ b/usrp2/custom/custom_dsp_rx.v
@@ -36,7 +36,10 @@ module custom_dsp_rx
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
diff --git a/usrp2/custom/custom_dsp_tx.v b/usrp2/custom/custom_dsp_tx.v
index 4b1388b02..5206a63a6 100644
--- a/usrp2/custom/custom_dsp_tx.v
+++ b/usrp2/custom/custom_dsp_tx.v
@@ -36,7 +36,10 @@ module custom_dsp_tx
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, //dsp clock
+    input reset, //active high synchronous reset
+    input clear, //active high on packet control init
+    input enable, //active high when streaming enabled
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
diff --git a/usrp2/gpif/packet_reframer.v b/usrp2/gpif/packet_reframer.v
index 1e913fd77..8bb8a3678 100644
--- a/usrp2/gpif/packet_reframer.v
+++ b/usrp2/gpif/packet_reframer.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/usrp2/gpif/slave_fifo.v b/usrp2/gpif/slave_fifo.v
index b7d740619..10740942b 100644
--- a/usrp2/gpif/slave_fifo.v
+++ b/usrp2/gpif/slave_fifo.v
@@ -1,5 +1,5 @@
 //
-// Copyright 2011 Ettus Research LLC
+// Copyright 2011-2012 Ettus Research LLC
 //
 // This program is free software: you can redistribute it and/or modify
 // it under the terms of the GNU General Public License as published by
diff --git a/usrp2/sdr_lib/ddc_chain.v b/usrp2/sdr_lib/ddc_chain.v
index 3dee978a5..800bb5b13 100644
--- a/usrp2/sdr_lib/ddc_chain.v
+++ b/usrp2/sdr_lib/ddc_chain.v
@@ -19,7 +19,7 @@
 
 module ddc_chain
   #(parameter BASE = 0, parameter DSPNO = 0)
-  (input clk, input rst,
+  (input clk, input rst, input clr,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
@@ -166,7 +166,7 @@ module ddc_chain
      (.clk(clk),.reset(rst), .in(prod_reg_q),.strobe_in(strobe_mult), .out(ddc_chain_out[15:0]), .strobe_out());
 
    dsp_rx_glue #(.DSPNO(DSPNO)) custom(
-    .clock(clk), .reset(rst), .enable(run),
+    .clock(clk), .reset(rst), .clear(clr), .enable(run),
     .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
     .frontend_i(rx_fe_i_mux), .frontend_q(rx_fe_q_mux),
     .ddc_in_i(to_cordic_i), .ddc_in_q(to_cordic_q),
diff --git a/usrp2/sdr_lib/dsp_rx_glue.v b/usrp2/sdr_lib/dsp_rx_glue.v
index 2c7c188e0..e2a1d52b1 100644
--- a/usrp2/sdr_lib/dsp_rx_glue.v
+++ b/usrp2/sdr_lib/dsp_rx_glue.v
@@ -28,7 +28,7 @@ module dsp_rx_glue
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, input reset, input clear, input enable,
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -63,7 +63,7 @@ module dsp_rx_glue
             `else
             RX_DSP0_MODULE rx_dsp0_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
@@ -81,7 +81,7 @@ module dsp_rx_glue
             `else
             RX_DSP1_MODULE rx_dsp1_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .ddc_in_i(ddc_in_i), .ddc_in_q(ddc_in_q),
diff --git a/usrp2/sdr_lib/dsp_tx_glue.v b/usrp2/sdr_lib/dsp_tx_glue.v
index 8eccd2bfc..9af13c6c1 100644
--- a/usrp2/sdr_lib/dsp_tx_glue.v
+++ b/usrp2/sdr_lib/dsp_tx_glue.v
@@ -28,7 +28,7 @@ module dsp_tx_glue
 )
 (
     //control signals
-    input clock, input reset, input enable,
+    input clock, input reset, input clear, input enable,
 
     //user settings bus, controlled through user setting regs API
     input set_stb, input [7:0] set_addr, input [31:0] set_data,
@@ -63,7 +63,7 @@ module dsp_tx_glue
             `else
             TX_DSP0_MODULE tx_dsp0_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
@@ -81,7 +81,7 @@ module dsp_tx_glue
             `else
             TX_DSP1_MODULE tx_dsp1_custom
             (
-                .clock(clock), .reset(reset), .enable(enable),
+                .clock(clock), .reset(reset), .clear(clear), .enable(enable),
                 .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data),
                 .frontend_i(frontend_i), .frontend_q(frontend_q),
                 .duc_out_i(duc_out_i), .duc_out_q(duc_out_q),
diff --git a/usrp2/sdr_lib/duc_chain.v b/usrp2/sdr_lib/duc_chain.v
index d3b2b394f..7a72903a6 100644
--- a/usrp2/sdr_lib/duc_chain.v
+++ b/usrp2/sdr_lib/duc_chain.v
@@ -19,7 +19,7 @@
 
 module duc_chain
   #(parameter BASE = 0, parameter DSPNO = 0)
-  (input clk, input rst,
+  (input clk, input rst, input clr,
    input set_stb, input [7:0] set_addr, input [31:0] set_data,
    input set_stb_user, input [7:0] set_addr_user, input [31:0] set_data_user,
 
@@ -148,7 +148,7 @@ module duc_chain
       );
 
    dsp_tx_glue #(.DSPNO(DSPNO)) dsp_tx_glue(
-    .clock(clk), .reset(rst), .enable(run),
+    .clock(clk), .reset(rst), .clear(clr), .enable(run),
     .set_stb(set_stb_user), .set_addr(set_addr_user), .set_data(set_data_user),
     .frontend_i(tx_fe_i), .frontend_q(tx_fe_q),
     .duc_out_i(prod_i[33:10]), .duc_out_q(prod_q[33:10]),
diff --git a/usrp2/top/B100/u1plus_core.v b/usrp2/top/B100/u1plus_core.v
index c6ef80751..c5fe368a5 100644
--- a/usrp2/top/B100/u1plus_core.v
+++ b/usrp2/top/B100/u1plus_core.v
@@ -53,8 +53,7 @@ module u1plus_core
    localparam SR_TX_FRONT = 54;      // 5 regs (+0 to +4)
 
    localparam SR_REG_TEST32 = 60;    // 1 reg
-   localparam SR_CLEAR_RX_FIFO = 61; // 1 reg
-   localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
+   localparam SR_CLEAR_FIFO = 61;    // 1 reg
    localparam SR_GLOBAL_RESET = 63;  // 1 reg
    localparam SR_USER_REGS = 64;     // 2 regs
 
@@ -107,16 +106,12 @@ module u1plus_core
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
 		 tx_err_src_rdy, tx_err_dst_rdy;
 
-   wire 	 clear_tx, clear_rx;
-   
-   setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_rx));
+   wire 	 clear_fifo;
 
-   setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx
+   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(1)) sr_clear_fifo
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_tx));
-      
+      .in(set_data),.out(),.changed(clear_fifo));
+
    wire 	 run_rx0, run_rx1;
 
    slave_fifo #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
@@ -131,7 +126,7 @@ module u1plus_core
 	 
 	 .dsp_rx_run(run_rx0 | run_rx1),
 	 
-	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
+	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_fifo), .clear_rx(clear_fifo),
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 	 .tx_err_data_i(tx_err_data), .tx_err_src_rdy_i(tx_err_src_rdy), .tx_err_dst_rdy_o(tx_err_dst_rdy),
@@ -145,7 +140,7 @@ module u1plus_core
    // RX ADC Frontend, does IQ Balance, DC Offset, muxing
 
    wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
-   
+
    rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
      (.clk(wb_clk),.rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -157,12 +152,12 @@ module u1plus_core
    // DSP RX 0
 
    wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0;
+   wire 	 strobe_rx0, clear_rx0;
    wire [35:0] 	 vita_rx_data0;
    wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
    
    ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(wb_clk),.rst(wb_rst),
+     (.clk(wb_clk), .rst(wb_rst), .clr(clear_rx0),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -174,7 +169,7 @@ module u1plus_core
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(rx_overrun_dsp0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
       .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
       .debug() );
    
@@ -182,12 +177,12 @@ module u1plus_core
    // DSP RX 1
 
    wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1;
+   wire 	 strobe_rx1, clear_rx1;
    wire [35:0] 	 vita_rx_data1;
    wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
    
    ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(wb_clk),.rst(wb_rst),
+     (.clk(wb_clk),.rst(wb_rst), .clr(clear_rx1),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -199,7 +194,7 @@ module u1plus_core
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(rx_overrun_dsp1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
       .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
       .debug() );
 
@@ -207,7 +202,7 @@ module u1plus_core
    // RX Stream muxing
 
    fifo36_mux #(.prio(0)) mux_data_streams
-     (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_fifo),
       .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
       .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
       .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
@@ -218,7 +213,7 @@ module u1plus_core
    wire 	 run_tx;
    wire [23:0] 	 tx_fe_i, tx_fe_q;
    wire [31:0]   sample_tx;
-   wire strobe_tx;
+   wire strobe_tx, clear_tx;
 
    vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
@@ -232,11 +227,11 @@ module u1plus_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(tx_underrun_dsp), .run(run_tx),
+      .underrun(tx_underrun_dsp), .run(run_tx), .clear_o(clear_tx),
       .debug(debug_vt));
 
    duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(wb_clk),.rst(wb_rst),
+     (.clk(wb_clk), .rst(wb_rst), .clr(clear_tx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
diff --git a/usrp2/top/E1x0/u1e_core.v b/usrp2/top/E1x0/u1e_core.v
index 765023e29..032c320e0 100644
--- a/usrp2/top/E1x0/u1e_core.v
+++ b/usrp2/top/E1x0/u1e_core.v
@@ -56,8 +56,7 @@ module u1e_core
    localparam SR_TX_FRONT = 54;      // 5 regs (+0 to +4)
 
    localparam SR_REG_TEST32 = 60;    // 1 reg
-   localparam SR_CLEAR_RX_FIFO = 61; // 1 reg
-   localparam SR_CLEAR_TX_FIFO = 62; // 1 reg
+   localparam SR_CLEAR_FIFO = 61;    // 1 reg
    localparam SR_GLOBAL_RESET = 63;  // 1 reg
    localparam SR_USER_REGS = 64;     // 2 regs
 
@@ -104,15 +103,13 @@ module u1e_core
    wire 	 tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy, 
 		 tx_err_src_rdy, tx_err_dst_rdy;
 
-   wire 	 clear_tx, clear_rx;
-   
-   setting_reg #(.my_addr(SR_CLEAR_RX_FIFO), .width(1)) sr_clear_rx
-     (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_rx));
+   wire 	 clear_fifo;
 
-   setting_reg #(.my_addr(SR_CLEAR_TX_FIFO), .width(1)) sr_clear_tx
+   setting_reg #(.my_addr(SR_CLEAR_FIFO), .width(1)) sr_clear_fifo
      (.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_tx));
+      .in(set_data),.out(),.changed(clear_fifo));
+
+   wire 	 run_rx0, run_rx1;
 
    gpmc #(.TXFIFOSIZE(TXFIFOSIZE), .RXFIFOSIZE(RXFIFOSIZE))
    gpmc (.arst(wb_rst),
@@ -127,7 +124,7 @@ module u1e_core
 	 .wb_sel_o(m0_sel), .wb_cyc_o(m0_cyc), .wb_stb_o(m0_stb), .wb_we_o(m0_we),
 	 .wb_ack_i(m0_ack),
 	 
-	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_tx), .clear_rx(clear_rx),
+	 .fifo_clk(wb_clk), .fifo_rst(wb_rst), .clear_tx(clear_fifo), .clear_rx(clear_fifo),
 	 .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
 	 .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
 
@@ -144,8 +141,7 @@ module u1e_core
    // RX ADC Frontend, does IQ Balance, DC Offset, muxing
 
    wire [23:0] 	 rx_fe_i, rx_fe_q;  // 24 bits is total overkill here, but it matches u2/u2p
-   wire 	 run_rx0, run_rx1;
-   
+
    rx_frontend #(.BASE(SR_RX_FRONT)) rx_frontend
      (.clk(wb_clk),.rst(wb_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
@@ -157,12 +153,12 @@ module u1e_core
    // DSP RX 0
 
    wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0;
+   wire 	 strobe_rx0, clear_rx0;
    wire [35:0] 	 vita_rx_data0;
    wire 	 vita_rx_src_rdy0, vita_rx_dst_rdy0;
    
    ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(wb_clk),.rst(wb_rst),
+     (.clk(wb_clk), .rst(wb_rst), .clr(clear_rx0),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -174,7 +170,7 @@ module u1e_core
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(rx_overrun_dsp0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
       .rx_data_o(vita_rx_data0), .rx_dst_rdy_i(vita_rx_dst_rdy0), .rx_src_rdy_o(vita_rx_src_rdy0),
       .debug() );
    
@@ -182,12 +178,12 @@ module u1e_core
    // DSP RX 1
 
    wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1;
+   wire 	 strobe_rx1, clear_rx1;
    wire [35:0] 	 vita_rx_data1;
    wire 	 vita_rx_src_rdy1, vita_rx_dst_rdy1;
    
    ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(wb_clk),.rst(wb_rst),
+     (.clk(wb_clk),.rst(wb_rst), .clr(clear_rx1),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -199,7 +195,7 @@ module u1e_core
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(rx_overrun_dsp1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
       .rx_data_o(vita_rx_data1), .rx_dst_rdy_i(vita_rx_dst_rdy1), .rx_src_rdy_o(vita_rx_src_rdy1),
       .debug() );
 
@@ -207,7 +203,7 @@ module u1e_core
    // RX Stream muxing
 
    fifo36_mux #(.prio(0)) mux_data_streams
-     (.clk(wb_clk), .reset(wb_rst), .clear(0),
+     (.clk(wb_clk), .reset(wb_rst), .clear(clear_fifo),
       .data0_i(vita_rx_data0), .src0_rdy_i(vita_rx_src_rdy0), .dst0_rdy_o(vita_rx_dst_rdy0),
       .data1_i(vita_rx_data1), .src1_rdy_i(vita_rx_src_rdy1), .dst1_rdy_o(vita_rx_dst_rdy1),
       .data_o(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
@@ -218,7 +214,7 @@ module u1e_core
    wire 	 run_tx;
    wire [23:0] 	 tx_fe_i, tx_fe_q;
    wire [31:0]   sample_tx;
-   wire strobe_tx;
+   wire strobe_tx, clear_tx;
 
    vita_tx_chain #(.BASE(SR_TX_CTRL), .FIFOSIZE(10), .POST_ENGINE_FIFOSIZE(11),
 		   .REPORT_ERROR(1), .DO_FLOW_CONTROL(0),
@@ -232,11 +228,11 @@ module u1e_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(tx_underrun_dsp), .run(run_tx),
+      .underrun(tx_underrun_dsp), .run(run_tx), .clear_o(clear_tx),
       .debug(debug_vt));
 
    duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(wb_clk),.rst(wb_rst),
+     (.clk(wb_clk), .rst(wb_rst), .clr(clear_tx),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
diff --git a/usrp2/top/N2x0/u2plus_core.v b/usrp2/top/N2x0/u2plus_core.v
index 8b804bb0c..a0c2e7be6 100644
--- a/usrp2/top/N2x0/u2plus_core.v
+++ b/usrp2/top/N2x0/u2plus_core.v
@@ -578,13 +578,13 @@ module u2plus_core
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0;
+   wire 	 strobe_rx0, clear_rx0;
 
    always @(posedge dsp_clk)
      run_rx0_d1 <= run_rx0;
    
    ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -596,20 +596,20 @@ module u2plus_core
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(overrun0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
       .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
       .debug() );
 
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 1
    wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1;
+   wire 	 strobe_rx1, clear_rx1;
 
    always @(posedge dsp_clk)
      run_rx1_d1 <= run_rx1;
    
    ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -621,7 +621,7 @@ module u2plus_core
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(overrun1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
       .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
       .debug() );
 
@@ -674,12 +674,11 @@ module u2plus_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(underrun), .run(run_tx),
-      .clear_vita(clear_tx), //output internal vita clear signal
+      .underrun(underrun), .run(run_tx), .clear_o(clear_tx),
       .debug(debug_vt));
 
    duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
diff --git a/usrp2/top/USRP2/u2_core.v b/usrp2/top/USRP2/u2_core.v
index 4b2276e4a..7461ded68 100644
--- a/usrp2/top/USRP2/u2_core.v
+++ b/usrp2/top/USRP2/u2_core.v
@@ -566,13 +566,13 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 0
    wire [31:0] 	 sample_rx0;
-   wire 	 strobe_rx0;
+   wire 	 strobe_rx0, clear_rx0;
 
    always @(posedge dsp_clk)
      run_rx0_d1 <= run_rx0;
    
    ddc_chain #(.BASE(SR_RX_DSP0), .DSPNO(0)) ddc_chain0
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx0),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -584,20 +584,20 @@ module u2_core
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(overrun0),
-      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0),
+      .sample(sample_rx0), .run(run_rx0), .strobe(strobe_rx0), .clear_o(clear_rx0),
       .rx_data_o(wr1_dat), .rx_src_rdy_o(wr1_ready_i), .rx_dst_rdy_i(wr1_ready_o),
       .debug() );
 
    // /////////////////////////////////////////////////////////////////////////
    // DSP RX 1
    wire [31:0] 	 sample_rx1;
-   wire 	 strobe_rx1;
+   wire 	 strobe_rx1, clear_rx1;
 
    always @(posedge dsp_clk)
      run_rx1_d1 <= run_rx1;
    
    ddc_chain #(.BASE(SR_RX_DSP1), .DSPNO(1)) ddc_chain1
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk), .rst(dsp_rst), .clr(clear_rx1),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .rx_fe_i(rx_fe_i),.rx_fe_q(rx_fe_q),
@@ -609,7 +609,7 @@ module u2_core
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .vita_time(vita_time), .overrun(overrun1),
-      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1),
+      .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), .clear_o(clear_rx1),
       .rx_data_o(wr3_dat), .rx_src_rdy_o(wr3_ready_i), .rx_dst_rdy_i(wr3_ready_o),
       .debug() );
 
@@ -660,12 +660,11 @@ module u2_core
       .tx_data_i(tx_data), .tx_src_rdy_i(tx_src_rdy), .tx_dst_rdy_o(tx_dst_rdy),
       .err_data_o(tx_err_data), .err_src_rdy_o(tx_err_src_rdy), .err_dst_rdy_i(tx_err_dst_rdy),
       .sample(sample_tx), .strobe(strobe_tx),
-      .underrun(underrun), .run(run_tx),
-      .clear_vita(clear_tx), //output internal vita clear signal
+      .underrun(underrun), .run(run_tx), .clear_o(clear_tx),
       .debug(debug_vt));
 
    duc_chain #(.BASE(SR_TX_DSP), .DSPNO(0)) duc_chain
-     (.clk(dsp_clk),.rst(dsp_rst),
+     (.clk(dsp_clk),.rst(dsp_rst), .clr(clear_tx),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .set_stb_user(set_stb_user), .set_addr_user(set_addr_user), .set_data_user(set_data_user),
       .tx_fe_i(tx_fe_i),.tx_fe_q(tx_fe_q),
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v
index e4f7e9864..c57e6cc05 100644
--- a/usrp2/vrt/vita_rx_chain.v
+++ b/usrp2/vrt/vita_rx_chain.v
@@ -28,9 +28,9 @@ module vita_rx_chain
     input [63:0] vita_time,
     input [31:0] sample, input strobe,
     output [35:0] rx_data_o, output rx_src_rdy_o, input rx_dst_rdy_i,
-    output overrun, output run,
+    output overrun, output run, output clear_o,
     output [31:0] debug );
-       
+
    wire [100:0] sample_data;
    wire 	sample_dst_rdy, sample_src_rdy;
    wire [31:0] 	vrc_debug, vrf_debug;
@@ -39,6 +39,7 @@ module vita_rx_chain
    wire 	rx_src_rdy_int, rx_dst_rdy_int;
 
    wire clear;
+   assign clear_o = clear;
 
    setting_reg #(.my_addr(BASE+3)) sr
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
diff --git a/usrp2/vrt/vita_tx_chain.v b/usrp2/vrt/vita_tx_chain.v
index 93bc703cd..9b478081f 100644
--- a/usrp2/vrt/vita_tx_chain.v
+++ b/usrp2/vrt/vita_tx_chain.v
@@ -32,8 +32,7 @@ module vita_tx_chain
     input [35:0] tx_data_i, input tx_src_rdy_i, output tx_dst_rdy_o,
     output [35:0] err_data_o, output err_src_rdy_o, input err_dst_rdy_i,
     output [31:0] sample, input strobe,
-    output underrun, output run,
-    output clear_vita,
+    output underrun, output run, output clear_o,
     output [31:0] debug);
 
    localparam MAXCHAN = 1;
@@ -51,7 +50,7 @@ module vita_tx_chain
    wire [31:0] 		current_seqnum;
 
    wire clear;
-   assign clear_vita = clear;
+   assign clear_o = clear;
    assign underrun = error;
    assign message = error_code;