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| author | Matt Ettus <matt@ettus.com> | 2011-03-11 10:31:55 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-08 10:52:51 -0700 |
| commit | 883d5af46bf756908a2fe45dea8a7d3673f7cb0a (patch) | |
| tree | 8cd2636b556c8c054dd2fdf38cdc94f05dffa235 | |
| parent | f8a04a4879260b2692b823a067a63c3ca5e35731 (diff) | |
| download | uhd-883d5af46bf756908a2fe45dea8a7d3673f7cb0a.tar.gz uhd-883d5af46bf756908a2fe45dea8a7d3673f7cb0a.tar.bz2 uhd-883d5af46bf756908a2fe45dea8a7d3673f7cb0a.zip | |
unused nets
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx.v | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 9aee52131..36d56174e 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -31,7 +31,6 @@ module dsp_core_rx ); wire [15:0] scale_i, scale_q; - wire [13:0] adc_a_ofs, adc_b_ofs; reg [13:0] adc_i, adc_q; wire [31:0] phase_inc; reg [31:0] phase; |