packet_router: added splitter and mux for slow path stuff (also fixed typo in crossbar input)

2 files changed, 95 insertions, 10 deletions

diff --git a/usrp2/fifo/fifo36_splitter.v b/usrp2/fifo/fifo36_splitter.v
new file mode 100644
index 000000000..cf1978c34
--- /dev/null
+++ b/usrp2/fifo/fifo36_splitter.v
@@ -0,0 +1,68 @@
+
+// Split packets from a fifo based interface so it goes out identically on two interfaces
+
+module fifo36_splitter
+    (
+        input clk, input rst,
+        input [35:0] inp_data, input inp_valid, output inp_ready,
+        output [35:0] out0_data, output out0_valid, input out0_ready,
+        output [35:0] out1_data, output out1_valid, input out1_ready
+    );
+
+    localparam STATE_COPY_BOTH = 0;
+    localparam STATE_COPY_ZERO = 1;
+    localparam STATE_COPY_ONE = 2;
+
+    reg [1:0] state;
+    reg [35:0] data_reg;
+
+    assign out0_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
+    assign out1_data = (state == STATE_COPY_BOTH)? inp_data : data_reg;
+
+    assign out0_valid =
+        (state == STATE_COPY_BOTH)? inp_valid : (
+        (state == STATE_COPY_ZERO)? 1'b1      : (
+    1'b0));
+
+    assign out1_valid =
+        (state == STATE_COPY_BOTH)? inp_valid : (
+        (state == STATE_COPY_ONE)?  1'b1      : (
+    1'b0));
+
+    assign inp_ready = (state == STATE_COPY_BOTH)? (out0_ready | out1_ready) : 1'b0;
+
+    always @(posedge clk)
+    if (rst) begin
+        state <= STATE_COPY_BOTH;
+    end
+    else begin
+        case (state)
+
+        STATE_COPY_BOTH: begin
+            if ((out0_valid & out0_ready) & ~(out1_valid & out1_ready)) begin
+                state <= STATE_COPY_ONE;
+            end
+            else if (~(out0_valid & out0_ready) & (out1_valid & out1_ready)) begin
+                state <= STATE_COPY_ZERO;
+            end
+            data_reg <= inp_data;
+        end
+
+        STATE_COPY_ZERO: begin
+            if (out0_valid & out0_ready) begin
+                state <= STATE_COPY_BOTH;
+            end
+        end
+
+        STATE_COPY_ONE: begin
+            if (out1_valid & out1_ready) begin
+                state <= STATE_COPY_BOTH;
+            end
+        end
+
+        endcase //state
+    end
+
+
+
+endmodule //fifo36_splitter
diff --git a/usrp2/fifo/packet_router.v b/usrp2/fifo/packet_router.v
index 96b7e9e07..1ddfc1bc0 100644
--- a/usrp2/fifo/packet_router.v
+++ b/usrp2/fifo/packet_router.v
@@ -105,7 +105,7 @@ module packet_router
 
     //connect the crossbar ready signals
     assign eth_inp_ready = (master_mode_flag)? com_inp_ready : 1'b1/*null sink*/;
-    assign ser_inp_ready = (master_mode_flag)? crs_inp_ready : eth_inp_ready;
+    assign ser_inp_ready = (master_mode_flag)? crs_inp_ready : com_inp_ready;
 
     ////////////////////////////////////////////////////////////////////
     // Communication output sink crossbar
@@ -330,19 +330,11 @@ module packet_router
     wire com_insp_out_sp_both_valid;
     wire com_insp_out_sp_both_ready;
 
-    //connect the other interfaces into here for now
+    //connect this fast-path signals directly to the DSP out
     assign dsp_out_data = com_insp_out_fp_this_data;
     assign dsp_out_valid = com_insp_out_fp_this_valid;
     assign com_insp_out_fp_this_ready = dsp_out_ready;
 
-    assign crs_out_data = com_insp_out_fp_other_data;
-    assign crs_out_valid = com_insp_out_fp_other_valid;
-    assign com_insp_out_fp_other_ready = crs_out_ready;
-
-    assign cpu_out_data = com_insp_out_sp_both_data;
-    assign cpu_out_valid = com_insp_out_sp_both_valid;
-    assign com_insp_out_sp_both_ready = cpu_out_ready;
-
     reg [1:0] com_insp_state;
     reg [1:0] com_insp_dest;
     reg [3:0] com_insp_dreg_count; //data registers to buffer headers
@@ -472,6 +464,31 @@ module packet_router
     end
 
     ////////////////////////////////////////////////////////////////////
+    // Serdes crossbar output source
+    //   - combine slow-path data with fast-path other data
+    //   - slow-path data is duplicated to this and CPU out
+    ////////////////////////////////////////////////////////////////////
+
+    //dummy signals to join the the splitter and mux below
+    wire [35:0] _sp_split_to_mux_data;
+    wire        _sp_split_to_mux_valid;
+    wire        _sp_split_to_mux_ready;
+
+    fifo36_splitter crs_out_src0(
+        .clk(stream_clk), .rst(stream_rst),
+        .inp_data(com_insp_out_sp_both_data), .inp_valid(com_insp_out_sp_both_valid), .inp_ready(com_insp_out_sp_both_ready),
+        .out0_data(_sp_split_to_mux_data),    .out0_valid(_sp_split_to_mux_valid),    .out0_ready(_sp_split_to_mux_ready),
+        .out1_data(cpu_out_data),             .out1_valid(cpu_out_valid),             .out1_ready(cpu_out_ready)
+    );
+
+    fifo36_mux crs_out_src1(
+        .clk(stream_clk), .reset(stream_rst), .clear(1'b0),
+        .data0_i(com_insp_out_fp_other_data), .src0_rdy_i(com_insp_out_fp_other_valid), .dst0_rdy_o(com_insp_out_fp_other_ready),
+        .data1_i(_sp_split_to_mux_data),      .src1_rdy_i(_sp_split_to_mux_valid),      .dst1_rdy_o(_sp_split_to_mux_ready),
+        .data_o(crs_out_data),                .src_rdy_o(crs_out_valid),                .dst_rdy_i(crs_out_ready)
+    );
+
+    ////////////////////////////////////////////////////////////////////
     // DSP input framer
     //   - add a 1-line frame header to each DSP input packet
     //   - each header is composed of a byte count and flags