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author | Nick Foster <nick@nerdnetworks.org> | 2012-01-23 11:09:41 -0800 |
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committer | Nick Foster <nick@nerdnetworks.org> | 2012-01-23 11:09:41 -0800 |
commit | 111216e5cd579996ec8f498e155e9485580327e6 (patch) | |
tree | 351d3b3daed95efc3ba713a66f9c679b3597bd04 | |
parent | b36ab78c18d7c68ad9c9367004ff8decfb2ce817 (diff) | |
download | uhd-111216e5cd579996ec8f498e155e9485580327e6.tar.gz uhd-111216e5cd579996ec8f498e155e9485580327e6.tar.bz2 uhd-111216e5cd579996ec8f498e155e9485580327e6.zip |
Fix missing B100 core_compile (poor Git hygeine)
-rwxr-xr-x | usrp2/top/B100/core_compile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/usrp2/top/B100/core_compile b/usrp2/top/B100/core_compile new file mode 100755 index 000000000..b2ccc8b49 --- /dev/null +++ b/usrp2/top/B100/core_compile @@ -0,0 +1 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpif/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1plus_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models |