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| author | Matt Ettus <matt@ettus.com> | 2009-11-06 18:55:12 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-11-06 18:55:12 -0800 |
| commit | 80610d42fc8b0a7e9ee424fb6c01d5f34f925fc3 (patch) | |
| tree | 5761d709bcef0aa3ba7a008b42a6b58c0e5eaf90 | |
| parent | f1ce05d0d72a88c7c663f926930298b0657bae14 (diff) | |
| download | uhd-80610d42fc8b0a7e9ee424fb6c01d5f34f925fc3.tar.gz uhd-80610d42fc8b0a7e9ee424fb6c01d5f34f925fc3.tar.bz2 uhd-80610d42fc8b0a7e9ee424fb6c01d5f34f925fc3.zip | |
forgot to declare wires
| -rw-r--r-- | top/u2_core/u2_core.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v index ea4451c4e..bd1690b0b 100644 --- a/top/u2_core/u2_core.v +++ b/top/u2_core/u2_core.v @@ -566,6 +566,10 @@ module u2_core .fifo_occupied(dsp_rx_occ),.fifo_full(dsp_rx_full),.fifo_empty(dsp_rx_empty), .debug_rx(debug_rx) ); */ + wire rx_dst_rdy, rx_src_rdy, rx1_dst_rdy, rx1_src_rdy; + wire [99:0] rx_data; + wire [35:0] rx1_data; + vita_rx_control #(.BASE(SR_RX_CTRL)) vita_rx_control (.clk(dsp_clk), .reset(dsp_rst), .clear(0), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), |