parameterized fifo sizes, some reformatting

2 files changed, 57 insertions, 54 deletions

diff --git a/simple_gemac/simple_gemac_wrapper.v b/simple_gemac/simple_gemac_wrapper.v
index 8da77f096..de445476c 100644
--- a/simple_gemac/simple_gemac_wrapper.v
+++ b/simple_gemac/simple_gemac_wrapper.v
@@ -1,44 +1,46 @@
 
 module simple_gemac_wrapper
-  (input clk125, input reset,
-   // GMII
-   output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
-   input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
-   
-   // Flow Control Interface
-   input pause_req, input [15:0] pause_time,
-   
-   // Client FIFO Interfaces
-   input sys_clk,
-   output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
-   input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
-   
-   // Wishbone Interface
-   input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
-   input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
-   
-   // MIIM
-   inout mdio, output mdc,
-   output [31:0] debug);
-   
-   wire [7:0] rx_data, tx_data;
-   wire       tx_clk, tx_valid, tx_error, tx_ack;
-   wire       rx_clk, rx_valid, rx_error, rx_ack;
-
-   wire [47:0] ucast_addr, mcast_addr;
-   wire pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all, pause_en;
-
-   wire rst_rxclk, rst_txclk;
+  #(parameter RXFIFOSIZE=9,
+    parameter TXFIFOSIZE=6)
+   (input clk125, input reset,
+    // GMII
+    output GMII_GTX_CLK, output GMII_TX_EN, output GMII_TX_ER, output [7:0] GMII_TXD,
+    input GMII_RX_CLK, input GMII_RX_DV, input GMII_RX_ER, input [7:0] GMII_RXD,
+    
+    // Client FIFO Interfaces
+    input sys_clk,
+    output [35:0] rx_f36_data, output rx_f36_src_rdy, input rx_f36_dst_rdy,
+    input [35:0] tx_f36_data, input tx_f36_src_rdy, output tx_f36_dst_rdy,
+    
+    // Wishbone Interface
+    input wb_clk, input wb_rst, input wb_stb, input wb_cyc, output wb_ack, input wb_we,
+    input [7:0] wb_adr, input [31:0] wb_dat_i, output [31:0] wb_dat_o,
+    
+    // MIIM
+    inout mdio, output mdc,
+    output [31:0] debug);
+   
+   wire [7:0] 	  rx_data, tx_data;
+   wire 	  tx_clk, tx_valid, tx_error, tx_ack;
+   wire 	  rx_clk, rx_valid, rx_error, rx_ack;
+   
+   wire [47:0] 	  ucast_addr, mcast_addr;
+   wire 	  pass_ucast, pass_mcast, pass_bcast, pass_pause, pass_all;
+   wire 	  pause_request_en, pause_respect_en;
+   wire [15:0] 	  pause_time, pause_thresh, pause_time_req, rx_fifo_space;
+   
+   wire 	  tx_reset, rx_reset;
    reset_sync reset_sync_tx (.clk(tx_clk),.reset_in(reset),.reset_out(tx_reset));
    reset_sync reset_sync_rx (.clk(rx_clk),.reset_in(reset),.reset_out(rx_reset));
-
+   
    simple_gemac simple_gemac
      (.clk125(clk125),  .reset(reset),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
-      .pause_req(pause_req), .pause_time(pause_time), .pause_en(pause_en),
+      .pause_req(pause_req), .pause_time_req(pause_time_req), 
+      .pause_respect_en(pause_respect_en),
       .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
       .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
       .pass_pause(pass_pause), .pass_all(pass_all),
@@ -55,18 +57,20 @@ module simple_gemac_wrapper
       .mdio(mdio), .mdc(mdc),
       .ucast_addr(ucast_addr), .mcast_addr(mcast_addr),
       .pass_ucast(pass_ucast), .pass_mcast(pass_mcast), .pass_bcast(pass_bcast), 
-      .pass_pause(pass_pause), .pass_all(pass_all), .pause_en(pause_en) );
+      .pass_pause(pass_pause), .pass_all(pass_all), 
+      .pause_respect_en(pause_respect_en), .pause_request_en(pause_request_en),
+      .pause_time(pause_time), .pause_thresh(pause_thresh) );
 
    // RX FIFO Chain
-   wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
-
-   wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
-   wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
-
-   wire [7:0] rx_ll_data, rx_ll_data2;
-
-   wire [35:0] rx_f36_data_int1;
-   wire        rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
+   wire 	  rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy;
+   
+   wire 	  rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2;
+   wire 	  rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n;
+   
+   wire [7:0] 	  rx_ll_data, rx_ll_data2;
+   
+   wire [35:0] 	  rx_f36_data_int1;
+   wire 	  rx_f36_src_rdy_int1, rx_f36_dst_rdy_int1;
    
    rxmac_to_ll8 rx_adapt
      (.clk(rx_clk), .reset(rx_reset), .clear(0),
@@ -92,21 +96,21 @@ module simple_gemac_wrapper
       .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n),
       .f36_data(rx_f36_data_int1), .f36_src_rdy_o(rx_f36_src_rdy_int1), .f36_dst_rdy_i(rx_f36_dst_rdy_int1));
 
-   fifo_2clock_cascade #(.WIDTH(36), .SIZE(6)) rx_2clk_fifo
+   fifo_2clock_cascade #(.WIDTH(36), .SIZE(RXFIFOSIZE)) rx_2clk_fifo
      (.wclk(rx_clk), .datain(rx_f36_data_int1), 
-      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(),
+      .src_rdy_i(rx_f36_src_rdy_int1), .dst_rdy_o(rx_f36_dst_rdy_int1), .space(rx_fifo_space),
       .rclk(sys_clk), .dataout(rx_f36_data), 
       .src_rdy_o(rx_f36_src_rdy), .dst_rdy_i(rx_f36_dst_rdy), .occupied(), .arst(reset));
    
    // TX FIFO Chain
-   wire tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
-   wire tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
-   wire tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
-   wire [7:0] tx_ll_data, tx_ll_data2;
-   wire [35:0] tx_f36_data_int1;
-   wire        tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
-
-   fifo_2clock #(.WIDTH(36), .SIZE(6)) tx_2clk_fifo
+   wire 	  tx_ll_sof, tx_ll_eof, tx_ll_src_rdy, tx_ll_dst_rdy;
+   wire 	  tx_ll_sof2, tx_ll_eof2, tx_ll_src_rdy2, tx_ll_dst_rdy2;
+   wire 	  tx_ll_sof2_n, tx_ll_eof2_n, tx_ll_src_rdy2_n, tx_ll_dst_rdy2_n;
+   wire [7:0] 	  tx_ll_data, tx_ll_data2;
+   wire [35:0] 	  tx_f36_data_int1;
+   wire 	  tx_f36_src_rdy_int1, tx_f36_dst_rdy_int1;
+   
+   fifo_2clock #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_2clk_fifo
      (.wclk(sys_clk), .datain(tx_f36_data), 
       .src_rdy_i(tx_f36_src_rdy), .dst_rdy_o(tx_f36_dst_rdy), .space(),
       .rclk(tx_clk), .dataout(tx_f36_data_int1), 
diff --git a/top/u2_core/u2_core.v b/top/u2_core/u2_core.v
index cd0800afc..918215093 100755
--- a/top/u2_core/u2_core.v
+++ b/top/u2_core/u2_core.v
@@ -398,13 +398,12 @@ module u2_core
    // /////////////////////////////////////////////////////////////////////////
    // Ethernet MAC  Slave #6
 
-   simple_gemac_wrapper simple_gemac_wrapper
+   simple_gemac_wrapper #(.RXFIFOSIZE(11), .TXFIFOSIZE(6)) simple_gemac_wrapper
      (.clk125(clk_to_mac),  .reset(wb_rst),
       .GMII_GTX_CLK(GMII_GTX_CLK), .GMII_TX_EN(GMII_TX_EN),  
       .GMII_TX_ER(GMII_TX_ER), .GMII_TXD(GMII_TXD),
       .GMII_RX_CLK(GMII_RX_CLK), .GMII_RX_DV(GMII_RX_DV),  
       .GMII_RX_ER(GMII_RX_ER), .GMII_RXD(GMII_RXD),
-      .pause_req(0), .pause_time(0),
       .sys_clk(dsp_clk),
       .rx_f36_data({wr2_flags,wr2_dat}), .rx_f36_src_rdy(wr2_ready_i), .rx_f36_dst_rdy(wr2_ready_o),
       .tx_f36_data({rd2_flags,rd2_dat}), .tx_f36_src_rdy(rd2_ready_o), .tx_f36_dst_rdy(rd2_ready_i),
@@ -676,7 +675,7 @@ module u2_core
 			     { 4'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };
  */        
    assign debug 	 = { { GMII_RXD },
-			     { 1'd0, debug_mac2[3:0], GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
+			     { 5'd0, GMII_RX_DV, GMII_RX_ER, GMII_RX_CLK },
 			     { wr2_flags, rd2_flags },
 			     { GMII_TX_EN,3'd0, wr2_ready_i, wr2_ready_o, rd2_ready_i, rd2_ready_o } };