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| author | Matt Ettus <matt@ettus.com> | 2011-02-17 12:52:01 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-02-17 12:52:01 -0800 |
| commit | 4d785384dae8c6c0bd458ce720ac2906920b1804 (patch) | |
| tree | 1d32146cd4819aaf86f8a82a09da304636c22783 | |
| parent | 34a4cdb53dc4ed7e1b77d1034286465b04c21b5a (diff) | |
| download | uhd-4d785384dae8c6c0bd458ce720ac2906920b1804.tar.gz uhd-4d785384dae8c6c0bd458ce720ac2906920b1804.tar.bz2 uhd-4d785384dae8c6c0bd458ce720ac2906920b1804.zip | |
u2/u2p: added 2nd DSP unit
| -rw-r--r-- | usrp2/top/u2_rev3/u2_core.v | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/usrp2/top/u2_rev3/u2_core.v b/usrp2/top/u2_rev3/u2_core.v index dcfe59ed0..7dce8c673 100644 --- a/usrp2/top/u2_rev3/u2_core.v +++ b/usrp2/top/u2_rev3/u2_core.v @@ -635,6 +635,40 @@ module u2_core .datain(rx0_data), .src_rdy_i(rx0_src_rdy), .dst_rdy_o(rx0_dst_rdy), .dataout(wr1_dat), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o)); + // ///////////////////////////////////////////////////////////////////////// + // DSP RX 1 + wire [31:0] sample_rx1; + wire [35:0] rx1_data; + wire clear_rx1, strobe_rx1, rx1_dst_rdy, rx1_src_rdy; + + always @(posedge dsp_clk) + run_rx1_d1 <= run_rx1; + + dsp_core_rx #(.BASE(SR_RX_DSP1)) dsp_core_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b), + .sample(sample_rx1), .run(run_rx1_d1), .strobe(strobe_rx1), + .debug() ); + + setting_reg #(.my_addr(SR_RX_CTRL1+3)) sr_clear_rx1 + (.clk(dsp_clk),.rst(dsp_rst), + .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp), + .out(),.changed(clear_rx1)); + + vita_rx_chain #(.BASE(SR_RX_CTRL1)) vita_rx_chain1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp), + .vita_time(vita_time), .overrun(overrun1), + .sample(sample_rx1), .run(run_rx1), .strobe(strobe_rx1), + .rx_data_o(rx1_data), .rx_src_rdy_o(rx1_src_rdy), .rx_dst_rdy_i(rx1_dst_rdy), + .debug() ); + + fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade1 + (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx1), + .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy), + .dataout(wr3_dat), .src_rdy_o(wr3_ready_i), .dst_rdy_i(wr3_ready_o)); + // /////////////////////////////////////////////////////////////////////////////////// // DSP TX |