preliminary registers definition

2 files changed, 95 insertions, 37 deletions

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..b25c15b81
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+*~
diff --git a/host/lib/usrp/usrp_e/usrp_e_regs.hpp b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
index 219f459a5..edd87e649 100644
--- a/host/lib/usrp/usrp_e/usrp_e_regs.hpp
+++ b/host/lib/usrp/usrp_e/usrp_e_regs.hpp
@@ -1,49 +1,106 @@
+
+
+////////////////////////////////////////////////////////////////
 //
-// Copyright 2010 Ettus Research LLC
-//
-// This program is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published by
-// the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This program is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//         Memory map for embedded wishbone bus
 //
+////////////////////////////////////////////////////////////////
+
+// All addresses are byte addresses.  All accesses are word (16-bit) accesses.
+//  This means that address bit 0 is usually 0.
+//  There are 11 bits of address for the control.
+
+#ifndef __USRP_E_REGS_H
+#define __USRP_E_REGS_H
+
+/////////////////////////////////////////////////////
+// Slave pointers
+
+#define UE_REG_SLAVE(n) ((n)<<7)
+
+/////////////////////////////////////////////////////
+// Slave 0 -- Misc Regs
+
+#define UE_REG_MISC_BASE UE_REG_SLAVE(0)
+
+#define UE_REG_MISC_LED        UE_REG_MISC_BASE + 0
+#define UE_REG_MISC_SW         UE_REG_MISC_BASE + 2
+#define UE_REG_MISC_CGEN_CTRL  UE_REG_MISC_BASE + 4
+#define UE_REG_MISC_CGEN_ST    UE_REG_MISC_BASE + 6
+#define UE_REG_MISC_TEST       UE_REG_MISC_BASE + 8
+
+/////////////////////////////////////////////////////
+// Slave 1 -- UART
+//   CLKDIV is 16 bits, others are only 8
+
+#define UE_REG_UART_BASE UE_REG_SLAVE(1)
 
-#ifndef INCLUDED_USRP_E_REGS_HPP
-#define INCLUDED_USRP_E_REGS_HPP
+#define UE_REG_UART_CLKDIV  UE_REG_UART_BASE + 0
+#define UE_REG_UART_TXLEVEL UE_REG_UART_BASE + 2
+#define UE_REG_UART_RXLEVEL UE_REG_UART_BASE + 4
+#define UE_REG_UART_TXCHAR  UE_REG_UART_BASE + 6
+#define UE_REG_UART_RXCHAR  UE_REG_UART_BASE + 8
+
+/////////////////////////////////////////////////////
+// Slave 2 -- SPI Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define UE_REG_SPI_BASE UE_REG_SLAVE(2)
 
-#include <boost/cstdint.hpp>
 
 ////////////////////////////////////////////////
-// GPIO, Slave 4
-//
-// These go to the daughterboard i/o pins
+// Slave 3 -- I2C Core
+//   This should be accessed through the IOCTL
+//   Users should not touch directly
+
+#define UE_REG_I2C_BASE UE_REG_SLAVE(3)
+
+
+////////////////////////////////////////////////
+// Slave 4 -- GPIO
 
-#define GPIO_BASE 0x40
+#define UE_REG_GPIO_BASE UE_REG_SLAVE(4)
 
-struct gpio_regs_t{
-    boost::uint16_t rx_io;      // tx data in high 16, rx in low 16
-    boost::uint16_t tx_io;
-    boost::uint16_t rx_ddr;     // 32 bits, 1 means output. tx in high 16, rx in low 16
-    boost::uint16_t tx_ddr;
-    boost::uint16_t tx_sel_low; // 16 2-bit fields select which source goes to TX DB
-    boost::uint16_t tx_sel_high;
-    boost::uint16_t rx_sel_low; // 16 2-bit fields select which source goes to RX DB
-    boost::uint16_t rx_sel_high;
-};
+#define UE_REG_GPIO_RX_IO      UE_REG_GPIO_BASE + 0
+#define UE_REG_GPIO_TX_IO      UE_REG_GPIO_BASE + 2
+#define UE_REG_GPIO_RX_DDR     UE_REG_GPIO_BASE + 4
+#define UE_REG_GPIO_TX_DDR     UE_REG_GPIO_BASE + 6
+#define UE_REG_GPIO_RX_SEL     UE_REG_GPIO_BASE + 8
+#define UE_REG_GPIO_TX_SEL     UE_REG_GPIO_BASE + 10
+#define UE_REG_GPIO_RX_DBG     UE_REG_GPIO_BASE + 12
+#define UE_REG_GPIO_TX_DBG     UE_REG_GPIO_BASE + 14
 
 // each 2-bit sel field is layed out this way
-#define GPIO_SEL_SW        0 // if pin is an output, set by software in the io reg
-#define GPIO_SEL_ATR       1 // if pin is an output, set by ATR logic
-#define GPIO_SEL_DEBUG_0   2 // if pin is an output, debug lines from FPGA fabric
-#define GPIO_SEL_DEBUG_1   3 // if pin is an output, debug lines from FPGA fabric
+#define GPIO_SEL_SW	   0 // if pin is an output, set by software in the io reg
+#define	GPIO_SEL_ATR	   1 // if pin is an output, set by ATR logic
+#define	GPIO_SEL_DEBUG_0   0 // if pin is an output, debug lines from FPGA fabric
+#define	GPIO_SEL_DEBUG_1   1 // if pin is an output, debug lines from FPGA fabric
+
+
+////////////////////////////////////////////////////
+// Slave 5 -- Settings Bus
+//
+// Output-only, no readback, 32 registers total
+//  Each register must be written 32 bits at a time
+//  First the address xxx_xx00 and then xxx_xx10
+
+#define UE_REG_SETTINGS_BASE UE_REG_SLAVE(5)
+
+///////////////////////////////////////////////////
+// Slave 6 -- ATR Controller
+//   16 regs
+
+#define UE_REG_ATR_BASE  UE_REG_SLAVE(6)
+
+#define	UE_REG_ATR_IDLE_RXSIDE	UE_REG_ATR_BASE + 0
+#define	UE_REG_ATR_IDLE_TXSIDE	UE_REG_ATR_BASE + 2
+#define UE_REG_ATR_INTX_RXSIDE  UE_REG_ATR_BASE + 4
+#define UE_REG_ATR_INTX_TXSIDE  UE_REG_ATR_BASE + 6
+#define	UE_REG_ATR_INRX_RXSIDE  UE_REG_ATR_BASE + 8
+#define	UE_REG_ATR_INRX_TXSIDE  UE_REG_ATR_BASE + 10
+#define	UE_REG_ATR_FULL_RXSIDE  UE_REG_ATR_BASE + 12
+#define	UE_REG_ATR_FULL_TXSIDE  UE_REG_ATR_BASE + 14
 
-//#define gpio_base ((gpio_regs_t *) GPIO_BASE)
+#endif
 
-#endif /* INCLUDED_USRP_E_REGS_HPP */