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| author | Josh Blum <josh@joshknows.com> | 2011-05-16 11:58:03 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-05-16 11:58:03 -0700 |
| commit | 13be023531fa1be8d43b999c3ea5ab477f101fdc (patch) | |
| tree | 9a24a949aa0d30b9a992d89c232ae1b812b3c09f | |
| parent | e6e010e02a12359a31e70ac7fe2ae7c39fa3e9d6 (diff) | |
| parent | c8565df0e51922443426a0392f5f1fb4e3743ce1 (diff) | |
| download | uhd-13be023531fa1be8d43b999c3ea5ab477f101fdc.tar.gz uhd-13be023531fa1be8d43b999c3ea5ab477f101fdc.tar.bz2 uhd-13be023531fa1be8d43b999c3ea5ab477f101fdc.zip | |
Merge branch 'use_vita_length' into next
| -rw-r--r-- | fpga/usrp2/control_lib/atr_controller.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/control_lib/atr_controller16.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/control_lib/bootram.v | 241 | ||||
| -rw-r--r-- | fpga/usrp2/fifo/dsp_framer36.v | 16 | ||||
| -rw-r--r-- | fpga/usrp2/models/IOBUF.v | 83 | ||||
| -rw-r--r-- | fpga/usrp2/sdr_lib/dsp_core_rx.v | 26 | ||||
| -rwxr-xr-x | fpga/usrp2/top/u1e/core_compile | 3 | ||||
| -rw-r--r-- | fpga/usrp2/top/u1e/u1e_core.v | 39 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/bootloader.rmi | 720 | ||||
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus_core.v | 4 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/trigger_context_pkt.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_rx_chain.v | 9 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_tx_chain.v | 5 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_tx_control.v | 2 | ||||
| -rw-r--r-- | fpga/usrp2/vrt/vita_tx_deframer.v | 4 | ||||
| -rwxr-xr-x | host/lib/transport/gen_vrt_if_packet.py | 6 | ||||
| -rw-r--r-- | host/lib/usrp/usrp_e100/usrp_e100_impl.hpp | 2 |
17 files changed, 765 insertions, 401 deletions
diff --git a/fpga/usrp2/control_lib/atr_controller.v b/fpga/usrp2/control_lib/atr_controller.v index fed2791f9..a161b5e00 100644 --- a/fpga/usrp2/control_lib/atr_controller.v +++ b/fpga/usrp2/control_lib/atr_controller.v @@ -7,7 +7,7 @@ module atr_controller (input clk_i, input rst_i, input [5:0] adr_i, input [3:0] sel_i, input [31:0] dat_i, output reg [31:0] dat_o, input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, input [31:0] master_time, + input run_rx, input run_tx, output [31:0] ctrl_lines); reg [3:0] state; diff --git a/fpga/usrp2/control_lib/atr_controller16.v b/fpga/usrp2/control_lib/atr_controller16.v index 3d8b5b1e9..74ce30a54 100644 --- a/fpga/usrp2/control_lib/atr_controller16.v +++ b/fpga/usrp2/control_lib/atr_controller16.v @@ -7,7 +7,7 @@ module atr_controller16 (input clk_i, input rst_i, input [5:0] adr_i, input [1:0] sel_i, input [15:0] dat_i, output reg [15:0] dat_o, input we_i, input stb_i, input cyc_i, output reg ack_o, - input run_rx, input run_tx, input [31:0] master_time, + input run_rx, input run_tx, output [31:0] ctrl_lines); reg [3:0] state; diff --git a/fpga/usrp2/control_lib/bootram.v b/fpga/usrp2/control_lib/bootram.v index 668012504..29d21ab5a 100644 --- a/fpga/usrp2/control_lib/bootram.v +++ b/fpga/usrp2/control_lib/bootram.v @@ -6,10 +6,10 @@ module bootram (input clk, input reset, - input [12:0] if_adr, + input [13:0] if_adr, output [31:0] if_data, - input [12:0] dwb_adr_i, + input [13:0] dwb_adr_i, input [31:0] dwb_dat_i, output [31:0] dwb_dat_o, input dwb_we_i, @@ -17,17 +17,23 @@ module bootram input dwb_stb_i, input [3:0] dwb_sel_i); - wire [31:0] DOA0, DOA1, DOA2, DOA3; - wire [31:0] DOB0, DOB1, DOB2, DOB3; - wire ENB0, ENB1, ENB2, ENB3; + wire [31:0] DOA0, DOA1, DOA2, DOA3, DOA4, DOA5, DOA6, DOA7; + wire [31:0] DOB0, DOB1, DOB2, DOB3, DOB4, DOB5, DOB6, DOB7; + wire ENB0, ENB1, ENB2, ENB3, ENB4, ENB5, ENB6, ENB7; wire [3:0] WEB; - reg [1:0] delayed_if_bank; + reg [2:0] delayed_if_bank; always @(posedge clk) - delayed_if_bank <= if_adr[12:11]; + delayed_if_bank <= if_adr[13:11]; - assign if_data = delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0); - assign dwb_dat_o = dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0); + assign if_data = delayed_if_bank[2] ? + (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA7 : DOA6) : (delayed_if_bank[0] ? DOA5 : DOA4)) + : (delayed_if_bank[1] ? (delayed_if_bank[0] ? DOA3 : DOA2) : (delayed_if_bank[0] ? DOA1 : DOA0)); + + + assign dwb_dat_o = dwb_adr_i[13] ? + (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB7 : DOB6) : (dwb_adr_i[11] ? DOB5 : DOB4)) + : (dwb_adr_i[12] ? (dwb_adr_i[11] ? DOB3 : DOB2) : (dwb_adr_i[11] ? DOB1 : DOB0)); always @(posedge clk) if(reset) @@ -35,10 +41,14 @@ module bootram else dwb_ack_o <= dwb_stb_i & ~dwb_ack_o; - assign ENB0 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b00); - assign ENB1 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b01); - assign ENB2 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b10); - assign ENB3 = dwb_stb_i & (dwb_adr_i[12:11] == 2'b11); + assign ENB0 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b000); + assign ENB1 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b001); + assign ENB2 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b010); + assign ENB3 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b011); + assign ENB4 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b100); + assign ENB5 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b101); + assign ENB6 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b110); + assign ENB7 = dwb_stb_i & (dwb_adr_i[13:11] == 3'b111); assign WEB = {4{dwb_we_i}} & dwb_sel_i; @@ -161,90 +171,125 @@ module bootram .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input .WEB(WEB) // Port B 4-bit Write Enable Input ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM4 + (.DOA(DOA4), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input -endmodule // bootram + .DOB(DOB4), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB4), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM5 + (.DOA(DOA5), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input -/* - // The following INIT_xx declarations specify the initial contents of the RAM - // Address 0 to 127 - .INIT_00(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_01(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_02(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_03(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_04(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_05(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_06(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_07(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_08(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_09(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_0F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // Address 128 to 255 - .INIT_10(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_11(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_12(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_13(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_14(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_15(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_16(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_17(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_18(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_19(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_1F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // Address 256 to 383 - .INIT_20(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_21(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_22(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_23(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_24(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_25(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_26(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_27(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_28(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_29(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_2F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // Address 384 to 511 - .INIT_30(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_31(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_32(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_33(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_34(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_35(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_36(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_37(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_38(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_39(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3A(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3B(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3C(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3D(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3E(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - .INIT_3F(256’h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000), - // The next set of INITP_xx are for the parity bits - // Address 0 to 127 - .INITP_00(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_01(256’h0000000000000000000000000000000000000000000000000000000000000000), - // Address 128 to 255 - .INITP_02(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_03(256’h0000000000000000000000000000000000000000000000000000000000000000), - // Address 256 to 383 - .INITP_04(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_05(256’h0000000000000000000000000000000000000000000000000000000000000000), - // Address 384 to 511 - .INITP_06(256’h0000000000000000000000000000000000000000000000000000000000000000), - .INITP_07(256’h0000000000000000000000000000000000000000000000000000000000000000) -*/ + .DOB(DOB5), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB5), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM6 + (.DOA(DOA6), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB6), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB6), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + + RAMB16BWE_S36_S36 + #(.INIT_A(36'h000000000), // Value of output RAM registers on Port A at startup + .INIT_B(36'h000000000), // Value of output RAM registers on Port B at startup + .SIM_COLLISION_CHECK("ALL"), // "NONE", "WARNING_ONLY", "GENERATE_X_ONLY", "ALL" + .SRVAL_A(36'h000000000), // Port A output value upon SSR assertion + .SRVAL_B(36'h000000000), // Port B output value upon SSR assertion + .WRITE_MODE_A("WRITE_FIRST"), // WRITE_FIRST, READ_FIRST or NO_CHANGE + .WRITE_MODE_B("WRITE_FIRST")) // WRITE_FIRST, READ_FIRST or NO_CHANGE + RAM7 + (.DOA(DOA7), // Port A 32-bit Data Output + .DOPA(), // Port A 4-bit Parity Output + .ADDRA(if_adr[10:2]), // Port A 9-bit Address Input + .CLKA(clk), // Port A 1-bit Clock + .DIA(32'd0), // Port A 32-bit Data Input + .DIPA(4'd0), // Port A 4-bit parity Input + .ENA(1'b1), // Port A 1-bit RAM Enable Input + .SSRA(1'b0), // Port A 1-bit Synchronous Set/Reset Input + .WEA(1'b0), // Port A 4-bit Write Enable Input + + .DOB(DOB7), // Port B 32-bit Data Output + .DOPB(), // Port B 4-bit Parity Output + .ADDRB(dwb_adr_i[10:2]), // Port B 9-bit Address Input + .CLKB(clk), // Port B 1-bit Clock + .DIB(dwb_dat_i), // Port B 32-bit Data Input + .DIPB(4'd0), // Port-B 4-bit parity Input + .ENB(ENB7), // Port B 1-bit RAM Enable Input + .SSRB(1'b0), // Port B 1-bit Synchronous Set/Reset Input + .WEB(WEB) // Port B 4-bit Write Enable Input + ); // End of RAMB16BWE_S36_S36_inst instantiation + +endmodule // bootram diff --git a/fpga/usrp2/fifo/dsp_framer36.v b/fpga/usrp2/fifo/dsp_framer36.v index c2ae8f96c..58455cee1 100644 --- a/fpga/usrp2/fifo/dsp_framer36.v +++ b/fpga/usrp2/fifo/dsp_framer36.v @@ -1,9 +1,13 @@ -// Frame DSP packets with a header line to be handled by the protocol machine +// This has 3 functions: +// Correct the VITA packet length +// [optional] Frame DSP packets with an header line to be handled by the protocol machine +// Hold on to the packet until there is a complete one before allowing to leave module dsp_framer36 #(parameter BUF_SIZE = 9, - parameter PORT_SEL = 0) + parameter PORT_SEL = 0, + parameter PROT_ENG_FLAGS = 1) (input clk, input reset, input clear, input [35:0] data_i, input src_rdy_i, output dst_rdy_o, output [35:0] data_o, output src_rdy_o, input dst_rdy_i); @@ -48,10 +52,10 @@ module dsp_framer36 always @(posedge clk) if(reset | clear) - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else if(do_xfer_out) if(dfifo_out_data[33]) // eof - pkt_len_out <= 0; + pkt_len_out <= (PROT_ENG_FLAGS ? 1'b0 : 1'b1); else pkt_len_out <= pkt_len_out + 1; @@ -59,8 +63,8 @@ module dsp_framer36 wire [1:0] port_sel_bits = PORT_SEL; - assign data_o = (pkt_len_out == 0) ? {4'b0001, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : - (pkt_len_out == 1) ? {4'b0000, dfifo_out_data[31:16],tfifo_data} : + assign data_o = (pkt_len_out == 0) ? {3'b000, 1'b1, 13'b0, port_sel_bits, 1'b1, tfifo_data[13:0],2'b00} : + (pkt_len_out == 1) ? {3'b000, (PROT_ENG_FLAGS ? 1'b0: 1'b1), dfifo_out_data[31:16],tfifo_data} : {dfifo_out_data[35:33], 1'b0, dfifo_out_data[31:0] }; assign src_rdy_o = dfifo_out_src_rdy & tfifo_out_src_rdy; diff --git a/fpga/usrp2/models/IOBUF.v b/fpga/usrp2/models/IOBUF.v new file mode 100644 index 000000000..1195dfb17 --- /dev/null +++ b/fpga/usrp2/models/IOBUF.v @@ -0,0 +1,83 @@ +// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/unisims/IOBUF.v,v 1.9 2007/05/23 21:43:39 patrickp Exp $ +/////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995/2004 Xilinx, Inc. +// All Right Reserved. +/////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor : Xilinx +// \ \ \/ Version : 10.1 +// \ \ Description : Xilinx Functional Simulation Library Component +// / / Bi-Directional Buffer +// /___/ /\ Filename : IOBUF.v +// \ \ / \ Timestamp : Thu Mar 25 16:42:37 PST 2004 +// \___\/\___\ +// +// Revision: +// 03/23/04 - Initial version. +// 02/22/06 - CR#226003 - Added integer, real parameter type +// 05/23/07 - Changed timescale to 1 ps / 1 ps. +// 05/23/07 - Added wire declaration for internal signals. + +`timescale 1 ps / 1 ps + + +module IOBUF (O, IO, I, T); + + parameter CAPACITANCE = "DONT_CARE"; + parameter integer DRIVE = 12; + parameter IBUF_DELAY_VALUE = "0"; + parameter IFD_DELAY_VALUE = "AUTO"; + parameter IOSTANDARD = "DEFAULT"; + parameter SLEW = "SLOW"; + + output O; + inout IO; + input I, T; + + wire ts; + + //tri0 GTS = glbl.GTS; + + or O1 (ts, GTS, T); + bufif0 T1 (IO, I, ts); + + buf B1 (O, IO); + + initial begin + + case (CAPACITANCE) + + "LOW", "NORMAL", "DONT_CARE" : ; + default : begin + $display("Attribute Syntax Error : The attribute CAPACITANCE on IOBUF instance %m is set to %s. Legal values for this attribute are DONT_CARE, LOW or NORMAL.", CAPACITANCE); + $finish; + end + + endcase + + case (IBUF_DELAY_VALUE) + + "0", "1", "2", "3", "4", "5", "6", "7", "8", "9", "10", "11", "12", "13", "14", "15", "16" : ; + default : begin + $display("Attribute Syntax Error : The attribute IBUF_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are 0, 1, 2, ... or 16.", IBUF_DELAY_VALUE); + $finish; + end + + endcase + + + case (IFD_DELAY_VALUE) + + "AUTO", "0", "1", "2", "3", "4", "5", "6", "7", "8" : ; + default : begin + $display("Attribute Syntax Error : The attribute IFD_DELAY_VALUE on IOBUF instance %m is set to %s. Legal values for this attribute are AUTO, 0, 1, 2, ... or 8.", IFD_DELAY_VALUE); + $finish; + end + + endcase + + end // initial begin + +endmodule + diff --git a/fpga/usrp2/sdr_lib/dsp_core_rx.v b/fpga/usrp2/sdr_lib/dsp_core_rx.v index 1318809d6..a315234cf 100644 --- a/fpga/usrp2/sdr_lib/dsp_core_rx.v +++ b/fpga/usrp2/sdr_lib/dsp_core_rx.v @@ -7,8 +7,6 @@ module dsp_core_rx input [13:0] adc_a, input adc_ovf_a, input [13:0] adc_b, input adc_ovf_b, - input [15:0] io_rx, - output [31:0] sample, input run, output strobe, @@ -33,10 +31,6 @@ module dsp_core_rx wire enable_hb1, enable_hb2; wire [7:0] cic_decim_rate; - wire [31:10] UNUSED_1; - wire [31:4] UNUSED_2; - wire [31:2] UNUSED_3; - setting_reg #(.my_addr(BASE+0)) sr_0 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(phase_inc),.changed()); @@ -45,9 +39,9 @@ module dsp_core_rx (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), .in(set_data),.out({scale_i,scale_q}),.changed()); - setting_reg #(.my_addr(BASE+2)) sr_2 + setting_reg #(.my_addr(BASE+2), .width(10)) sr_2 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({UNUSED_1, enable_hb1, enable_hb2, cic_decim_rate}),.changed()); + .in(set_data),.out({enable_hb1, enable_hb2, cic_decim_rate}),.changed()); rx_dcoffset #(.WIDTH(14),.ADDR(BASE+3)) rx_dcoffset_a (.clk(clk),.rst(rst),.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -60,12 +54,12 @@ module dsp_core_rx wire [7:0] muxctrl; setting_reg #(.my_addr(BASE+5), .width(8)) sr_8 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({UNUSED_2,muxctrl}),.changed()); + .in(set_data),.out(muxctrl),.changed()); wire [1:0] gpio_ena; setting_reg #(.my_addr(BASE+6), .width(2)) sr_9 (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), - .in(set_data),.out({UNUSED_3,gpio_ena}),.changed()); + .in(set_data),.out(gpio_ena),.changed()); always @(posedge clk) case(muxctrl[3:0]) // The I mapping @@ -153,19 +147,9 @@ module dsp_core_rx round #(.bits_in(18),.bits_out(16)) round_iout (.in(i_hb2),.out(i_out)); round #(.bits_in(18),.bits_out(16)) round_qout (.in(q_hb2),.out(q_out)); - // Streaming GPIO - // - // io_rx[15] => I channel LSB if gpio_ena[0] high - // io_rx[14] => Q channel LSB if gpio_ena[1] high - reg [31:0] sample_reg; always @(posedge clk) - begin - sample_reg[31:17] <= i_out[15:1]; - sample_reg[15:1] <= q_out[15:1]; - sample_reg[16] <= gpio_ena[0] ? io_rx[15] : i_out[0]; - sample_reg[0] <= gpio_ena[1] ? io_rx[14] : q_out[0]; - end + sample_reg <= {i_out,q_out}; assign sample = sample_reg; assign strobe = strobe_hb2; diff --git a/fpga/usrp2/top/u1e/core_compile b/fpga/usrp2/top/u1e/core_compile new file mode 100755 index 000000000..dc0cd081e --- /dev/null +++ b/fpga/usrp2/top/u1e/core_compile @@ -0,0 +1,3 @@ +iverilog -Wall -y. -y ../../control_lib/ -y ../../fifo/ -y ../../gpmc/ -y ../../models/ -y ../../sdr_lib/ -y ../../coregen/ -y ../../vrt/ -y ../../opencores/i2c/rtl/verilog/ -y ../../opencores/spi/rtl/verilog/ -y ../../timing/ -y ../../opencores/8b10b/ -I ../../opencores/spi/rtl/verilog/ -I ../../opencores/i2c/rtl/verilog/ -y ../../simple_gemac u1e_core.v 2>&1 | grep -v timescale | grep -v coregen | grep -v models + + diff --git a/fpga/usrp2/top/u1e/u1e_core.v b/fpga/usrp2/top/u1e/u1e_core.v index b3d71b4ab..d10a3ab30 100644 --- a/fpga/usrp2/top/u1e/u1e_core.v +++ b/fpga/usrp2/top/u1e/u1e_core.v @@ -11,7 +11,7 @@ module u1e_core input EM_NWE, input EM_NOE, inout db_sda, inout db_scl, - output sclk, output [7:0] sen, output mosi, input miso, + output sclk, output [15:0] sen, output mosi, input miso, input cgen_st_status, input cgen_st_ld, input cgen_st_refmon, output cgen_sync_b, output cgen_ref_sel, output tx_have_space, output tx_underrun, output rx_have_data, output rx_overrun, @@ -36,7 +36,7 @@ module u1e_core localparam SR_GLOBAL_RESET = 50; // 1 reg localparam SR_REG_TEST32 = 52; // 1 reg - wire [7:0] COMPAT_NUM = 8'd3; + wire [7:0] COMPAT_NUM = 8'd4; wire wb_clk = clk_fpga; wire wb_rst, global_reset; @@ -120,18 +120,15 @@ module u1e_core wire rx_eof = rx_data[33]; wire rx_src_rdy_int, rx_dst_rdy_int, tx_src_rdy_int, tx_dst_rdy_int; - wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug; + wire [31:0] debug_rx_dsp, vrc_debug, vrf_debug, vr_debug; // ///////////////////////////////////////////////////////////////////////// // DSP RX - wire [31:0] sample_rx, sample_tx; - wire strobe_rx, strobe_tx; - wire rx1_dst_rdy, rx1_src_rdy; - wire [99:0] rx1_data; - wire run_rx; + wire [31:0] sample_rx; + wire strobe_rx, run_rx; wire [35:0] vita_rx_data; wire vita_rx_src_rdy, vita_rx_dst_rdy; - + dsp_core_rx #(.BASE(SR_RX_DSP)) dsp_core_rx (.clk(wb_clk),.rst(wb_rst), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), @@ -139,20 +136,13 @@ module u1e_core .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), .debug(debug_rx_dsp) ); - vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), + vita_rx_chain #(.BASE(SR_RX_CTRL), .UNIT(0), .FIFOSIZE(9), .PROT_ENG_FLAGS(0)) vita_rx_chain + (.clk(wb_clk),.reset(wb_rst),.clear(clear_rx), .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), .vita_time(vita_time), .overrun(rx_overrun_dsp), .sample(sample_rx), .run(run_rx), .strobe(strobe_rx), - .sample_fifo_o(rx1_data), .sample_fifo_dst_rdy_i(rx1_dst_rdy), .sample_fifo_src_rdy_o(rx1_src_rdy), - .debug_rx(vrc_debug)); - - vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer - (.clk(wb_clk), .reset(wb_rst), .clear(clear_rx), - .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data), - .sample_fifo_i(rx1_data), .sample_fifo_dst_rdy_o(rx1_dst_rdy), .sample_fifo_src_rdy_i(rx1_src_rdy), - .data_o(vita_rx_data), .dst_rdy_i(vita_rx_dst_rdy), .src_rdy_o(vita_rx_src_rdy), - .debug_rx(vrf_debug) ); + .rx_data_o(vita_rx_data), .rx_dst_rdy_i(vita_rx_dst_rdy), .rx_src_rdy_o(vita_rx_src_rdy), + .debug(vr_debug) ); fifo36_mux #(.prio(0)) mux_err_stream (.clk(wb_clk), .reset(wb_rst), .clear(0), @@ -368,7 +358,7 @@ module u1e_core atr_controller16 atr_controller16 (.clk_i(wb_clk), .rst_i(wb_rst), - .adr_i(s6_adr), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), + .adr_i(s6_adr[5:0]), .sel_i(s6_sel), .dat_i(s6_dat_mosi), .dat_o(s6_dat_miso), .we_i(s6_we), .stb_i(s6_stb), .cyc_i(s6_cyc), .ack_o(s6_ack), .run_rx(run_rx), .run_tx(run_tx), .ctrl_lines(atr_lines)); @@ -383,7 +373,7 @@ module u1e_core wb_readback_mux_16LE readback_mux_32 (.wb_clk_i(wb_clk), .wb_rst_i(wb_rst), .wb_stb_i(s7_stb), - .wb_adr_i(s7_adr), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), + .wb_adr_i({5'b0,s7_adr}), .wb_dat_o(s7_dat_miso), .wb_ack_o(s7_ack), .word00(vita_time[63:32]), .word01(vita_time[31:0]), .word02(vita_time_pps[63:32]), .word03(vita_time_pps[31:0]), @@ -400,7 +390,8 @@ module u1e_core time_64bit #(.TICKS_PER_SEC(32'd64000000),.BASE(SR_TIME64)) time_64bit (.clk(wb_clk), .rst(wb_rst), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), - .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int)); + .pps(pps_in), .vita_time(vita_time), .vita_time_pps(vita_time_pps), .pps_int(pps_int), + .exp_time_in(0)); // ///////////////////////////////////////////////////////////////////////////////////// // Debug circuitry @@ -415,7 +406,7 @@ module u1e_core */ assign debug = debug_gpmc; - assign debug_gpio_0 = { {run_tx, strobe_tx, run_rx, strobe_rx, tx_i[11:0]}, + assign debug_gpio_0 = { {run_tx, 1'b0, run_rx, strobe_rx, tx_i[11:0]}, {2'b00, tx_src_rdy, tx_dst_rdy, tx_q[11:0]} }; assign debug_gpio_1 = debug_vt; diff --git a/fpga/usrp2/top/u2plus/bootloader.rmi b/fpga/usrp2/top/u2plus/bootloader.rmi index a0a3e13c5..e5be670fb 100644 --- a/fpga/usrp2/top/u2plus/bootloader.rmi +++ b/fpga/usrp2/top/u2plus/bootloader.rmi @@ -1,5 +1,5 @@ -defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_a4b10400_3a0b0b0b_0bae940c_82700b0b_0b0b0b0b; -defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_0ba4ee2d_88080b0b_80088408; +defparam bootram.RAM0.INIT_00=256'h00000000_00000000_00000000_d6cd0400_3a0b0b80_80e29c0c_82700b0b_0b0b0b0b; +defparam bootram.RAM0.INIT_01=256'h00000000_00000000_00000000_800c0400_880c840c_80d7972d_88080b0b_80088408; defparam bootram.RAM0.INIT_02=256'h00000000_00000000_04000000_ffff0652_832b2a83_81058205_72830609_71fd0608; defparam bootram.RAM0.INIT_03=256'h83a70400_0b0b0b0b_7383ffff_2b2b0906_05820583_83060981_83ffff73_71fd0608; defparam bootram.RAM0.INIT_04=256'h00000000_00000000_53510400_070a8106_73097306_09060906_72057373_72098105; @@ -7,9 +7,9 @@ defparam bootram.RAM0.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM0.INIT_06=256'h00000000_53510400_81065151_0a31050a_0a720a10_30720a10_71068106_71737109; defparam bootram.RAM0.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_51040000_732e0753_72722673; defparam bootram.RAM0.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c3040000_0b0b0b88; +defparam bootram.RAM0.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_c4040000_0b0b0b88; defparam bootram.RAM0.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_0a535104_720a722b; -defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a6_0981050b_72729f06; +defparam bootram.RAM0.INIT_0B=256'h00000000_00000000_00000000_00000000_05040000_0b0b88a7_0981050b_72729f06; defparam bootram.RAM0.INIT_0C=256'h00000000_00000000_04000000_06075351_8106ff05_0974090a_739f062a_72722aff; defparam bootram.RAM0.INIT_0D=256'h00000000_0c515104_0772fc06_832b0b2b_81058205_73830609_020d0406_71715351; defparam bootram.RAM0.INIT_0E=256'h00000000_00000000_00000000_51040000_0a810653_81050906_72050970_72098105; @@ -18,239 +18,495 @@ defparam bootram.RAM0.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_ defparam bootram.RAM0.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_04000000_05055351_72720981; defparam bootram.RAM0.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_07535104_73730906_72097206; defparam bootram.RAM0.INIT_13=256'h00000000_00000000_04000000_81ff0652_1010102a_81058305_72830609_71fc0608; -defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88a90400_060b0b0b_10100508_80738306_0b0b0bae_71fc0608; -defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_a82d5050_0b0b0b9e_88087575_80088408; -defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_da2d5050_0b0b0b9f_88087575_80088408; +defparam bootram.RAM0.INIT_14=256'h00000000_00000000_88aa0400_060b0b0b_10100508_88738306_0b0b80e2_71fc0608; +defparam bootram.RAM0.INIT_15=256'h00000000_0c510400_0c840c80_80085688_ee2d5050_0b0b80cd_88087575_80088408; +defparam bootram.RAM0.INIT_16=256'h00000000_0c510400_0c840c80_80085688_a02d5050_0b0b80cf_88087575_80088408; defparam bootram.RAM0.INIT_17=256'h04000000_07515151_05ff0506_73097274_70547106_8106ff05_0509060a_72097081; defparam bootram.RAM0.INIT_18=256'h51040000_06075151_7405ff05_06730972_05705471_098106ff_0509060a_72097081; defparam bootram.RAM0.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_05ff0504; -defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_0bae900c_810b0b0b; +defparam bootram.RAM0.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_51040000_80e2980c_810b0b0b; defparam bootram.RAM0.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_04000000_71810552; defparam bootram.RAM0.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_04000000_10100552_02840572; defparam bootram.RAM0.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; defparam bootram.RAM0.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_020d0400_05715351_717105ff; -defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_8e3f0410_81f33f9e; -defparam bootram.RAM0.INIT_21=256'h060c5151_2b0772fc_05101010_09810583_06738306_047381ff_10105351_10101010; -defparam bootram.RAM0.INIT_22=256'h535104ae_ed385151_100a5372_1052720a_72060571_06ff0509_72807281_043c0472; -defparam bootram.RAM0.INIT_23=256'hd00c8290_a0800bb5_b5cc0c82_0b0b0b0b_38838080_08822eb9_a138ae94_9008802e; -defparam bootram.RAM0.INIT_24=256'h80808480_b5d00cf8_8082800b_cc0cf880_0b0b0bb5_8080a40b_0c04f880_800bb5d4; -defparam bootram.RAM0.INIT_25=256'h0ba6c00b_d00c0b0b_80940bb5_0c80c0a8_0b0bb5cc_808c0b0b_0480c0a8_0bb5d40c; -defparam bootram.RAM0.INIT_26=256'hae9c0c70_92388412_5270802e_08700852_a338ae9c_d8335170_ff3d0db5_b5d40c04; -defparam bootram.RAM0.INIT_27=256'hc808802e_0b0b0bb5_04803d0d_833d0d04_0bb5d834_70f03881_70085252_2dae9c08; -defparam bootram.RAM0.INIT_28=256'hf5e23f82_510b0b0b_0b0bb5c8_3d0d040b_06853882_802e0981_0b0b800b_8e380b0b; -defparam bootram.RAM0.INIT_29=256'h518bc33f_d0055273_3fb23dfe_5254868c_59923d70_3dfee005_d03d0db2_3d0d0404; -defparam bootram.RAM0.INIT_2A=256'h3d335473_519e3986_c33fa6c4_52735198_38765378_ff74278f_775482ff_8008b238; -defparam bootram.RAM0.INIT_2B=256'hb039fc3d_858a3fff_39a6fc51_a6c85184_3f91d13f_c4518598_068f38a6_812e0981; -defparam bootram.RAM0.INIT_2C=256'h3fa78051_ef3f86e5_85e63f8e_81e08c0c_8b3f800b_80e4518a_81e08c0c_0d81ff0b; -defparam bootram.RAM0.INIT_2D=256'h51547380_70810651_08708d2a_3f81b8b4_805182ed_81ff0655_ee3f8008_84e23f83; -defparam bootram.RAM0.INIT_2E=256'h80805380_82c33f83_a6388151_8008802e_5190c43f_81fc8080_5184bd3f_c338a7ac; -defparam bootram.RAM0.INIT_2F=256'h88518484_3f8a39a8_735191a0_5184913f_d33fa7cc_8eb93f90_fc808051_ffff5281; -defparam bootram.RAM0.INIT_30=256'h5183e53f_9938a98c_8008802e_518faf3f_3fb0800a_e05183f8_74b238a8_3ffea13f; -defparam bootram.RAM0.INIT_31=256'h8fd53f80_98800a51_5183cd3f_e73fa9c4_800a5190_88ee3fb0_3f82ac51_815181f9; -defparam bootram.RAM0.INIT_32=256'h5183a53f_ca3faac0_800a518d_ffff5298_80805380_83ba3f83_38aa9451_08802eaa; -defparam bootram.RAM0.INIT_33=256'h80085480_518f983f_81fc8080_5183913f_ba39aba0_3faae451_b33f8fd8_82ac5188; -defparam bootram.RAM0.INIT_34=256'hac5187f8_82ea3f82_3faac051_80518d8f_5281fc80_5380ffff_38838080_08802eb5; -defparam bootram.RAM0.INIT_35=256'h82c63ffc_39a88851_3f81548a_80518fe4_5187e93f_db3f82ac_a7cc5182_3f8f9d3f; -defparam bootram.RAM0.INIT_36=256'hb7387581_54807425_74ff1656_5a575758_7a7c7f7f_04f83d0d_0c863d0d_e33f7380; -defparam bootram.RAM0.INIT_37=256'hff065185_05527781_538a3dfc_a1053482_33028405_70810558_8a3d3476_17575473; -defparam bootram.RAM0.INIT_38=256'h04fa3d0d_0c8a3d0d_81547380_8538c139_3f73802e_8a51878c_81ff0654_de3f8008; -defparam bootram.RAM0.INIT_39=256'hd051ff89_81f75280_3dfc0553_34815488_5675883d_748338dc_5580de56_02a30533; -defparam bootram.RAM0.INIT_3A=256'h70525684_02a70533_3dfc0552_34815389_0533893d_7c5702ab_04f93d0d_3f883d0d; -defparam bootram.RAM0.INIT_3B=256'h3f800881_755183c1_76537b52_77259738_2e9e3880_56547380_81ff0670_fe3f8008; -defparam bootram.RAM0.INIT_3C=256'h5381f752_883dfc05_3d0d8154_3d0d04fa_74800c89_83388155_5473802e_ff067056; -defparam bootram.RAM0.INIT_3D=256'h3d0d04fb_75800c88_83388156_2e098106_567480de_883d3356_a03f800b_80d051ff; -defparam bootram.RAM0.INIT_3E=256'h5581c03f_06537652_157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779; -defparam bootram.RAM0.INIT_3F=256'h800b800c_5181a43f_3f8a5272_705253cb_0d747653_0d04fe3d_800c873d_e539800b; -defparam bootram.RAM1.INIT_00=256'h81135374_55558439_76787055_04fc3d0d_3f833d0d_528051de_ff3d0d73_843d0d04; -defparam bootram.RAM1.INIT_01=256'h863d0d04_3473800c_e7388073_2e098106_0652718a_800881ff_80087334_5181bc3f; -defparam bootram.RAM1.INIT_02=256'h0d04ff3d_1234823d_0533aea0_7251028f_04803d0d_3f833d0d_528051c9_ff3d0d73; -defparam bootram.RAM1.INIT_03=256'hfe3d0d80_833d0d04_0c545151_05702272_7610abdc_82908005_14708429_0d738429; -defparam bootram.RAM1.INIT_04=256'h3d0d04fc_25e73884_13538273_51cc3f81_13335272_c43faea4_33527251_53aea013; -defparam bootram.RAM1.INIT_05=256'h527351df_0687388d_812e0981_14335372_9438aea0_2e098106_5654748a_3d0d7678; -defparam bootram.RAM1.INIT_06=256'h3d0d04ff_8c150c86_2ef83874_08537280_55538414_82908005_14708429_3f738429; -defparam bootram.RAM1.INIT_07=256'h0c833d0d_90120880_802ef838_12085170_05535188_29829080_29147084_3d0d7384; -defparam bootram.RAM1.INIT_08=256'haea80570_84517010_71258338_06515184_a408708f_880c81b8_800b81a8_04ff3d0d; -defparam bootram.RAM1.INIT_09=256'h04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c_0c70882a_0681a880_227081ff; -defparam bootram.RAM1.INIT_0A=256'h06515151_862a7081_a8900870_81863881_5171802e_55535481_05970533_76780288; -defparam bootram.RAM1.INIT_0B=256'h51515170_2a708106_90087081_900c81a8_900b81a8_a88c0c81_10810781_70f13872; -defparam bootram.RAM1.INIT_0C=256'h3880e851_71802eb1_802eba38_51515170_70813251_2a708106_90087087_f13881a8; -defparam bootram.RAM1.INIT_0D=256'h81a88c08_5170f138_81065151_70812a70_81a89008_81a8900c_38a05170_71812e83; -defparam bootram.RAM1.INIT_0E=256'h3d0d04fd_70800c85_81a8900c_3980c00b_39815188_ff1252cc_81055634_51707470; -defparam bootram.RAM1.INIT_0F=256'h38721081_515170f1_70810651_0870862a_5481a890_05335553_02880597_3d0d7678; -defparam bootram.RAM1.INIT_10=256'h06515151_812a7081_a8900870_a8900c81_90517081_2e843881_d0517180_a88c0c81; -defparam bootram.RAM1.INIT_11=256'h2e80c538_cf387180_70802e80_51515151_06708132_872a7081_a8900870_70f13881; -defparam bootram.RAM1.INIT_12=256'h70810651_0870812a_0c81a890_7081a890_83389051_5171812e_8c0c80d0_733381a8; -defparam bootram.RAM1.INIT_13=256'h14ff1353_2e8e3881_51517080_81325151_70810670_0870872a_3881a890_515170f1; -defparam bootram.RAM1.INIT_14=256'h81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80_80c00b81_81518a39_54ffb739; -defparam bootram.RAM1.INIT_15=256'h31515186_ac087074_085381b8_3881b8ac_7174259b_a2387052_51525470_70810a06; -defparam bootram.RAM1.INIT_16=256'h06515252_117081ff_0533ffa9_3d0d028f_3d0d04ff_52e23985_f1388112_8d9f7127; -defparam bootram.RAM1.INIT_17=256'h800c833d_06515170_127081ff_268938d0_515171b9_7081ff06_9638c912_7180da26; -defparam bootram.RAM1.INIT_18=256'h17335353_38810b81_810682ef_71ba2e09_5358ff53_56807633_0d797b58_0d04f93d; -defparam bootram.RAM1.INIT_19=256'h51545271_51515153_7080c406_abed1133_72197033_7081ff06_38728114_71782eaa; -defparam bootram.RAM1.INIT_1A=256'h82173352_2b9ff006_3f800884_3351fefb_d8388116_33515271_38721670_802e82bd; -defparam bootram.RAM1.INIT_1B=256'h8a388316_fd537482_33575354_10178b11_84190c70_06720570_800881ff_52feec3f; -defparam bootram.RAM1.INIT_1C=256'h06730585_2b83fe80_3f800888_5253febb_06841733_2bbfe080_3f80088c_3351fecb; -defparam bootram.RAM1.INIT_1D=256'h06730588_800881ff_53fe983f_86173352_f0067305_08842b9f_fea93f80_17335253; -defparam bootram.RAM1.INIT_1E=256'h71773474_80081252_52fdf83f_88173352_2b9ff006_3f800884_3351fe87_180c8716; -defparam bootram.RAM1.INIT_1F=256'h5152fdcf_33555256_70810552_17711970_068c1908_057081ff_38741089_742780d2; -defparam bootram.RAM1.INIT_20=256'h701a7081_08157033_74348c17_08135372_fdc13f80_72335253_2b9ff006_3f800884; -defparam bootram.RAM1.INIT_21=256'h78337205_08881808_b0388417_087526ff_51528417_5a525b51_7081ff06_ff068119; -defparam bootram.RAM1.INIT_22=256'h3f800884_5354fcf3_56545b51_1a891133_ff067310_70307081_54730519_71882a05; -defparam bootram.RAM1.INIT_23=256'h06893885_722e0981_52fb5377_81ff0651_80081270_52fce43f_8a153352_2b9ff006; -defparam bootram.RAM1.INIT_24=256'h515170f1_70810651_0870882a_0d82e090_0d04803d_800c893d_39805372_39fe5383; -defparam bootram.RAM1.INIT_25=256'he0900870_07535382_0780c080_7a8c8006_7880ff06_02930533_04fe3d0d_38823d0d; -defparam bootram.RAM1.INIT_26=256'h0c718280_0682e098_0c7581ff_7182e090_82e0800c_70f13876_06515151_882a7081; -defparam bootram.RAM1.INIT_27=256'h82e08008_5170f138_81065151_70882a70_82e09008_802e9638_0c725172_0782e090; -defparam bootram.RAM1.INIT_28=256'hff873f86_80528051_88548053_0c888055_0b82e094_fc3d0d81_843d0d04_5170800c; -defparam bootram.RAM1.INIT_29=256'h840c7c88_8b0b82e0_82e0900c_0c88800b_0b82e098_fee43f80_3d0d7d56_3d0d04f6; -defparam bootram.RAM1.INIT_2A=256'h7e558054_0cfeb33f_0b82e090_900c8aa8_a80b82e0_e0980c88_0c810b82_2b82e080; -defparam bootram.RAM1.INIT_2B=256'h82e08808_e08c0858_fe983f82_82e0900c_0c8a800b_0b82e090_d3388880_73762780; -defparam bootram.RAM1.INIT_2C=256'h52717327_38705380_70732783_52579053_3d767531_80085b88_085a82e0_5982e084; -defparam bootram.RAM1.INIT_2D=256'h980c8c3d_800b82e0_54ffa939_ec397214_34811252_70810557_51703375_91387117; -defparam bootram.RAM1.INIT_2E=256'h70335154_57557417_84059d05_d23f8002_526851fe_545780c0_0d883d70_0d04ea3d; -defparam bootram.RAM1.INIT_2F=256'h85388154_2e098106_54738199_16703351_06943874_aa2e0981_9d387381_7381ff2e; -defparam bootram.RAM1.INIT_30=256'h527951fe_70545484_3d0d863d_3d0d04f9_73800c98_d1388054_55be7527_8b398115; -defparam bootram.RAM1.INIT_31=256'h893d0d04_5574800c_06833881_752e0981_f73f8008_52735185_8453abe8_823f8055; -defparam bootram.RAM1.INIT_32=256'h72812a88_832a8406_872a0771_2a820671_05337085_3d0d0297_940c04fd_810b81e0; -defparam bootram.RAM1.INIT_33=256'h70720778_2b80c006_ff067685_07077081_a0067173_0674832b_07731090_06717307; -defparam bootram.RAM1.INIT_34=256'hd00a0681_fe3d0d74_853d0d04_52555552_52535155_c0800c51_81ff0682_872b0770; -defparam bootram.RAM1.INIT_35=256'hb251ff87_51ff8c3f_923f8199_81aa51ff_51ff983f_9e3f81ff_81ff51ff_d00a0753; -defparam bootram.RAM1.INIT_36=256'h51fee83f_feed3fb2_81ff0651_fef53f72_ff065252_882a7081_ff813f72_3f80e151; -defparam bootram.RAM1.INIT_37=256'hca3f81a1_3fb051fe_5253fecf_7081ff06_3f72902a_2a51fedb_e23f7298_818151fe; -defparam bootram.RAM1.INIT_38=256'h3f8051fe_a051feab_51feb03f_feb53f80_ba3fa051_3f8e51fe_8051febf_51fec43f; -defparam bootram.RAM1.INIT_39=256'h8025ab38_08880508_fc050c8c_800b8c08_0cf93d0d_8c08028c_0d04ff39_a63f843d; -defparam bootram.RAM1.INIT_3A=256'h08f4050c_38810b8c_fc050888_050c8c08_0b8c08f4_88050c80_08308c08_8c088805; -defparam bootram.RAM1.INIT_3B=256'h050c800b_308c088c_088c0508_25ab388c_8c050880_050c8c08_088c08fc_8c08f405; -defparam bootram.RAM1.INIT_3C=256'h0c80538c_8c08fc05_08f00508_f0050c8c_810b8c08_05088838_0c8c08fc_8c08f005; -defparam bootram.RAM1.INIT_3D=256'h802e8c38_08fc0508_050c548c_708c08f8_a73f8008_05085181_528c0888_088c0508; -defparam bootram.RAM1.INIT_3E=256'h028c0cfb_0c048c08_893d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; -defparam bootram.RAM1.INIT_3F=256'h0c810b8c_8c088805_88050830_93388c08_05088025_0c8c0888_8c08fc05_3d0d800b; -defparam bootram.RAM2.INIT_00=256'h8c050852_81538c08_088c050c_0508308c_388c088c_0880258c_8c088c05_08fc050c; -defparam bootram.RAM2.INIT_01=256'hf8050830_8c388c08_0508802e_548c08fc_08f8050c_8008708c_0851ad3f_8c088805; -defparam bootram.RAM2.INIT_02=256'h810b8c08_0cfd3d0d_8c08028c_0d8c0c04_0c54873d_05087080_0c8c08f8_8c08f805; -defparam bootram.RAM2.INIT_03=256'h802ea338_08fc0508_27ac388c_08880508_8c05088c_050c8c08_0b8c08f8_fc050c80; -defparam bootram.RAM2.INIT_04=256'h08fc050c_0508108c_0c8c08fc_8c088c05_8c050810_99388c08_8c050824_800b8c08; -defparam bootram.RAM2.INIT_05=256'h05088c08_388c0888_050826a1_088c0888_8c088c05_2e80c938_fc050880_c9398c08; -defparam bootram.RAM2.INIT_06=256'h0508812a_0c8c08fc_8c08f805_fc050807_05088c08_0c8c08f8_8c088805_8c050831; -defparam bootram.RAM2.INIT_07=256'h388c0888_08802e8f_8c089005_0cffaf39_8c088c05_0508812a_0c8c088c_8c08fc05; -defparam bootram.RAM2.INIT_08=256'h800c853d_08f40508_050c518c_708c08f4_08f80508_518d398c_08f4050c_0508708c; -defparam bootram.RAM2.INIT_09=256'h38ff1252_70802eb0_07830651_8c387474_52837227_77795656_fc3d0d78_0d8c0c04; -defparam bootram.RAM2.INIT_0A=256'h71ff2e09_14545555_158115ff_06bd3881_712e0981_33525372_38743374_71ff2ea0; -defparam bootram.RAM2.INIT_0B=256'h8414fc14_8f388411_2e098106_70087308_74745451_863d0d04_800b800c_8106e238; -defparam bootram.RAM2.INIT_0C=256'h70797b55_fc3d0d76_863d0d04_7131800c_ffaf3972_70735555_8326e938_54545171; -defparam bootram.RAM2.INIT_0D=256'h70810554_2e983872_125271ff_2ea738ff_06517080_72750783_72278c38_5555558f; -defparam bootram.RAM2.INIT_0E=256'h70840554_04745172_0c863d0d_ea387480_2e098106_125271ff_055634ff_33747081; -defparam bootram.RAM2.INIT_0F=256'h05530c72_08717084_70840554_05530c72_08717084_70840554_05530c72_08717084; -defparam bootram.RAM2.INIT_10=256'h54087170_72708405_72279538_26c93883_1252718f_05530cf0_08717084_70840554; -defparam bootram.RAM2.INIT_11=256'h812e9838_08545472_800bae94_39fd3d0d_7054ff83_8326ed38_fc125271_8405530c; -defparam bootram.RAM2.INIT_12=256'h823fe3a0_b5dc0ce4_519b3f72_ad3f8008_528151e6_b73faeb4_e4993fe3_73b5dc0c; -defparam bootram.RAM2.INIT_13=256'h5a545a77_82c81108_7baeb808_39f73d0d_843f00ff_3f800851_8151e696_3faeb452; -defparam bootram.RAM2.INIT_14=256'hb5387382_38807424_742480e9_59555980_0581712b_841908ff_38818818_802e80d9; -defparam bootram.RAM2.INIT_15=256'h0853722d_53795174_16700853_2eb53878_06537280_80190877_05565681_2b781188; -defparam bootram.RAM2.INIT_16=256'h53bc1308_38aeb808_5877ffad_d6387708_54738025_2c5a5757_fc177981_ff14fc17; -defparam bootram.RAM2.INIT_17=256'hffa938d2_54738025_2c5a5757_fc177981_ff14fc17_0853722d_f8c03f74_a5387951; -defparam bootram.RAM2.INIT_18=256'h08525270_0bfc0570_3d0db5bc_f8943fff_722d7951_bc130853_94397251_398057ff; -defparam bootram.RAM2.INIT_19=256'h04000000_04e3893f_833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138; -defparam bootram.RAM2.INIT_1A=256'h7475726e_65207265_696d6167_61696e20_523a206d_4552524f_4f4b0000_00000040; -defparam bootram.RAM2.INIT_1B=256'h4e4f4b00_64652e00_64206d6f_206c6f61_49484558_20696e20_4261636b_65642120; -defparam bootram.RAM2.INIT_1C=256'h61205a50_756c7472_70657220_72207375_6f616465_6f6f746c_322b2062_55535250; -defparam bootram.RAM2.INIT_1D=256'h696e2073_50322b20_20555352_74696e67_53746172_6e0a0000_6974696f_55206564; -defparam bootram.RAM2.INIT_1E=256'h6f6d206d_6e206672_65747572_523a2072_4552524f_2e000000_6d6f6465_61666520; -defparam bootram.RAM2.INIT_1F=256'h65722068_206e6576_6f756c64_73207368_20546869_72616d21_70726f67_61696e20; -defparam bootram.RAM2.INIT_20=256'h61726520_69726d77_66652066_6f207361_523a206e_4552524f_6e210000_61707065; -defparam bootram.RAM2.INIT_21=256'h6b2e2046_62726963_6d206120_20492061_626c652e_61696c61_65206176_696d6167; -defparam bootram.RAM2.INIT_22=256'h2e000000_2052414d_5820746f_20494845_6c6f6164_20746f20_66726565_65656c20; -defparam bootram.RAM2.INIT_23=256'h6e204650_6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563; -defparam bootram.RAM2.INIT_24=256'h20465047_74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069; -defparam bootram.RAM2.INIT_25=256'h20626f6f_6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d; -defparam bootram.RAM2.INIT_26=256'h20696d61_46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000; -defparam bootram.RAM2.INIT_27=256'h2070726f_6c6f6164_20746f20_74696e67_74656d70_2e0a4174_6f756e64_67652066; -defparam bootram.RAM2.INIT_28=256'h6f647563_64207072_56616c69_2e2e2e00_77617265_6669726d_696f6e20_64756374; -defparam bootram.RAM2.INIT_29=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; -defparam bootram.RAM2.INIT_2A=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; -defparam bootram.RAM2.INIT_2B=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; -defparam bootram.RAM2.INIT_2C=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; -defparam bootram.RAM2.INIT_2D=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; -defparam bootram.RAM2.INIT_2E=256'h14580a2c_2e2e2e00_77617265_6669726d_61666520_6e672073_54727969_6e642e20; -defparam bootram.RAM2.INIT_2F=256'h20202020_28282820_20202828_20202020_00202020_0b0b0b0b_01b200d9_05160364; -defparam bootram.RAM2.INIT_30=256'h10040404_10101010_10101010_10101010_20881010_20202020_20202020_20202020; -defparam bootram.RAM2.INIT_31=256'h01010101_01010101_01010101_41414141_10104141_10101010_04040410_04040404; -defparam bootram.RAM2.INIT_32=256'h02020202_02020202_02020202_42424242_10104242_10101010_01010101_01010101; -defparam bootram.RAM2.INIT_33=256'h00000000_00000000_00000000_00000000_20000000_10101010_02020202_02020202; -defparam bootram.RAM2.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_37=256'h43000000_65000000_792e6578_64756d6d_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_38=256'h00001ac4_00000000_00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff; -defparam bootram.RAM2.INIT_39=256'h00000000_0000173c_000016f0_000b0000_0018000f_ffff0031_05050400_01010100; -defparam bootram.RAM2.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00001a5c_00001a00_000019a4; -defparam bootram.RAM2.INIT_3B=256'h00000000_00000000_00000000_000016fc_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM2.INIT_3F=256'h00000000_00000000_000b0000_deec0005_1234e66d_330eabcd_00000001_00000000; -defparam bootram.RAM3.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_15=256'h00000000_ffffffff_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_ffffffff; -defparam bootram.RAM3.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; -defparam bootram.RAM3.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM0.INIT_20=256'h10101010_10101010_10101010_10101010_10101010_10101010_cf943f04_82813f80; +defparam bootram.RAM0.INIT_21=256'hfc060c51_102b0772_83051010_06098105_ff067383_51047381_10101053_10101010; +defparam bootram.RAM0.INIT_22=256'h51535104_72ed3851_0a100a53_71105272_09720605_8106ff05_72728072_51043c04; +defparam bootram.RAM0.INIT_23=256'h800b80e2_f40c82a0_0b0b80e2_8380800b_822ebd38_80e29c08_802ea438_80e29808; +defparam bootram.RAM0.INIT_24=256'h0b80e2f8_80808280_e2f40cf8_0b0b0b80_808080a4_fc0c04f8_800b80e2_f80c8290; +defparam bootram.RAM0.INIT_25=256'h940b80e2_80c0a880_80e2f40c_8c0b0b0b_80c0a880_e2fc0c04_84800b80_0cf88080; +defparam bootram.RAM0.INIT_26=256'h70085252_80e2a408_5170a738_80e38033_04ff3d0d_80e2fc0c_80d7c80b_f80c0b0b; +defparam bootram.RAM0.INIT_27=256'h8034833d_810b80e3_5270ee38_08700852_2d80e2a4_e2a40c70_38841280_70802e94; +defparam bootram.RAM0.INIT_28=256'h38823d0d_09810685_800b802e_0b0b0b0b_802e8e38_80e2f008_3d0d0b0b_0d040480; +defparam bootram.RAM0.INIT_29=256'h852eb238_5a798380_0d973d22_0404ee3d_3f823d0d_0b0bf5d4_e2f0510b_040b0b80; +defparam bootram.RAM0.INIT_2A=256'h5a953d22_819d3980_862e8f38_39798380_8e3881a7_8380842e_248b3879_79838085; +defparam bootram.RAM0.INIT_2B=256'h7053963d_f423923d_3d2280e4_39815a95_e4f8238a_953d2280_9539825a_80e4fc23; +defparam bootram.RAM0.INIT_2C=256'h7b1d7f1d_3d415e5c_0b883d99_5b5f4080_0284057b_ae3f8008_abdc3f8b_84055241; +defparam bootram.RAM0.INIT_2D=256'h79337b34_7d055b5b_7b1d963d_901f5e5c_ef38800b_5c887c26_7b34811c_5b5b7933; +defparam bootram.RAM0.INIT_2E=256'h7c26ef38_811c5c86_79337b34_601d5b5b_5e5c7b1d_800b881f_7c26ed38_811c5c88; +defparam bootram.RAM0.INIT_2F=256'h3d0d686a_3d0d04ee_9d903f94_7c26ef38_811c5c86_79337b34_611d5b5b_805c7b1e; +defparam bootram.RAM0.INIT_30=256'ha23f80e1_d7cc5198_538a5280_2e8f3875_0856758a_27973876_5a578379_8412085a; +defparam bootram.RAM0.INIT_31=256'h9f185675_17085dff_5ba05c88_3fa0588a_9c51988f_a45280d8_8e387853_5878a326; +defparam bootram.RAM0.INIT_32=256'h39951733_085e82f2_cc3f8008_80c15c8a_56750804_80da8c05_38758429_95268388; +defparam bootram.RAM0.INIT_33=256'h55961733_5a515677_2a848006_70307096_3380f232_92389417_7580f22e_56888058; +defparam bootram.RAM0.INIT_34=256'h80085f80_5199b83f_38815877_75782e83_18335758_52800b97_538c1708_54901708; +defparam bootram.RAM0.INIT_35=256'h398d1733_c95c81dd_8fdb3f80_18335256_ea05538c_7054953d_398d1733_d35c82aa; +defparam bootram.RAM0.INIT_36=256'h75822488_822ea038_17335675_81c7399c_3f80c85c_525690e7_538c1833_70548e18; +defparam bootram.RAM0.INIT_37=256'h17085692_5695398c_1808710c_8c170890_8106a038_75842e09_a138a839_3875812e; +defparam bootram.RAM0.INIT_38=256'h9e387582_5675822e_399c1733_d05c81ba_33763480_08569317_8a398c17_17227623; +defparam bootram.RAM0.INIT_39=256'h17087022_5691398c_08700840_9a388c17_2e098106_a2397584_812e9d38_24883875; +defparam bootram.RAM0.INIT_3A=256'h7553943d_83389456_56947625_398d1733_d25c80fe_33405680_8c170870_40568839; +defparam bootram.RAM0.INIT_3B=256'h94762583_8d173356_3480d739_8405b505_5c800802_bc3f80d6_1733518b_ea05528c; +defparam bootram.RAM0.INIT_3C=256'h05b50534_5c750284_9d3f80d5_1733518a_8e17528c_993f7553_1733518d_3894568c; +defparam bootram.RAM0.INIT_3D=256'h57577533_963d7905_5a587719_800b833d_3ddc0554_17085594_80cc5c8c_ad39785e; +defparam bootram.RAM0.INIT_3E=256'h19963d79_3d5a5877_54800b83_943ddc05_a05ca455_ed38a439_58887826_77348118; +defparam bootram.RAM0.INIT_3F=256'h0d747053_0d04fe3d_a63f943d_8080519d_26ed3883_18588878_33773481_05575775; +defparam bootram.RAM1.INIT_00=256'h8d39a052_3f9db93f_815191ea_5188953f_38a052a0_72802e92_5394b83f_80d8e852; +defparam bootram.RAM1.INIT_01=256'h5280d9a4_89b53f86_80d98851_0d82b53f_0d04fa3d_d93f843d_3f725191_72518884; +defparam bootram.RAM1.INIT_02=256'h92b43f88_3f800851_bd3f85df_85cb3f86_3fa7f13f_c45193f3_8a5280d9_5193fc3f; +defparam bootram.RAM1.INIT_03=256'h96db3f86_52800851_85c13f73_3f800854_8c3f86b1_92ce3f88_3f800851_983f86bd; +defparam bootram.RAM1.INIT_04=256'h83808451_3f8ab252_805197a1_fb528380_96e53f8b_5190bf3f_84528008_a03f8380; +defparam bootram.RAM1.INIT_05=256'h825196f9_dd528380_97833fbe_83808651_3f8ab252_8551978d_b2528380_97973f8a; +defparam bootram.RAM1.INIT_06=256'h802e80c9_08568008_90b43f80_3dfc0551_aabb3f88_51a8a93f_bd3f8ffa_3f805190; +defparam bootram.RAM1.INIT_07=256'h055180c3_52800890_5380d9e8_06ad3884_ee2e0981_557382fd_8e052255_38768008; +defparam bootram.RAM1.INIT_08=256'h3f883974_735185dd_3f86e23f_525491a4_3f941670_f05192b3_9a3880d9_853f8008; +defparam bootram.RAM1.INIT_09=256'h8d38a00b_5573802e_81065155_70852a70_82808c08_3f8eae3f_b43f8fb9_5275519c; +defparam bootram.RAM1.INIT_0A=256'h808c0c80_80c00b82_2efef838_51547380_2a708106_9d3f7486_80d55186_82808c0c; +defparam bootram.RAM1.INIT_0B=256'h3f9f5280_aa3f89d8_889f3f8d_3f82b73f_f53f93c5_fe3d0d85_3ffee839_cf518682; +defparam bootram.RAM1.INIT_0C=256'hcf3f8852_82ac518c_5185913f_3f845284_ac518cdc_859e3f82_9f528051_5185c23f; +defparam bootram.RAM1.INIT_0D=256'h805184e8_82539f52_518cb53f_f73f82ac_52905184_8cc23f90_3f82ac51_88518584; +defparam bootram.RAM1.INIT_0E=256'h9f529e51_8025df38_ff135372_518c993f_db3f80e4_529c5184_8ca63f9f_3f80e451; +defparam bootram.RAM1.INIT_0F=256'h808c0870_803d0d82_843d0d04_810b800c_81e0840c_bf3f890b_52815184_84e33f9f; +defparam bootram.RAM1.INIT_10=256'h82055a57_30708025_a7053370_7f028c05_3d0d7a7d_3d0d04f9_800c5182_8b2a8106; +defparam bootram.RAM1.INIT_11=256'h30709f2a_388a5573_88557383_832e8838_88055575_38728025_75822e93_57585957; +defparam bootram.RAM1.INIT_12=256'h842b0751_fe057072_05777131_76812cff_802e9738_38725472_8177259e_51538054; +defparam bootram.RAM1.INIT_13=256'h73528118_51ac9a3f_ff065277_a43f7281_527b51ac_81805474_86397353_54548054; +defparam bootram.RAM1.INIT_14=256'h54bd5378_815580ca_9f053356_fb3d0d02_893d0d04_51ac8a3f_815280da_51ac923f; +defparam bootram.RAM1.INIT_15=256'hff3ffeb8_51d63f90_3f815281_c551abe1_0d815280_0d04fe3d_e63f873d_527551fe; +defparam bootram.RAM1.INIT_16=256'hfa3d0d78_843d0d04_e0800c53_70900781_81e08008_802ef338_ff065372_3f800881; +defparam bootram.RAM1.INIT_17=256'h33527181_38805471_70802e83_70335252_9e387217_53727627_70565480_7a575781; +defparam bootram.RAM1.INIT_18=256'h04fe3d0d_0c883d0d_81517080_802e8338_74075170_53df3974_80558113_ff2e8338; +defparam bootram.RAM1.INIT_19=256'h88335574_3d0d80e3_3d0d04f9_bcac3f84_80e2ac51_80dae852_88348653_810b80e3; +defparam bootram.RAM1.INIT_1A=256'h80d051ab_54568252_54873d70_24b63886_08558075_3481b8a4_0b80e388_80c63881; +defparam bootram.RAM1.INIT_1B=256'h38865375_0655748c_800881ff_51fee93f_38865275_74802e9c_81ff0655_d53f8008; +defparam bootram.RAM1.INIT_1C=256'h80e2a80c_80dae408_80e38434_0d04810b_800c893d_80e2ac0b_51bbd73f_5280e2ac; +defparam bootram.RAM1.INIT_1D=256'h38845487_807524b3_b8a40855_e3843481_38810b80_557480c3_80e38433_04fb3d0d; +defparam bootram.RAM1.INIT_1E=256'h0551fdfc_52873dfc_2e993884_06557480_800881ff_51aaeb3f_8c5280d0_3dfc0553; +defparam bootram.RAM1.INIT_1F=256'h77568454_04fb3d0d_0c873d0d_e2a80b80_e2a80c80_86387580_ff065574_3f800881; +defparam bootram.RAM1.INIT_20=256'h0b80e384_e2a80c81_38750880_74802e8d_81ff0655_b13f8008_80d051a9_75538c52; +defparam bootram.RAM1.INIT_21=256'h81e08c0c_80e38c0c_08060770_7180e38c_09737506_803d0d73_873d0d04_3474800c; +defparam bootram.RAM1.INIT_22=256'h0c51823d_0c81e098_7080e390_90080607_067180e3_73097375_04803d0d_51823d0d; +defparam bootram.RAM1.INIT_23=256'h8a528051_04ff3d0d_0c843d0d_c93f7280_53805182_0d747053_3f04fe3d_0d0482b1; +defparam bootram.RAM1.INIT_24=256'h157481ff_2e903881_54547280_7081ff06_56567433_3d0d7779_3d0d04fb_82b83f83; +defparam bootram.RAM1.INIT_25=256'h75335556_59565880_0d797b7d_0d04f93d_800c873d_e539800b_5582933f_06537652; +defparam bootram.RAM1.INIT_26=256'h8b387581_5473802e_e53f7433_78525581_81157453_77259d38_38815680_73762ea4; +defparam bootram.RAM1.INIT_27=256'h04fe3d0d_3f833d0d_8051ff8f_3d0d7352_3d0d04ff_75800c89_7324e538_17575376; +defparam bootram.RAM1.INIT_28=256'h528051dd_ff3d0d73_843d0d04_800b800c_5181ab3f_3f8a5272_5253feff_74765370; +defparam bootram.RAM1.INIT_29=256'h73348008_c23f8008_53755181_84398113_56575556_77797b71_04fb3d0d_3f833d0d; +defparam bootram.RAM1.INIT_2A=256'h7431800c_80733472_7224db38_74315274_2e8a3872_387181ff_718a2e90_81ff0652; +defparam bootram.RAM1.INIT_2B=256'h14708429_0d738429_0d04ff3d_1234823d_3380e2b4_51028f05_803d0d72_873d0d04; +defparam bootram.RAM1.INIT_2C=256'hb4133352_805380e2_04fe3d0d_51833d0d_720c5451_f0057022_761080da_82908005; +defparam bootram.RAM1.INIT_2D=256'h0d767856_0d04fc3d_e538843d_53827325_c93f8113_33527251_80e2b813_7251c13f; +defparam bootram.RAM1.INIT_2E=256'h3f738429_527351de_0687388d_812e0981_14335372_3880e2b4_09810695_54748a2e; +defparam bootram.RAM1.INIT_2F=256'h3d0d7484_3d0d04fe_8c150c86_2ef83874_08537280_55538414_82908005_14708429; +defparam bootram.RAM1.INIT_30=256'h800c843d_12085372_2e853890_ff537080_52535181_05881108_29829080_29157084; +defparam bootram.RAM1.INIT_31=256'h38901208_70732e91_52545253_05881108_29829080_29167084_0d807584_0d04fe3d; +defparam bootram.RAM1.INIT_32=256'h0c81b8a4_0b81a888_ff3d0d80_843d0d04_3872800c_545170f1_88140852_7081ff06; +defparam bootram.RAM1.INIT_33=256'h0c70882a_0681a880_227081ff_e2bc0570_51701080_25833884_51518471_08708f06; +defparam bootram.RAM1.INIT_34=256'h55535481_05970533_76780288_04fd3d0d_0c833d0d_0b81a888_51518180_81a8840c; +defparam bootram.RAM1.INIT_35=256'ha88c0c81_10810781_70f13872_06515151_862a7081_a8900870_81863881_5171802e; +defparam bootram.RAM1.INIT_36=256'h2a708106_90087087_f13881a8_51515170_2a708106_90087081_900c81a8_900b81a8; +defparam bootram.RAM1.INIT_37=256'h81a8900c_38a05170_71812e83_3880e851_71802eb1_802eba38_51515170_70813251; +defparam bootram.RAM1.INIT_38=256'hff1252cc_81055634_51707470_81a88c08_5170f138_81065151_70812a70_81a89008; +defparam bootram.RAM1.INIT_39=256'h05335553_02880597_3d0d7678_3d0d04fd_70800c85_81a8900c_3980c00b_39815188; +defparam bootram.RAM1.INIT_3A=256'h2e843881_d0517180_a88c0c81_38721081_515170f1_70810651_0870862a_5481a890; +defparam bootram.RAM1.INIT_3B=256'h872a7081_a8900870_70f13881_06515151_812a7081_a8900870_a8900c81_90517081; +defparam bootram.RAM1.INIT_3C=256'h5171812e_8c0c80d0_733381a8_2e80c538_cf387180_70802e80_51515151_06708132; +defparam bootram.RAM1.INIT_3D=256'h0870872a_3881a890_515170f1_70810651_0870812a_0c81a890_7081a890_83389051; +defparam bootram.RAM1.INIT_3E=256'h80c00b81_81518a39_54ffb739_14ff1353_2e8e3881_51517080_81325151_70810670; +defparam bootram.RAM1.INIT_3F=256'ha2387052_51525470_70810a06_81b8a408_fd3d0d75_853d0d04_5170800c_a8900c80; +defparam bootram.RAM2.INIT_00=256'h52e23985_f1388112_8d9f7127_31515186_ac087074_085381b8_3881b8ac_7174259b; +defparam bootram.RAM2.INIT_01=256'h808c0c80_0cff0b82_0b828084_80800cef_81e20b82_8280880c_3d0dff0b_3d0d04ff; +defparam bootram.RAM2.INIT_02=256'h82808808_04fb3d0d_38833d0d_708025f1_0cff1151_70840554_51a1c972_e4d45287; +defparam bootram.RAM2.INIT_03=256'h38725173_71802e8f_74760652_e4d45555_53810b80_58515280_8c087106_70098280; +defparam bootram.RAM2.INIT_04=256'h04ff3d0d_38873d0d_877325dc_10575553_13841576_0c8f3981_7482808c_0852712d; +defparam bootram.RAM2.INIT_05=256'h72068280_80880870_2b700982_0c518172_d4057571_842980e4_269f3871_73527187; +defparam bootram.RAM2.INIT_06=256'h0c833d0d_5281e0c8_81e0c40c_22747008_0d029205_0404ff3d_52833d0d_880c5351; +defparam bootram.RAM2.INIT_07=256'hcc0c823d_820b81e0_802ef338_06515170_a0087084_cc0c81b8_810b81e0_04803d0d; +defparam bootram.RAM2.INIT_08=256'hb8a00875_2e933881_54527280_08708106_0d81b8a0_0c04fe3d_7181e0c0_0d04de3f; +defparam bootram.RAM2.INIT_09=256'hfc51f7af_8b3880da_5271802e_70810651_3971812a_8080529a_0c535381_71902a71; +defparam bootram.RAM2.INIT_0A=256'h2ef23881_51517080_7080c006_81b8a008_04803d0d_0c843d0d_72527180_3fff9e3f; +defparam bootram.RAM2.INIT_0B=256'ha0087090_0c5281b8_0781e0cc_70902b88_028e0522_04ff3d0d_0c823d0d_80800b80; +defparam bootram.RAM2.INIT_0C=256'h8638ba51_5372802e_0d755480_0d04fd3d_cc0c833d_840b81e0_802ef338_06515170; +defparam bootram.RAM2.INIT_0D=256'h83113356_fb3d0d77_853d0d04_7327e638_81135385_52a1ca3f_14703352_f5c43f72; +defparam bootram.RAM2.INIT_0E=256'h61630290_3d0d7c7e_3d0d04f6_80ed3f87_80db8051_70335356_81113354_82113355; +defparam bootram.RAM2.INIT_0F=256'had51782d_8a387952_3875802e_7680258f_5d5b5957_2a515b5f_7030709f_05bb0533; +defparam bootram.RAM2.INIT_10=256'h527651a9_ffbd3f77_3f800851_7651a990_80537752_79557854_77269438_76305777; +defparam bootram.RAM2.INIT_11=256'h3d0d04f7_f4ac3f82_8b053351_803d0d02_8c3d0d04_3351782d_80db8c05_a83f8008; +defparam bootram.RAM2.INIT_12=256'h387681ff_802e81d1_06575775_337081ff_5c5a5878_5208a4b0_70708405_3d0d8c3d; +defparam bootram.RAM2.INIT_13=256'ha0387580_7580f024_2e80fb38_597580f0_19703357_80db3881_2e098106_065675a5; +defparam bootram.RAM2.INIT_14=256'h397580f5_c638818b_80e42e80_81953975_2e819e38_8a387580_7580e324_e32eb938; +defparam bootram.RAM2.INIT_15=256'h77841983_3880ec39_80f82eba_80f53975_2e80db38_387580f3_80f5248b_2eac3875; +defparam bootram.RAM2.INIT_16=256'h53903977_a4b05480_59568055_19710852_da397784_51792d80_56805275_12335259; +defparam bootram.RAM2.INIT_17=256'ha4b05480_59568055_19710852_92397784_81538a52_55a4b054_52595680_84197108; +defparam bootram.RAM2.INIT_18=256'h76708105_8e388052_5675802e_59567633_19710859_9e397784_51fdd03f_53905275; +defparam bootram.RAM2.INIT_19=256'h803d0d81_a0940c04_04810b81_0c8b3d0d_39800b80_1959fea3_2dec3981_58335179; +defparam bootram.RAM2.INIT_1A=256'hff067b8c_05337980_3d0d0297_3d0d04fd_70f13882_06515151_882a7081_a0900870; +defparam bootram.RAM2.INIT_1B=256'h81a0900c_a0800c72_980c7781_ff0681a0_3f7683ff_555354d0_80c08007_80060770; +defparam bootram.RAM2.INIT_1C=256'h3d0d04fc_70800c85_a0800851_ffaa3f81_802e8938_0c735173_0781a090_7180c280; +defparam bootram.RAM2.INIT_1D=256'h3971902a_555351ee_73058115_10157022_278f3872_80537274_7a545555_3d0d7678; +defparam bootram.RAM2.INIT_1E=256'h86537552_04fd3d0d_0c863d0d_ec397180_902a0552_ffff0672_8d387183_5170802e; +defparam bootram.RAM2.INIT_1F=256'h80720c88_a8528551_3d0d80e3_3d0d04ff_a00c5485_700880e3_aaf83f76_80e39851; +defparam bootram.RAM2.INIT_20=256'h52702254_80e3a452_2253800b_0d029605_0d04fd3d_f338833d_52708025_12ff1252; +defparam bootram.RAM2.INIT_21=256'h787a7183_04fa3d0d_0c853d0d_80517080_7225ee38_12525285_38811288_72742e8e; +defparam bootram.RAM2.INIT_22=256'h80e3a455_80e3a80b_ad398008_0884050c_89387680_8008802e_5856c73f_ffff0653; +defparam bootram.RAM2.INIT_23=256'h73237684_988c3f75_7525eb38_14545585_38811588_71802e8f_88155552_55557308; +defparam bootram.RAM2.INIT_24=256'h88055291_7353923d_54a9c73f_3dd60552_933d5392_0d867054_0d04f13d_140c883d; +defparam bootram.RAM2.INIT_25=256'h23800b8c_8405a605_3d238002_8a800b8b_a2052381_80028405_a9b83f90_3ddc0551; +defparam bootram.RAM2.INIT_26=256'h5e80538a_23685d66_8405ae05_3d238002_c0910b8d_aa052380_80028405_3d238180; +defparam bootram.RAM2.INIT_27=256'h05ba0523_3d220284_903d2396_23983d22_8405ae05_3f800802_0551fdb7_52913de4; +defparam bootram.RAM2.INIT_28=256'h9a903f91_e6840551_80c02981_d4055269_ac53913d_05be0523_23800284_800b913d; +defparam bootram.RAM2.INIT_29=256'h80e39852_a53f8653_f20551a8_3d529a3d_2386539b_800b973d_3d0d805b_3d0d04e8; +defparam bootram.RAM2.INIT_2A=256'h5a800b9b_08800858_f7f73f80_80e20523_22028405_0280f205_51a8973f_9a3df805; +defparam bootram.RAM2.INIT_2B=256'ha33d0840_a13d085f_905d6e5e_4659845c_45a33d08_44a13d08_f005436e_3dc41143; +defparam bootram.RAM2.INIT_2C=256'h75085473_3873760c_73752784_51565a55_90807131_1a787c31_58750870_8c3d5684; +defparam bootram.RAM2.INIT_2D=256'h3f750853_a851eedc_883880db_5473802e_16088306_738c3894_73830654_802e9a38; +defparam bootram.RAM2.INIT_2E=256'h26843880_ac3878bf_778025ff_ff195957_05570817_3f757084_765198e6_94160852; +defparam bootram.RAM2.INIT_2F=256'h1f94055a_943d237f_818a800b_6b6e4040_04ea3d0d_3f9a3d0d_2a51f781_c0597882; +defparam bootram.RAM2.INIT_30=256'h5a79963d_80c08007_ce052369_02840580_23818080_800b953d_80ca0523_79028405; +defparam bootram.RAM2.INIT_31=256'h8008095a_5cfae43f_933d7052_80538a52_08466847_2380e3a0_0580d205_23800284; +defparam bootram.RAM2.INIT_32=256'h923880db_ff065a79_3f800881_5c5e8a8e_983d7053_913d7053_80d20523_79028405; +defparam bootram.RAM2.INIT_33=256'h54908053_5d94557b_60586b57_7f5a6d59_3fa93902_cf3fec8d_3f7a51f6_d451f7db; +defparam bootram.RAM2.INIT_34=256'h3d0d7f58_3d0d04f7_fd8d3f98_7c26ef38_811c5c86_79337b34_7c1f5b5b_805c7b1d; +defparam bootram.RAM2.INIT_35=256'h05237756_028405a6_8b3d2380_88185776_05a20523_3d220284_8a3d238d_02ae0522; +defparam bootram.RAM2.INIT_36=256'h90800284_0b8e3d23_ee3d0d81_8b3d0d04_51fe9e3f_5391527d_8b3df805_7e558854; +defparam bootram.RAM2.INIT_37=256'h80085294_be3f8653_b60523e8_81028405_05b50534_34840284_860b8f3d_05b20523; +defparam bootram.RAM2.INIT_38=256'h3df60551_53805294_a4c83f86_3df20551_80085294_983f8453_a4d83fe9_3dec0551; +defparam bootram.RAM2.INIT_39=256'h8653805b_e4055490_9c55943d_80578056_80598058_0843025c_fc3f8008_a5d53fe8; +defparam bootram.RAM2.INIT_3A=256'haa3d088e_04d93d0d_3f943d0d_ef38fbcf_5b867b26_7a34811b_dba01b33_7a1c5a80; +defparam bootram.RAM2.INIT_3B=256'h8d387952_5b799b26_29f2055b_ac3d0884_9d38901d_09810682_7d90862e_11225f5d; +defparam bootram.RAM2.INIT_3C=256'h802e0981_225a7990_a838821b_09810686_5a79812e_b4397a22_f5b93f86_80dc8451; +defparam bootram.RAM2.INIT_3D=256'h85ff389e_2e098106_225a7981_8c38861b_09810686_798c842e_841b225a_06869a38; +defparam bootram.RAM2.INIT_3E=256'h0551a28a_a93dffa8_80e3a052_08438453_87c33f80_1d70525f_87cb3fa8_1d705240; +defparam bootram.RAM2.INIT_3F=256'h821b2202_22a13d23_a2e83f7a_98527951_865380e3_38a73d5a_800885d5_3f80085c; +defparam bootram.RAM3.INIT_00=256'h05238653_84058182_05348202_84058181_851b3302_33a23d34_0523841b_840580fe; +defparam bootram.RAM3.INIT_01=256'h5b865398_02818e05_5aa2a73f_3dea0552_547f53aa_b53f8470_e40551a2_7952a93d; +defparam bootram.RAM3.INIT_02=256'ha2803f02_7a527e51_3d5f8653_a28c3f9e_3df40551_537f52a9_a2983f79_1d527a51; +defparam bootram.RAM3.INIT_03=256'h811c5c86_79337b34_7f1d5b5b_7d537b1d_3ddc0554_5d9c55a9_7c587c57_7c5a7c59; +defparam bootram.RAM3.INIT_04=256'h5b5b6084_708c2a43_901d7022_0684aa38_802e0981_b4397d90_f99d3f84_7c26ef38; +defparam bootram.RAM3.INIT_05=256'hffff065e_861b2280_06848638_852e0981_06515a79_882a708f_84973879_2e098106; +defparam bootram.RAM3.INIT_06=256'h5580e3a0_7d901c62_8338815f_993f8008_821d51a0_80dba052_7d5f8653_7d83fa38; +defparam bootram.RAM3.INIT_07=256'h5183fe3f_1d529c1d_83c73888_387b802e_815c7e87_80088338_5ca0833f_5470535b; +defparam bootram.RAM3.INIT_08=256'h087a08a4_a4388c1b_09810683_387f912e_812e81bb_415d407f_1c22ec11_891b3382; +defparam bootram.RAM3.INIT_09=256'h1de41d82_838339ac_51f2883f_5280dca4_3879537e_7e7a2e8f_5d5d4240_1f841122; +defparam bootram.RAM3.INIT_0A=256'h3d405a88_499a3d99_993d237f_ec387a22_08802e82_80084280_5df5c73f_1d22535d; +defparam bootram.RAM3.INIT_0B=256'h8853a93d_3d236047_821b2297_519feb3f_5379527f_9c3d4088_519ff73f_537e5279; +defparam bootram.RAM3.INIT_0C=256'h1d7f1d5b_3d5e5c7b_7c557d84_cd3f7b56_527e519f_3f885379_79519fd6_ffb40552; +defparam bootram.RAM3.INIT_0D=256'h887b26ef_34811b5b_0284051c_1b5a7933_38805b7f_887c26ef_34811c5c_5b79337b; +defparam bootram.RAM3.INIT_0E=256'h2e818138_8a387e88_427e832e_7033415b_1b08a41e_81f3398c_085a792d_38618405; +defparam bootram.RAM3.INIT_0F=256'h810681bd_79912e09_1e335b5b_80c01db5_0680e838_832e0981_1a335a79_81db3981; +defparam bootram.RAM3.INIT_10=256'h840c7d81_0c7d81e1_0b81e180_9438810a_2e098106_5c5a797b_80e4fc22_38821b22; +defparam bootram.RAM3.INIT_11=256'hc40c7d81_0c7d81e2_0b81e2c0_9438810a_2e098106_225b797b_3980e4f8_e1880cb3; +defparam bootram.RAM3.INIT_12=256'h3f80de39_e951e48a_e4d00c80_86387d81_2e098106_225b797b_3980e4f4_e2c80c93; +defparam bootram.RAM3.INIT_13=256'h22963d23_0523841a_840580ce_05347d02_840580cd_3d347d02_5d5d7d95_ac1de41d; +defparam bootram.RAM3.INIT_14=256'h527c51f1_537b812a_8a3f8008_70525bf2_6052943d_05237d53_840580d2_861a2202; +defparam bootram.RAM3.INIT_15=256'h3fa93d0d_6151f6b1_7a537f52_7c557e54_05237b56_840580ce_095a7902_fe3f8008; +defparam bootram.RAM3.INIT_16=256'h8c135351_56517108_80e3dc54_38767008_727427a4_d4085553_800b80e3_04fc3d0d; +defparam bootram.RAM3.INIT_17=256'h04fb3d0d_0c863d0d_ff517080_7326e738_81135373_72518b39_81068538_70752e09; +defparam bootram.RAM3.INIT_18=256'he3d40c8e_38811480_73872689_e3d40854_25ba3880_3f800880_5755ffb9_77797153; +defparam bootram.RAM3.INIT_19=256'h54865375_dc120c51_760880e3_1470822b_0c547310_0680e3d8_08811187_3980e3d8; +defparam bootram.RAM3.INIT_1A=256'h813f873d_e005519c_842980e3_53755273_08055486_80081080_14519439_5280e3e0; +defparam bootram.RAM3.INIT_1B=256'h842980e3_54865373_10800805_99388008_73800824_d83f8054_0d7551fe_0d04fd3d; +defparam bootram.RAM3.INIT_1C=256'h2b71902b_12337198_75703381_04fd3d0d_0c853d0d_81547380_519bd73f_e0055276; +defparam bootram.RAM3.INIT_1D=256'h0d883d70_0d04ea3d_5452853d_52535456_7107800c_07831633_70882b72_07821433; +defparam bootram.RAM3.INIT_1E=256'h9d387381_7381ff2e_70335154_57557417_84059d05_b43f8002_52685194_545780c0; +defparam bootram.RAM3.INIT_1F=256'h55be7527_8b398115_85388154_2e098106_54738199_16703351_06943874_aa2e0981; +defparam bootram.RAM3.INIT_20=256'h845380dc_e43f8055_52795193_70545484_3d0d863d_3d0d04f9_73800c98_d1388054; +defparam bootram.RAM3.INIT_21=256'he0940c04_04810b81_0c893d0d_81557480_81068338_08752e09_99c43f80_c8527351; +defparam bootram.RAM3.INIT_22=256'h81065151_708d2a70_81b8b408_5189bb3f_ff065580_3f800881_d13f8abc_fc3d0d8d; +defparam bootram.RAM3.INIT_23=256'h8008802e_51febf3f_3fb0800a_8451e1a4_b53880dd_81833974_80dccc51_54738838; +defparam bootram.RAM3.INIT_24=256'hdde85180_84b53f80_b0800a51_51e6d93f_813f82ac_3f815189_b051e190_9a3880dd; +defparam bootram.RAM3.INIT_25=256'hff529880_805380ff_e33f8380_deb451e0_2ebb3880_3f800880_0a51fee3_cc399880; +defparam bootram.RAM3.INIT_26=256'h82ac51e6_51e0bd3f_3f80df84_9b3ffee5_82ac51e6_51e0cd3f_3f80dee0_0a5192b9; +defparam bootram.RAM3.INIT_27=256'h0d757053_0c04fd3d_7180e4bc_863d0d04_51e0a93f_3980dfc0_83e93f88_8b3f8051; +defparam bootram.RAM3.INIT_28=256'h2d853d0d_38735172_72802e85_e4bc0853_de9a3f80_a052a051_54eab83f_80e08c52; +defparam bootram.RAM3.INIT_29=256'h04fc3d0d_2d843d0d_38805172_72802e85_e4bc0853_ddfe3f80_a0528051_04fe3d0d; +defparam bootram.RAM3.INIT_2A=256'h08868006_38820b80_802e80ec_54815571_81065153_08862a70_3fff0b80_9a518987; +defparam bootram.RAM3.INIT_2B=256'h54718480_8a3987e8_802e8e38_388a5471_8280248a_2e9b3871_54718280_535580e4; +defparam bootram.RAM3.INIT_2C=256'h83067207_088a2c70_2a8c0680_ba3f7188_52855188_c23f8008_54845188_2e8338ff; +defparam bootram.RAM3.INIT_2D=256'hc8110852_8c0680e2_3f71822b_5452debb_c4555351_c80c80e0_337080e4_80e18411; +defparam bootram.RAM3.INIT_2E=256'ha338fec1_2e098106_a6387481_0c74822e_7480e4c0_082e9838_7480e4c0_52ded53f; +defparam bootram.RAM3.INIT_2F=256'h51fdfb3f_fea73f73_80e4c40c_2e8e3873_80e4c408_06963873_822e0981_3f9e3974; +defparam bootram.RAM3.INIT_30=256'h0b80e4c4_e4c00cff_3f800b80_0851879c_daa93f80_04fd3d0d_3f863d0d_995187c7; +defparam bootram.RAM3.INIT_31=256'he03f8451_528451e4_c73fbabd_529c5187_3f81ae80_985187d0_a63f8d52_0c995187; +defparam bootram.RAM3.INIT_32=256'h8d388008_7380082e_5186f43f_87aa3f84_53548451_f49f0670_08908007_87893f80; +defparam bootram.RAM3.INIT_33=256'h0d04fd3d_833f853d_52805187_08848007_86dd3f80_d63f8051_e0dc51e7_53735280; +defparam bootram.RAM3.INIT_34=256'h73109006_71730707_812a8806_2a840672_2a077183_82067187_3370852a_0d029705; +defparam bootram.RAM3.INIT_35=256'hff0682c0_2b077081_72077887_80c00670_0676852b_077081ff_06717307_74832ba0; +defparam bootram.RAM3.INIT_36=256'hff51ff9e_0a075381_0a0681d0_3d0d74d0_3d0d04fe_55555285_53515552_800c5152; +defparam bootram.RAM3.INIT_37=256'h813f7288_80e151ff_51ff873f_ff8c3fb2_3f819951_aa51ff92_ff983f81_3f81ff51; +defparam bootram.RAM3.INIT_38=256'h3f72982a_8151fee2_fee83f81_ed3fb251_ff0651fe_f53f7281_065252fe_2a7081ff; +defparam bootram.RAM3.INIT_39=256'h51febf3f_fec43f80_3f81a151_b051feca_53fecf3f_81ff0652_72902a70_51fedb3f; +defparam bootram.RAM3.INIT_3A=256'h04ffaf3d_3f843d0d_8051fea6_51feab3f_feb03fa0_b53f8051_3fa051fe_8e51feba; +defparam bootram.RAM3.INIT_3B=256'h9451e5bf_945280e1_38775382_82932690_58595777_08841208_0880da3d_0d80d83d; +defparam bootram.RAM3.INIT_3C=256'h80ca3875_7580e426_2e80e938_387580e4_80e62698_80cc3875_7580e62e_3f81d039; +defparam bootram.RAM3.INIT_3D=256'h81953975_2e80f738_387580f2_80f3268b_819b3875_7580f32e_3881ac39_80e12ea5; +defparam bootram.RAM3.INIT_3E=256'h8c943f80_3f800841_80398c90_08084181_d7d33f80_3980c15f_da38818b_80f72e80; +defparam bootram.RAM3.INIT_3F=256'h5f80d639_f93f80c5_e0055189_80d33dfd_8c170852_90170853_5f80ee39_084280c6; +defparam bootram.RAM4.INIT_00=256'h5fb73994_bc3980c2_3880c45f_75802e86_81ff0656_bb3f8008_e005518a_80d33dfd; +defparam bootram.RAM4.INIT_01=256'h528c1708_53901708_3dfe8005_a43980d3_3f80d75f_085188dd_08528c17_17539017; +defparam bootram.RAM4.INIT_02=256'hec055480_80d33dfd_5f829455_3f8339a0_8051fcff_3980d35f_80d25f8d_518bba3f; +defparam bootram.RAM4.INIT_03=256'h8251ec9b_ec388380_58887826_77348118_57577533_d53d7905_58771980_0b833d5a; +defparam bootram.RAM4.INIT_04=256'h028405ab_02a70533_3ff93d0d_ff518398_51d8e03f_0d80e1e0_0d04803d_3f80d33d; +defparam bootram.RAM4.INIT_05=256'h0d7a7c7f_0d04f83d_9e3f893d_528051e5_54755381_88805598_2b075757_05337188; +defparam bootram.RAM4.INIT_06=256'h58330284_76708105_738a3d34_81175754_25b73875_56548074_5874ff16_7f5a5757; +defparam bootram.RAM4.INIT_07=256'hef3f7380_548a51dd_0881ff06_dcc13f80_81ff0651_fc055277_82538a3d_05a10534; +defparam bootram.RAM4.INIT_08=256'hdc567588_56748338_335580de_0d02a305_0d04fa3d_800c8a3d_39815473_2e8538c1; +defparam bootram.RAM4.INIT_09=256'hab053389_0d7c5702_0d04f93d_893f883d_80d051ff_5381f752_883dfc05_3d348154; +defparam bootram.RAM4.INIT_0A=256'h802e9e38_70565473_0881ff06_dbe13f80_33705256_5202a705_893dfc05_3d348153; +defparam bootram.RAM4.INIT_0B=256'h5574800c_2e833881_56547380_81ff0670_a43f8008_527551da_3876537b_80772597; +defparam bootram.RAM4.INIT_0C=256'h56567480_0b883d33_ffa03f80_5280d051_055381f7_54883dfc_fa3d0d81_893d0d04; +defparam bootram.RAM4.INIT_0D=256'h0ca60b81_0b81c080_940c80eb_990b81c0_883d0d04_5675800c_06833881_de2e0981; +defparam bootram.RAM4.INIT_0E=256'h820b81c0_c0980c51_70810781_2bbe8006_3d0d7288_b00c0480_b00b81c0_c0ac0c89; +defparam bootram.RAM4.INIT_0F=256'h803d0d72_823d0d04_a808800c_f13881c0_51515170_2a708106_a4087081_a00c81c0; +defparam bootram.RAM4.INIT_10=256'h70812a70_81c0a408_81c0a00c_9c0c840b_517381c0_81c0980c_06708107_882bbe80; +defparam bootram.RAM4.INIT_11=256'h91387583_55575771_72830655_0d787a7c_ff39fa3d_823d0d04_5170f138_81065151; +defparam bootram.RAM4.INIT_12=256'h94387382_55737527_822a7255_88ca3f72_86388151_5271802e_38728306_0652718a; +defparam bootram.RAM4.INIT_13=256'h708f0680_7470842a_04fe3d0d_39883d0d_811454e9_0c525452_12700872_2b771177; +defparam bootram.RAM4.INIT_14=256'h803d0d82_843d0d04_53d3cf3f_ec113352_8f0680e1_d3dc3f72_54515353_e1ec1133; +defparam bootram.RAM4.INIT_15=256'hff067a8c_05337880_3d0d0293_3d0d04fe_70f13882_06515151_882a7081_e0900870; +defparam bootram.RAM4.INIT_16=256'h800c7182_387682e0_515170f1_70810651_0870882a_5382e090_c0800753_80060780; +defparam bootram.RAM4.INIT_17=256'h90087088_963882e0_5172802e_e0900c72_82800782_e0980c71_81ff0682_e0900c75; +defparam bootram.RAM4.INIT_18=256'he0940c88_0d810b82_0d04fc3d_800c843d_80085170_f13882e0_51515170_2a708106; +defparam bootram.RAM4.INIT_19=256'h81528151_548a8053_88805590_04fc3d0d_3f863d0d_8051ff87_80538052_80558854; +defparam bootram.RAM4.INIT_1A=256'hfed53f86_81528051_88548653_0d888055_0d04fc3d_800c863d_0881ff06_fef13f80; +defparam bootram.RAM4.INIT_1B=256'hff065170_3f800881_803d0deb_823d0d04_8106800c_80088132_3d0dca3f_3d0d0480; +defparam bootram.RAM4.INIT_1C=256'h8055a054_ffb43f88_9b38dd3f_75800826_5684e33f_fb3d0d77_823d0d04_802ef438; +defparam bootram.RAM4.INIT_1D=256'h80cb3d08_80c93d08_ffba3d0d_873d0d04_51fe843f_53815280_069b0a07_75fe9b0a; +defparam bootram.RAM4.INIT_1E=256'h805381ff_81a73882_73800826_54849f3f_b4387517_81ff2681_57805573_ff115657; +defparam bootram.RAM4.INIT_1F=256'h9f3f7482_fed43ffd_3ffefd3f_73518aea_cb3d0852_3f755380_52548c8f_52883d70; +defparam bootram.RAM4.INIT_20=256'h0c88a00b_0b82e098_e0800c81_c00a0782_c00a0680_900c76fe_800b82e0_e0980c88; +defparam bootram.RAM4.INIT_21=256'h0c54fe84_0882e08c_fe801570_3d558f56_ef3f80c8_e0900cfc_8aa00b82_82e0900c; +defparam bootram.RAM4.INIT_22=256'h88800b82_e0800c54_15700882_0c54fe8c_0882e084_fe881570_e0880c54_15700882; +defparam bootram.RAM4.INIT_23=256'he0980c81_38800b82_8025ffbc_16565675_3fff1690_900cfcb0_800b82e0_e0900c8a; +defparam bootram.RAM4.INIT_24=256'h082680cb_80577380_5682db3f_12575a56_797b7d72_04f93d0d_80c83d0d_5574800c; +defparam bootram.RAM4.INIT_25=256'h27833876_55577675_80743175_2ea23882_06547380_387581ff_802e80c3_38815774; +defparam bootram.RAM4.INIT_26=256'h807527e1_38745482_74802e8e_31575956_74197676_eb3f7316_527551fd_54775373; +defparam bootram.RAM4.INIT_27=256'h802e8d38_56545573_0d76787a_0d04fc3d_800c893d_3f815776_dc39fd8c_38828054; +defparam bootram.RAM4.INIT_28=256'hcb3f8008_0ca63981_160c8075_0c800b84_800b8816_74279038_ed3f8008_73135481; +defparam bootram.RAM4.INIT_29=256'h51fcc93f_88160c71_84160c71_760c7406_80083072_5281bd3f_ff165651_30707406; +defparam bootram.RAM4.INIT_2A=256'h14088415_38815388_71802e9f_06705452_800881ff_54fc983f_fd3d0d75_863d0d04; +defparam bootram.RAM4.INIT_2B=256'h0d04fc3d_800c853d_3f805372_0c51fc94_05708816_14088008_81823f88_082e9438; +defparam bootram.RAM4.INIT_2C=256'h04ff3d0d_0c863d0d_800a0680_3f8008fe_8151faa3_0a538152_a05481f9_0d888055; +defparam bootram.RAM4.INIT_2D=256'h81069338_70a02e09_06545151_800881ff_7081ff06_8008882a_a038d73f_80e4cc08; +defparam bootram.RAM4.INIT_2E=256'hc03f8008_833d0d04_3f71800c_8438f5b2_52827127_08ea1152_0c80e4cc_7180e4cc; +defparam bootram.RAM4.INIT_2F=256'h04f63d0d_082b800c_3f810b80_0c04ffa9_80082b80_f33f810b_33800c04_80e2c205; +defparam bootram.RAM4.INIT_30=256'he0800c81_7c882b82_82e0840c_900c8b0b_800b82e0_e0980c88_3f800b82_7d56f998; +defparam bootram.RAM4.INIT_31=256'h2780d338_80547376_e73f7e55_e0900cf8_8aa80b82_82e0900c_0c88a80b_0b82e098; +defparam bootram.RAM4.INIT_32=256'he084085a_88085982_085882e0_3f82e08c_900cf8cc_800b82e0_e0900c8a_88800b82; +defparam bootram.RAM4.INIT_33=256'h71175170_73279138_53805271_27833870_90537073_75315257_5b883d76_82e08008; +defparam bootram.RAM4.INIT_34=256'h803d0d72_8c3d0d04_82e0980c_a939800b_721454ff_1252ec39_05573481_33757081; +defparam bootram.RAM4.INIT_35=256'h3f800870_085182de_8c088805_8c050852_80538c08_0cfd3d0d_8c08028c_51f7893f; +defparam bootram.RAM4.INIT_36=256'h05085182_528c0888_088c0508_0d81538c_8c0cfd3d_048c0802_3d0d8c0c_800c5485; +defparam bootram.RAM4.INIT_37=256'h0c8c0888_8c08fc05_3d0d800b_028c0cf9_0c048c08_853d0d8c_70800c54_b93f8008; +defparam bootram.RAM4.INIT_38=256'h08883881_8c08fc05_08f4050c_0c800b8c_8c088805_88050830_ab388c08_05088025; +defparam bootram.RAM4.INIT_39=256'h0508308c_388c088c_088025ab_8c088c05_08fc050c_f405088c_050c8c08_0b8c08f4; +defparam bootram.RAM4.INIT_3A=256'h05088c08_0c8c08f0_8c08f005_8838810b_08fc0508_f0050c8c_800b8c08_088c050c; +defparam bootram.RAM4.INIT_3B=256'h548c08fc_08f8050c_8008708c_5181a73f_08880508_0508528c_538c088c_fc050c80; +defparam bootram.RAM4.INIT_3C=256'h0d8c0c04_0c54893d_05087080_0c8c08f8_8c08f805_f8050830_8c388c08_0508802e; +defparam bootram.RAM4.INIT_3D=256'h08308c08_8c088805_80259338_08880508_fc050c8c_800b8c08_0cfb3d0d_8c08028c; +defparam bootram.RAM4.INIT_3E=256'h050c8153_308c088c_088c0508_258c388c_8c050880_050c8c08_0b8c08fc_88050c81; +defparam bootram.RAM4.INIT_3F=256'h802e8c38_08fc0508_050c548c_708c08f8_ad3f8008_88050851_08528c08_8c088c05; +defparam bootram.RAM5.INIT_00=256'h028c0cfd_0c048c08_873d0d8c_70800c54_08f80508_f8050c8c_08308c08_8c08f805; +defparam bootram.RAM5.INIT_01=256'h388c08fc_050827ac_088c0888_8c088c05_08f8050c_0c800b8c_8c08fc05_3d0d810b; +defparam bootram.RAM5.INIT_02=256'h08fc0508_8c050c8c_08108c08_8c088c05_08249938_8c088c05_a338800b_0508802e; +defparam bootram.RAM5.INIT_03=256'h26a1388c_08880508_8c05088c_c9388c08_08802e80_8c08fc05_050cc939_108c08fc; +defparam bootram.RAM5.INIT_04=256'hf8050c8c_08078c08_8c08fc05_08f80508_88050c8c_08318c08_8c088c05_08880508; +defparam bootram.RAM5.INIT_05=256'h90050880_af398c08_8c050cff_812a8c08_088c0508_fc050c8c_812a8c08_08fc0508; +defparam bootram.RAM5.INIT_06=256'h518c08f4_08f4050c_0508708c_398c08f8_050c518d_708c08f4_08880508_2e8f388c; +defparam bootram.RAM5.INIT_07=256'h06517080_74740783_72278c38_56565283_0d787779_0c04fc3d_853d0d8c_0508800c; +defparam bootram.RAM5.INIT_08=256'h15ff1454_38811581_098106bd_5372712e_33743352_2ea03874_125271ff_2eb038ff; +defparam bootram.RAM5.INIT_09=256'h81068f38_73082e09_54517008_0d047474_800c863d_e238800b_2e098106_555571ff; +defparam bootram.RAM5.INIT_0A=256'h0d04fc3d_800c863d_39727131_5555ffaf_e9387073_51718326_fc145454_84118414; +defparam bootram.RAM5.INIT_0B=256'h71ff2e98_38ff1252_70802ea7_07830651_8c387275_558f7227_7b555555_0d767079; +defparam bootram.RAM5.INIT_0C=256'h3d0d0474_74800c86_8106ea38_71ff2e09_34ff1252_70810556_05543374_38727081; +defparam bootram.RAM5.INIT_0D=256'h05540871_0c727084_70840553_05540871_0c727084_70840553_05540871_51727084; +defparam bootram.RAM5.INIT_0E=256'h95387270_38837227_718f26c9_0cf01252_70840553_05540871_0c727084_70840553; +defparam bootram.RAM5.INIT_0F=256'h71028c05_3d0d7679_ff8339fc_ed387054_52718326_530cfc12_71708405_84055408; +defparam bootram.RAM5.INIT_10=256'h38737370_71ff2e93_38ff1252_70802ea2_74830651_72278a38_55535583_9f053357; +defparam bootram.RAM5.INIT_11=256'h7071902b_882b7507_0d047474_800c863d_06ef3874_ff2e0981_ff125271_81055534; +defparam bootram.RAM5.INIT_12=256'h530c7271_71708405_05530c72_72717084_8405530c_38727170_8f7227a5_07515451; +defparam bootram.RAM5.INIT_13=256'h718326f2_0cfc1252_70840553_90387271_38837227_718f26dd_0cf01252_70840553; +defparam bootram.RAM5.INIT_14=256'h5170802e_74078306_80d93871_5272802e_70545555_0d787a7c_9039fa3d_387053ff; +defparam bootram.RAM5.INIT_15=256'h81873870_3872802e_098106a9_5174712e_33743356_2eb13871_135372ff_80d438ff; +defparam bootram.RAM5.INIT_16=256'h33743356_06d13871_ff2e0981_55555272_8115ff15_fc388112_70802e80_81ff0651; +defparam bootram.RAM5.INIT_17=256'h27883871_57558373_0d047174_800c883d_51525270_06717131_067581ff_517081ff; +defparam bootram.RAM5.INIT_18=256'hff120670_09f7fbfd_38740870_72802eb1_39fc1353_5552ff97_88387476_0874082e; +defparam bootram.RAM5.INIT_19=256'hd0387476_0876082e_27d03874_57558373_84158417_51709a38_80065151_f8848281; +defparam bootram.RAM5.INIT_1A=256'h387380e4_72812e9e_9c085454_800b80e2_04fd3d0d_0c883d0d_39800b80_5552fedf; +defparam bootram.RAM5.INIT_1B=256'he4d00cff_a33f7280_800851f6_ffb9bb3f_dc528151_973f80e2_fb3fffb1_d00cffb1; +defparam bootram.RAM5.INIT_1C=256'h0d80e2e4_ff39ff3d_f6863f00_3f800851_51ffb99e_e2dc5281_b0fa3f80_b1de3fff; +defparam bootram.RAM5.INIT_1D=256'h833d0d04_8106f138_70ff2e09_70085252_702dfc12_ff2e9138_08525270_0bfc0570; +defparam bootram.RAM5.INIT_1E=256'h6c207061_6e74726f_6e20636f_6f722069_21457272_00000040_3f040000_04ffb289; +defparam bootram.RAM5.INIT_1F=256'h74696269_6f6d7061_65642063_70656374_3a204578_646c6572_2068616e_636b6574; +defparam bootram.RAM5.INIT_20=256'h21457272_25640a00_676f7420_62757420_25642c20_62657220_206e756d_6c697479; +defparam bootram.RAM5.INIT_21=256'h3a204578_646c6572_2068616e_636b6574_6c207061_6e74726f_6e20636f_6f722069; +defparam bootram.RAM5.INIT_22=256'h7420676f_2c206275_68202564_656e6774_6164206c_61796c6f_65642070_70656374; +defparam bootram.RAM5.INIT_23=256'h70656564_643a2073_616e6765_6b206368_206c696e_0a657468_0a000000_74202564; +defparam bootram.RAM5.INIT_24=256'h6f616465_6f6f746c_44502062_31302055_50204e32_0a555352_640a0000_203d2025; +defparam bootram.RAM5.INIT_25=256'h723a2025_756d6265_7479206e_62696c69_70617469_20636f6d_46504741_720a0000; +defparam bootram.RAM5.INIT_26=256'h756d6265_7479206e_62696c69_70617469_20636f6d_77617265_4669726d_640a0000; +defparam bootram.RAM5.INIT_27=256'h65727920_65636f76_69702072_476f7420_00000000_61646472_640a0000_723a2025; +defparam bootram.RAM5.INIT_28=256'h000007cc_000007cc_000007cc_000007cc_00000650_00000000_65743a20_7061636b; +defparam bootram.RAM5.INIT_29=256'h000007cc_000007a2_000007cc_000007cc_000006a5_000006bd_000007cc_000007cc; +defparam bootram.RAM5.INIT_2A=256'h00000778_000007cc_0000065d_00000715_000007cc_000006d3_000007cc_000007cc; +defparam bootram.RAM5.INIT_2B=256'h45000000_01b200d9_05160364_14580a2c_3fff0000_0050c285_c0a80a02_00000751; +defparam bootram.RAM5.INIT_2C=256'h00000000_43444546_38394142_34353637_30313233_2e256400_642e2564_25642e25; +defparam bootram.RAM5.INIT_2D=256'h656e7420_69676e6d_6420616c_3a206261_5f706b74_73656e64_ffff0000_ffffffff; +defparam bootram.RAM5.INIT_2E=256'h6f6e3a20_636f6d6d_6e65745f_66000000_72206275_6e642f6f_656e2061_6f66206c; +defparam bootram.RAM5.INIT_2F=256'h666f7220_696e6720_6c6f6f6b_63686520_74206361_6f206869_65642074_6661696c; +defparam bootram.RAM5.INIT_30=256'h3d202564_697a6520_72642073_20776569_6172703a_646c655f_0a68616e_00000000; +defparam bootram.RAM5.INIT_31=256'h3a202564_67746873_206c656e_74656e74_6e736973_696e636f_55445020_0a000000; +defparam bootram.RAM5.INIT_32=256'h696e2073_50322b20_20555352_74696e67_53746172_0b0b0b0b_00000000_2025640a; +defparam bootram.RAM5.INIT_33=256'h6172652e_69726d77_66652066_67207361_6164696e_2e204c6f_6d6f6465_61666520; +defparam bootram.RAM5.INIT_34=256'h6374696f_726f6475_69642070_2076616c_20666f72_6b696e67_43686563_00000000; +defparam bootram.RAM5.INIT_35=256'h74696f6e_6f647563_64207072_56616c69_2e2e2e00_6d616765_47412069_6e204650; +defparam bootram.RAM5.INIT_36=256'h6720746f_7074696e_7474656d_642e2041_666f756e_61676520_4120696d_20465047; +defparam bootram.RAM5.INIT_37=256'h46504741_696f6e20_64756374_2070726f_616c6964_4e6f2076_742e0000_20626f6f; +defparam bootram.RAM5.INIT_38=256'h6820746f_726f7567_67207468_6c6c696e_2e0a4661_6f756e64_67652066_20696d61; +defparam bootram.RAM5.INIT_39=256'h6f647563_64207072_56616c69_72652e00_726d7761_6e206669_6c742d69_20627569; +defparam bootram.RAM5.INIT_3A=256'h2e2e2e00_64696e67_204c6f61_756e642e_6520666f_6d776172_20666972_74696f6e; +defparam bootram.RAM5.INIT_3B=256'h6d616765_6e672069_61727469_2e205374_64696e67_206c6f61_73686564_46696e69; +defparam bootram.RAM5.INIT_3C=256'h70726f67_61696e20_6f6d206d_6e206672_65747572_523a2052_4552524f_2e000000; +defparam bootram.RAM5.INIT_3D=256'h6e210000_61707065_65722068_206e6576_6f756c64_73207368_20546869_72616d21; +defparam bootram.RAM5.INIT_3E=256'h20666f75_77617265_6669726d_696f6e20_64756374_2070726f_616c6964_4e6f2076; +defparam bootram.RAM5.INIT_3F=256'h2d696e20_75696c74_746f2062_75676820_7468726f_696e6720_46616c6c_6e642e20; +defparam bootram.RAM6.INIT_00=256'h00000000_2025640a_7420746f_64207365_53706565_2e000000_77617265_6669726d; +defparam bootram.RAM6.INIT_01=256'h45545249_53594d4d_58000000_57455f52_58000000_57455f54_00000000_4e4f4e45; +defparam bootram.RAM6.INIT_02=256'h5048595f_6c3a2000_6e74726f_7720636f_20666c6f_726e6574_65746865_43000000; +defparam bootram.RAM6.INIT_03=256'h20307825_20676f74_7825782c_74652030_2077726f_4144563a_4e45475f_4155544f; +defparam bootram.RAM6.INIT_04=256'h6e207570_6f722069_21457272_00030203_00000001_00030003_00000000_780a0000; +defparam bootram.RAM6.INIT_05=256'h64207061_65637465_20457870_6c65723a_68616e64_6b657420_20706163_64617465; +defparam bootram.RAM6.INIT_06=256'h00000000_2025640a_20676f74_20627574_2025642c_6e677468_64206c65_796c6f61; +defparam bootram.RAM6.INIT_07=256'h64756d6d_43444546_38394142_34353637_30313233_00000000_6f72740a_0a0a6162; +defparam bootram.RAM6.INIT_08=256'h00000000_00000000_ffffff00_ffff00ff_ff00ffff_00ffffff_65000000_792e6578; +defparam bootram.RAM6.INIT_09=256'hffff0031_05050400_01010100_3fff0000_0050c285_c0a80a02_0000316c_00000000; +defparam bootram.RAM6.INIT_0A=256'h000030fc_10101200_00003038_00003030_00003028_00003020_000b0000_0018000f; +defparam bootram.RAM6.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_ffffffff_00000000_ffffffff; +defparam bootram.RAM6.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM6.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_00=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_01=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_02=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_03=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_04=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_05=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_06=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_07=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_08=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_09=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_0F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_10=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_11=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_12=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_13=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_14=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_15=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_16=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_17=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_18=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_19=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_1F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_20=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_21=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_22=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_23=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_24=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_25=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_26=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_27=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_28=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_29=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_2F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_30=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_31=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_32=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_33=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_34=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_35=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_36=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_37=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_38=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_39=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3A=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3B=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3C=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3D=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3E=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; +defparam bootram.RAM7.INIT_3F=256'h00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000; diff --git a/fpga/usrp2/top/u2plus/u2plus_core.v b/fpga/usrp2/top/u2plus/u2plus_core.v index 22e181caf..ee5d7efcd 100644 --- a/fpga/usrp2/top/u2plus/u2plus_core.v +++ b/fpga/usrp2/top/u2plus/u2plus_core.v @@ -321,8 +321,8 @@ module u2plus_core // I-port connects directly to processor bootram bootram(.clk(wb_clk), .reset(wb_rst), - .if_adr(13'b0), .if_data(), - .dwb_adr_i(sf_adr[12:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), + .if_adr(14'b0), .if_data(), + .dwb_adr_i(sf_adr[13:0]), .dwb_dat_i(sf_dat_o), .dwb_dat_o(sf_dat_i), .dwb_we_i(sf_we), .dwb_ack_o(sf_ack), .dwb_stb_i(sf_stb), .dwb_sel_i(sf_sel)); ////blinkenlights v0.1 diff --git a/fpga/usrp2/vrt/trigger_context_pkt.v b/fpga/usrp2/vrt/trigger_context_pkt.v index 226ec45f2..1d456814b 100644 --- a/fpga/usrp2/vrt/trigger_context_pkt.v +++ b/fpga/usrp2/vrt/trigger_context_pkt.v @@ -10,7 +10,7 @@ module trigger_context_pkt wire [15:0] packets; wire [6:0] dummy1; wire [14:0] dummy2; - wire enable_timed, enable_consumed; + wire enable_cycle, enable_consumed; reg [30:0] cycle_count, packet_count; diff --git a/fpga/usrp2/vrt/vita_rx_chain.v b/fpga/usrp2/vrt/vita_rx_chain.v index d7498286d..28955d108 100644 --- a/fpga/usrp2/vrt/vita_rx_chain.v +++ b/fpga/usrp2/vrt/vita_rx_chain.v @@ -2,7 +2,8 @@ module vita_rx_chain #(parameter BASE=0, parameter UNIT=0, - parameter FIFOSIZE=10) + parameter FIFOSIZE=10, + parameter PROT_ENG_FLAGS=1) (input clk, input reset, input clear, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [63:0] vita_time, output overrun, @@ -15,7 +16,7 @@ module vita_rx_chain wire [31:0] vrc_debug, vrf_debug; wire [35:0] rx_data_int; - wire rx_src_rdy_int, rx_dst_rdy_in; + wire rx_src_rdy_int, rx_dst_rdy_int; vita_rx_control #(.BASE(BASE), .WIDTH(32)) vita_rx_control (.clk(clk), .reset(reset), .clear(clear), @@ -32,7 +33,9 @@ module vita_rx_chain .data_o(rx_data_int), .src_rdy_o(rx_src_rdy_int), .dst_rdy_i(rx_dst_rdy_int), .debug_rx(vrf_debug) ); - dsp_framer36 #(.BUF_SIZE(FIFOSIZE), .PORT_SEL(UNIT)) dsp0_framer36 + dsp_framer36 #(.BUF_SIZE(FIFOSIZE), + .PORT_SEL(UNIT), + .PROT_ENG_FLAGS(PROT_ENG_FLAGS)) dsp0_framer36 (.clk(clk), .reset(reset), .clear(clear), .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_o), .src_rdy_o(rx_src_rdy_o), .dst_rdy_i(rx_dst_rdy_i) ); diff --git a/fpga/usrp2/vrt/vita_tx_chain.v b/fpga/usrp2/vrt/vita_tx_chain.v index 6f567668d..fa84d7a2f 100644 --- a/fpga/usrp2/vrt/vita_tx_chain.v +++ b/fpga/usrp2/vrt/vita_tx_chain.v @@ -27,16 +27,17 @@ module vita_tx_chain wire trigger, sent; wire [31:0] debug_vtc, debug_vtd, debug_tx_dsp; - wire error, packet_consumed; + wire error, packet_consumed, ack; wire [31:0] error_code; wire clear_seqnum; wire [31:0] current_seqnum; + wire strobe_tx; assign underrun = error; assign message = error_code; setting_reg #(.my_addr(BASE_CTRL+1)) sr - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(),.changed(clear_vita)); setting_reg #(.my_addr(BASE_CTRL+2), .at_reset(0)) sr_streamid diff --git a/fpga/usrp2/vrt/vita_tx_control.v b/fpga/usrp2/vrt/vita_tx_control.v index e966d987c..14b97a215 100644 --- a/fpga/usrp2/vrt/vita_tx_control.v +++ b/fpga/usrp2/vrt/vita_tx_control.v @@ -71,7 +71,7 @@ module vita_tx_control wire [31:0] error_policy; setting_reg #(.my_addr(BASE+3)) sr_error_policy - (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr), + (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr), .in(set_data),.out(error_policy),.changed()); wire policy_wait = error_policy[0]; diff --git a/fpga/usrp2/vrt/vita_tx_deframer.v b/fpga/usrp2/vrt/vita_tx_deframer.v index eb39feaec..163c2af20 100644 --- a/fpga/usrp2/vrt/vita_tx_deframer.v +++ b/fpga/usrp2/vrt/vita_tx_deframer.v @@ -38,8 +38,8 @@ module vita_tx_deframer assign has_secs = ~(data_i[23:22]==2'b00); assign has_tics = ~(data_i[21:20]==2'b00); assign has_trailer = data_i[26]; - assign is_sob = data_i[25]; - assign is_eob = data_i[24]; + wire is_sob = data_i[25]; + wire is_eob = data_i[24]; wire eof = data_i[33]; reg has_streamid_reg, has_classid_reg, has_secs_reg, has_tics_reg; reg has_trailer_reg, is_sob_reg, is_eob_reg; diff --git a/host/lib/transport/gen_vrt_if_packet.py b/host/lib/transport/gen_vrt_if_packet.py index 8481932ed..7df2092d8 100755 --- a/host/lib/transport/gen_vrt_if_packet.py +++ b/host/lib/transport/gen_vrt_if_packet.py @@ -152,17 +152,11 @@ void vrt::if_hdr_unpack_$(suffix)( ){ //extract vrt header boost::uint32_t vrt_hdr_word = $(XE_MACRO)(packet_buff[0]); - /* size_t packet_words32 = vrt_hdr_word & 0xffff; //failure case if (if_packet_info.num_packet_words32 < packet_words32) throw uhd::value_error("bad vrt header or packet fragment"); - */ - //Fix for short packets sent from the fpga: - // Use the num_packet_words32 passed in as input, - // and do not use the header bits which could be wrong. - size_t packet_words32 = if_packet_info.num_packet_words32; //extract fields from the header if_packet_info.packet_type = if_packet_info_t::packet_type_t(vrt_hdr_word >> 29); diff --git a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp index ab3379dd5..318a75191 100644 --- a/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp +++ b/host/lib/usrp/usrp_e100/usrp_e100_impl.hpp @@ -33,7 +33,7 @@ uhd::transport::zero_copy_if::sptr usrp_e100_make_mmap_zero_copy(usrp_e100_iface::sptr iface); -static const boost::uint16_t USRP_E_FPGA_COMPAT_NUM = 0x03; +static const boost::uint16_t USRP_E_FPGA_COMPAT_NUM = 0x04; //! load an fpga image from a bin file into the usrp-e fpga extern void usrp_e100_load_fpga(const std::string &bin_file); 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