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| author | Josh Blum <josh@joshknows.com> | 2012-04-09 14:28:25 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2012-04-09 14:30:16 -0700 |
| commit | 00c241844a62c22cac538316d507c524acc1c393 (patch) | |
| tree | 710299bd0b928b5cf1471b84e9c7d42fa8ca8bcf | |
| parent | c8a2e4881f06212be7e10227220ebac33987143b (diff) | |
| download | uhd-00c241844a62c22cac538316d507c524acc1c393.tar.gz uhd-00c241844a62c22cac538316d507c524acc1c393.tar.bz2 uhd-00c241844a62c22cac538316d507c524acc1c393.zip | |
dsp: clear register now overlaps with numchan register.
This fixes the bug of unwanted clearing when setting format.
| -rw-r--r-- | host/lib/usrp/cores/rx_dsp_core_200.cpp | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/host/lib/usrp/cores/rx_dsp_core_200.cpp b/host/lib/usrp/cores/rx_dsp_core_200.cpp index 4b60f111c..cf8db1927 100644 --- a/host/lib/usrp/cores/rx_dsp_core_200.cpp +++ b/host/lib/usrp/cores/rx_dsp_core_200.cpp @@ -38,13 +38,12 @@ #define REG_RX_CTRL_STREAM_CMD _ctrl_base + 0 #define REG_RX_CTRL_TIME_HI _ctrl_base + 4 #define REG_RX_CTRL_TIME_LO _ctrl_base + 8 -#define REG_RX_CTRL_CLEAR _ctrl_base + 12 +#define REG_RX_CTRL_FORMAT _ctrl_base + 12 #define REG_RX_CTRL_VRT_HDR _ctrl_base + 16 #define REG_RX_CTRL_VRT_SID _ctrl_base + 20 #define REG_RX_CTRL_VRT_TLR _ctrl_base + 24 #define REG_RX_CTRL_NSAMPS_PP _ctrl_base + 28 #define REG_RX_CTRL_NCHANNELS _ctrl_base + 32 -#define REG_RX_CTRL_FORMAT REG_RX_CTRL_CLEAR //re-use clear address template <class T> T ceil_log2(T num){ return std::ceil(std::log(num)/std::log(T(2))); @@ -78,8 +77,7 @@ public: } void clear(void){ - _iface->poke32(REG_RX_CTRL_CLEAR, 1); //reset - _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); + _iface->poke32(REG_RX_CTRL_NCHANNELS, 1); //also reset _iface->poke32(REG_RX_CTRL_VRT_HDR, 0 | (0x1 << 28) //if data with stream id | (0x1 << 26) //has trailer |