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author | Matt Ettus <matt@ettus.com> | 2011-03-03 11:00:12 -0800 |
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committer | Matt Ettus <matt@ettus.com> | 2011-03-03 11:00:12 -0800 |
commit | 943113459cae9f3174f8d12c35add851439ac1a2 (patch) | |
tree | dfc86556fca0dd27f7bb75629a3f44d82c01aee3 | |
parent | 36a785b0ce6ddc7be26bff5d2bcd898be6626522 (diff) | |
download | uhd-943113459cae9f3174f8d12c35add851439ac1a2.tar.gz uhd-943113459cae9f3174f8d12c35add851439ac1a2.tar.bz2 uhd-943113459cae9f3174f8d12c35add851439ac1a2.zip |
u2/u2p: ll8 now all active high, removed extra shortfifo from eth wrapper
-rw-r--r-- | usrp2/fifo/ll8_to_fifo19.v | 14 | ||||
-rw-r--r-- | usrp2/simple_gemac/simple_gemac_wrapper19.v | 25 |
2 files changed, 10 insertions, 29 deletions
diff --git a/usrp2/fifo/ll8_to_fifo19.v b/usrp2/fifo/ll8_to_fifo19.v index 3c95c2374..71a8f5ac3 100644 --- a/usrp2/fifo/ll8_to_fifo19.v +++ b/usrp2/fifo/ll8_to_fifo19.v @@ -2,10 +2,10 @@ module ll8_to_fifo19 (input clk, input reset, input clear, input [7:0] ll_data, - input ll_sof_n, - input ll_eof_n, - input ll_src_rdy_n, - output ll_dst_rdy_n, + input ll_sof, + input ll_eof, + input ll_src_rdy, + output ll_dst_rdy, output [18:0] f19_data, output f19_src_rdy_o, @@ -18,13 +18,11 @@ module ll8_to_fifo19 ll8_shortfifo head_fifo (.clk(clk), .reset(reset), .clear(clear), - .datain(ll_data), .sof_i(~ll_sof_n), .eof_i(~ll_eof_n), - .error_i(0), .src_rdy_i(~ll_src_rdy_n), .dst_rdy_o(ll_dst_rdy), + .datain(ll_data), .sof_i(ll_sof), .eof_i(ll_eof), + .error_i(0), .src_rdy_i(ll_src_rdy), .dst_rdy_o(ll_dst_rdy), .dataout(ll_data_int), .sof_o(ll_sof_int), .eof_o(ll_eof_int), .error_o(), .src_rdy_o(ll_src_rdy_int), .dst_rdy_i(ll_dst_rdy_int)); - assign ll_dst_rdy_n = ~ll_dst_rdy; - // Actual ll8_to_fifo19 which could deadlock if not connected to a shortfifo localparam XFER_EMPTY = 0; localparam XFER_HALF = 1; diff --git a/usrp2/simple_gemac/simple_gemac_wrapper19.v b/usrp2/simple_gemac/simple_gemac_wrapper19.v index 6cdbd1a59..516cb3e2a 100644 --- a/usrp2/simple_gemac/simple_gemac_wrapper19.v +++ b/usrp2/simple_gemac/simple_gemac_wrapper19.v @@ -68,11 +68,7 @@ module simple_gemac_wrapper19 // RX FIFO Chain wire rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy; - - wire rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2; - wire rx_ll_sof2_n, rx_ll_eof2_n, rx_ll_src_rdy2_n, rx_ll_dst_rdy2_n; - - wire [7:0] rx_ll_data, rx_ll_data2; + wire [7:0] rx_ll_data; wire [18:0] rx_f19_data_int1; wire rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1; @@ -83,22 +79,10 @@ module simple_gemac_wrapper19 .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), .ll_error(), // error also encoded in sof/eof .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy)); - ll8_shortfifo rx_sfifo - (.clk(rx_clk), .reset(rx_reset), .clear(0), - .datain(rx_ll_data), .sof_i(rx_ll_sof), .eof_i(rx_ll_eof), - .error_i(0), .src_rdy_i(rx_ll_src_rdy), .dst_rdy_o(rx_ll_dst_rdy), - .dataout(rx_ll_data2), .sof_o(rx_ll_sof2), .eof_o(rx_ll_eof2), - .error_o(), .src_rdy_o(rx_ll_src_rdy2), .dst_rdy_i(rx_ll_dst_rdy2)); - - assign rx_ll_dst_rdy2 = ~rx_ll_dst_rdy2_n; - assign rx_ll_src_rdy2_n = ~rx_ll_src_rdy2; - assign rx_ll_sof2_n = ~rx_ll_sof2; - assign rx_ll_eof2_n = ~rx_ll_eof2; - ll8_to_fifo19 ll8_to_fifo19 (.clk(rx_clk), .reset(rx_reset), .clear(0), - .ll_data(rx_ll_data2), .ll_sof_n(rx_ll_sof2_n), .ll_eof_n(rx_ll_eof2_n), - .ll_src_rdy_n(rx_ll_src_rdy2_n), .ll_dst_rdy_n(rx_ll_dst_rdy2_n), + .ll_data(rx_ll_data), .ll_sof(rx_ll_sof), .ll_eof(rx_ll_eof), + .ll_src_rdy(rx_ll_src_rdy), .ll_dst_rdy(rx_ll_dst_rdy), .f19_data(rx_f19_data_int1), .f19_src_rdy_o(rx_f19_src_rdy_int1), .f19_dst_rdy_i(rx_f19_dst_rdy_int1)); //fifo_2clock_cascade #(.WIDTH(19), .SIZE(RXFIFOSIZE)) rx_2clk_fifo @@ -160,8 +144,7 @@ module simple_gemac_wrapper19 { tx_valid, tx_error, tx_ack, tx_f19_src_rdy_int1, tx_f19_dst_rdy_int1, tx_f19_data_int1[18:16]}, { tx_data} }; assign debug_rx = { { rx_f19_src_rdy, rx_f19_dst_rdy, debug_state[5:0] }, - { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, - rx_ll_sof2, rx_ll_eof2, rx_ll_src_rdy2, rx_ll_dst_rdy2 }, + { rx_ll_sof, rx_ll_eof, rx_ll_src_rdy, rx_ll_dst_rdy, 4'b0 }, { rx_valid, rx_error, rx_ack, rx_f19_src_rdy_int1, rx_f19_dst_rdy_int1, rx_f19_data_int1[18:16]}, { rx_data} }; |