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| author | Matt Ettus <matt@ettus.com> | 2011-08-23 17:58:10 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-08-26 13:23:43 -0700 |
| commit | 62ff57e24585359c6c216e59d3b01688140c02d5 (patch) | |
| tree | a05818aa78193f2cf9f76c28ae37e544ed62b913 | |
| parent | d5cbb77380d8f408469735b6ed6d4e10763d63b2 (diff) | |
| download | uhd-62ff57e24585359c6c216e59d3b01688140c02d5.tar.gz uhd-62ff57e24585359c6c216e59d3b01688140c02d5.tar.bz2 uhd-62ff57e24585359c6c216e59d3b01688140c02d5.zip | |
dsp: slow down the time constant of the DC offset correction by a factor of 16. it may need to be even slower.
| -rw-r--r-- | usrp2/sdr_lib/rx_dcoffset.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/sdr_lib/rx_dcoffset.v b/usrp2/sdr_lib/rx_dcoffset.v index e43461261..9840e9e1f 100644 --- a/usrp2/sdr_lib/rx_dcoffset.v +++ b/usrp2/sdr_lib/rx_dcoffset.v @@ -20,7 +20,7 @@ module rx_dcoffset #(parameter WIDTH=16, parameter ADDR=8'd0, - parameter alpha_shift=16) + parameter alpha_shift=20) (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, input [WIDTH-1:0] in, output [WIDTH-1:0] out); |