u1p: implement a signal to indicate a partially full usb lut, to flush it

7 files changed, 175 insertions, 22 deletions

diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index 007bb41b3..13a549dc7 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -5,7 +5,7 @@ module gpif
    (// GPIF signals
     input gpif_clk, input gpif_rst,
     inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy,
-    input [2:0] gpif_misc,
+    output [2:0] gpif_misc,
     
     // Wishbone signals
     input wb_clk, input wb_rst,
@@ -20,7 +20,7 @@ module gpif
     input [35:0] tx_err_data_i, input tx_err_src_rdy_i, output tx_err_dst_rdy_o,
     
     output tx_underrun, output rx_overrun,
-    input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl,
+    input [7:0] frames_per_packet, input [15:0] test_len, input [7:0] test_rate, input [3:0] test_ctrl,
     output [31:0] debug0, output [31:0] debug1
     );
 
@@ -103,13 +103,14 @@ module gpif
 
    packet_splitter #(.FRAME_LEN(256)) packet_splitter
      (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_rx),
+      .frames_per_packet(),
       .data_i(rx19_data), .src_rdy_i(rx19_src_rdy), .dst_rdy_o(rx19_dst_rdy),
       .data_o(splt_data), .src_rdy_o(splt_src_rdy), .dst_rdy_i(splt_dst_rdy));
      
    gpif_rd gpif_rd
      (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
       .gpif_data(gpif_d_out), .gpif_rd(RD), .gpif_ep(EP),
-      .gpif_empty_d(DE), .gpif_empty_c(CE),
+      .gpif_empty_d(DE), .gpif_empty_c(CE), .gpif_flush(gpif_misc[0]),
       
       .sys_clk(fifo_clk), .sys_rst(fifo_rst),
       .data_i(splt_data), .src_rdy_i(splt_src_rdy), .dst_rdy_o(splt_dst_rdy),
diff --git a/usrp2/gpif/gpif_rd.v b/usrp2/gpif/gpif_rd.v
index ed0721a36..728b8be78 100644
--- a/usrp2/gpif/gpif_rd.v
+++ b/usrp2/gpif/gpif_rd.v
@@ -3,6 +3,7 @@ module gpif_rd
   (input gpif_clk, input gpif_rst,
    output [15:0] gpif_data, input gpif_rd, input gpif_ep,
    output reg gpif_empty_d, output reg gpif_empty_c,
+   output reg gpif_flush,
    
    input sys_clk, input sys_rst,
    input [18:0] data_i, input src_rdy_i, output dst_rdy_o,
@@ -10,8 +11,9 @@ module gpif_rd
    output [31:0] debug
    );
    
-   wire [17:0] 	data_o, resp_o; // drop occ bit from input data
-   wire 	final_rdy_data, final_rdy_resp;
+   wire [18:0] 	 data_o; // occ bit indicates flush
+   wire [17:0] 	 resp_o; // no occ bit
+   wire 	 final_rdy_data, final_rdy_resp;
    
    // 33/257 Bug Fix
    reg [8:0] 	read_count;
@@ -24,10 +26,10 @@ module gpif_rd
        read_count <= 0;
 
    // Data Path
-   wire [17:0] 	data_int;
+   wire [18:0] 	data_int;
    wire 	src_rdy_int, dst_rdy_int;
-   fifo_2clock_cascade #(.WIDTH(18), .SIZE(4)) rd_fifo_2clk
-     (.wclk(sys_clk), .datain(data_i[17:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
+   fifo_2clock_cascade #(.WIDTH(19), .SIZE(4)) rd_fifo_2clk
+     (.wclk(sys_clk), .datain(data_i[18:0]), .src_rdy_i(src_rdy_i), .dst_rdy_o(dst_rdy_o), .space(),
       .rclk(~gpif_clk), .dataout(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .occupied(),
       .arst(sys_rst));
 
@@ -37,7 +39,7 @@ module gpif_rd
    wire 	consume_sop = consume_data_line & final_rdy_data & data_o[16];
    wire 	consume_eop = consume_data_line & final_rdy_data & data_o[17];
    
-   fifo_cascade #(.WIDTH(18), .SIZE(10)) rd_fifo
+   fifo_cascade #(.WIDTH(19), .SIZE(10)) rd_fifo
      (.clk(~gpif_clk), .reset(gpif_rst), .clear(0),
       .datain(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), .space(),
       .dataout(data_o), .src_rdy_o(final_rdy_data), .dst_rdy_i(consume_data_line), .occupied());
@@ -56,7 +58,14 @@ module gpif_rd
        gpif_empty_d <= 1;
      else
        gpif_empty_d <= ~|packet_count;
-   	      
+
+   // Use occ bit to signal a gpif flush
+   always @(negedge gpif_clk)
+     if(gpif_rst)
+       gpif_flush <= 0;
+     else if(consume_eop & data_o[18])
+       gpif_flush <= ~gpif_flush;
+   
    // Response Path
    wire [15:0] 	resp_fifolevel;
    wire 	consume_resp_line = gpif_rd & gpif_ep & ~read_count[4];
diff --git a/usrp2/gpif/gpif_tb.v b/usrp2/gpif/gpif_tb.v
index a71796d86..fe12c83b3 100644
--- a/usrp2/gpif/gpif_tb.v
+++ b/usrp2/gpif/gpif_tb.v
@@ -47,6 +47,7 @@ module gpif_tb();
 
    packet_splitter #(.FRAME_LEN(256)) rx_packet_splitter
      (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .frames_per_packet(2),
       .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
       .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt));
 
diff --git a/usrp2/gpif/packet_splitter.v b/usrp2/gpif/packet_splitter.v
index f8028a4df..1c289c2fa 100644
--- a/usrp2/gpif/packet_splitter.v
+++ b/usrp2/gpif/packet_splitter.v
@@ -4,6 +4,7 @@
 module packet_splitter
   #(parameter FRAME_LEN=256)
    (input clk, input reset, input clear,
+    input  [7:0] frames_per_packet,
     input [18:0] data_i,
     input src_rdy_i,
     output dst_rdy_o,
@@ -14,6 +15,7 @@ module packet_splitter
    reg [1:0] state;
    reg [15:0] length;
    reg [15:0] frame_len;
+   reg [7:0]  frame_count;
    
    localparam PS_IDLE = 0;
    localparam PS_FRAME = 1;
@@ -24,7 +26,10 @@ module packet_splitter
    
    always @(posedge clk)
      if(reset | clear)
-       state <= PS_IDLE;
+       begin
+	  state <= PS_IDLE;
+	  frame_count <= 0;
+       end
      else
        case(state)
 	 PS_IDLE :
@@ -33,6 +38,7 @@ module packet_splitter
 		length <= { data_i[14:0],1'b0};
 		frame_len <= FRAME_LEN;
 		state <= PS_FRAME;
+		frame_count <= 1;
 	     end
 	 PS_FRAME :
 	   if(src_rdy_i & dst_rdy_i)
@@ -40,8 +46,9 @@ module packet_splitter
 	       state <= PS_IDLE;
 	     else if(frame_len == 2)
 	       begin
-		  state <= PS_NEW_FRAME;
 		  length <= length - 1;
+		  state <= PS_NEW_FRAME;
+		  frame_count <= frame_count + 1;
 	       end
 	     else if((length == 2)|eof_i)
 	       begin
@@ -57,9 +64,15 @@ module packet_splitter
 	   if(src_rdy_i & dst_rdy_i)
 	     begin
 		frame_len <= FRAME_LEN;
-		state <= PS_FRAME;
-		length <= length - 1;
-	     end
+		if((length == 2)|eof_i)
+		  state <= PS_PAD;
+		else
+		  begin
+		     state <= PS_FRAME;
+		     length <= length - 1;
+		  end // else: !if((length == 2)|eof_i)
+	     end // if (src_rdy_i & dst_rdy_i)
+	 
 	 PS_PAD :
 	   if(dst_rdy_i)
 	     if(frame_len == 2)
@@ -68,16 +81,20 @@ module packet_splitter
 	       frame_len <= frame_len - 1;
 
        endcase // case (state)
-   
+
+   wire next_state_is_idle = dst_rdy_i & (frame_len==2) & 
+	( (state==PS_PAD) | ( (state==PS_FRAME) & src_rdy_i & ((length==2)|eof_i) ) );
+	  
+	 
 	
    
    assign dst_rdy_o = dst_rdy_i & (state != PS_PAD);
    assign src_rdy_o = src_rdy_i | (state == PS_PAD);
    
-   wire occ_out = 0;
    wire eof_out = (frame_len == 2) & (state != PS_IDLE) & (state != PS_NEW_FRAME);
    wire sof_out = (state == PS_IDLE) | (state == PS_NEW_FRAME);
-
+   wire occ_out = eof_out & next_state_is_idle & (frames_per_packet != frame_count);
+   
    wire [15:0] data_out = data_i[15:0];
    assign data_o = {occ_out, eof_out, sof_out, data_out};
    
diff --git a/usrp2/gpif/packet_splitter_tb.v b/usrp2/gpif/packet_splitter_tb.v
new file mode 100644
index 000000000..d35f1c6d4
--- /dev/null
+++ b/usrp2/gpif/packet_splitter_tb.v
@@ -0,0 +1,120 @@
+
+module packet_splitter_tb();
+   
+   reg sys_clk = 0;
+   reg sys_rst = 1;
+   reg gpif_clk = 0;
+   reg gpif_rst = 1;
+      
+   reg [15:0] gpif_data;
+   reg 	      WR = 0, EP = 0;
+
+   wire       CF, DF;
+   
+   wire       gpif_full_d, gpif_full_c;
+   wire [18:0] data_o, ctrl_o, data_splt;
+   wire        src_rdy, dst_rdy, src_rdy_splt, dst_rdy_splt;
+   wire        ctrl_src_rdy, ctrl_dst_rdy;
+
+   assign ctrl_dst_rdy = 1;
+   
+   initial $dumpfile("packet_splitter_tb.vcd");
+   initial $dumpvars(0,packet_splitter_tb);
+
+   initial #1000 gpif_rst = 0;
+   initial #1000 sys_rst = 0;
+   always #64 gpif_clk <= ~gpif_clk;
+   always #47.9 sys_clk <= ~sys_clk;
+
+   wire [35:0] data_int;
+   wire        src_rdy_int, dst_rdy_int;
+
+   assign dst_rdy_splt = 1;
+
+   vita_pkt_gen vita_pkt_gen
+     (.clk(sys_clk), .reset(sys_rst) , .clear(0),
+      .len(7),.data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int));
+
+   fifo36_to_fifo19 #(.LE(1)) f36_to_f19
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .f36_datain(data_int), .f36_src_rdy_i(src_rdy_int), .f36_dst_rdy_o(dst_rdy_int),
+      .f19_dataout(data_o), .f19_src_rdy_o(src_rdy), .f19_dst_rdy_i(dst_rdy));
+   		 
+   packet_splitter #(.FRAME_LEN(13)) rx_packet_splitter
+     (.clk(sys_clk), .reset(sys_rst), .clear(0),
+      .frames_per_packet(3),
+      .data_i(data_o), .src_rdy_i(src_rdy), .dst_rdy_o(dst_rdy),
+      .data_o(data_splt), .src_rdy_o(src_rdy_splt), .dst_rdy_i(dst_rdy_splt));
+
+   always @(posedge sys_clk)
+     if(ctrl_src_rdy & ctrl_dst_rdy)
+       $display("CTRL: %x",ctrl_o);
+
+   always @(posedge sys_clk)
+     if(src_rdy_splt & dst_rdy_splt)
+       begin
+	  if(data_splt[16])
+	    $display("<-------- DATA SOF--------->");
+	  $display("DATA: %x",data_splt);
+	  if(data_splt[17])
+	    $display("<-------- DATA EOF--------->");
+       end
+   
+   initial
+     begin
+	#10000;
+	repeat (1)
+	  begin
+	     @(posedge gpif_clk);
+	     
+	     WR <= 1;
+	     gpif_data <= 256;  // Length
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data + 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+
+	     while(DF)
+	       @(posedge gpif_clk);
+	     repeat (16)
+	       @(posedge gpif_clk);
+	     
+	     WR <= 1;
+	     repeat(256)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+
+
+/*
+	     while(DF)
+	       @(posedge gpif_clk);
+	     	     
+	     repeat (20)
+	       @(posedge gpif_clk);
+	     WR <= 1;
+	     gpif_data <= 16'h5;
+	     @(posedge gpif_clk);
+	     gpif_data <= 16'h00;
+	     @(posedge gpif_clk);
+	     repeat(254)
+	       begin
+		  gpif_data <= gpif_data - 1;
+		  @(posedge gpif_clk);
+	       end
+	     WR <= 0;
+ */
+	  end
+     end // initial begin
+   
+   initial #200000 $finish;
+   
+     
+endmodule // packet_splitter_tb
diff --git a/usrp2/top/u1plus/u1plus.v b/usrp2/top/u1plus/u1plus.v
index 9d52353db..7e1bd2ea7 100644
--- a/usrp2/top/u1plus/u1plus.v
+++ b/usrp2/top/u1plus/u1plus.v
@@ -8,7 +8,7 @@ module u1plus
 
    // GPIF
    inout [15:0] GPIF_D, input [3:0] GPIF_CTL, output [3:0] GPIF_RDY,
-   input FX2_PA7_FLAGD, input FX2_PA6_PKTEND, input FX2_PA2_SLOE,
+   output FX2_PA7_FLAGD, output FX2_PA6_PKTEND, output FX2_PA2_SLOE,
    input IFCLK,
    
    inout SDA_FPGA, inout SCL_FPGA, // I2C
@@ -141,7 +141,7 @@ module u1plus
 		     .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .debug_txd(FPGA_TXD), .debug_rxd(FPGA_RXD),
 		     .gpif_d(GPIF_D), .gpif_ctl(GPIF_CTL), .gpif_rdy(GPIF_RDY),
-		     .gpif_misc({FX2_PA7_FLAGD,FX_PA6_PKTEND,FX2_PA2_SLOE}),
+		     .gpif_misc({FX2_PA7_FLAGD,FX2_PA6_PKTEND,FX2_PA2_SLOE}),
 		     .gpif_clk(IFCLK),
 
 		     .db_sda(SDA_FPGA), .db_scl(SCL_FPGA),
diff --git a/usrp2/top/u1plus/u1plus_core.v b/usrp2/top/u1plus/u1plus_core.v
index 76a15b271..a2147e463 100644
--- a/usrp2/top/u1plus/u1plus_core.v
+++ b/usrp2/top/u1plus/u1plus_core.v
@@ -7,7 +7,7 @@ module u1plus_core
    
    // GPIF
    inout [15:0] gpif_d, input [3:0] gpif_ctl, output [3:0] gpif_rdy,
-   input [2:0] gpif_misc, input gpif_clk,
+   output [2:0] gpif_misc, input gpif_clk,
    
    inout db_sda, inout db_scl,
    output sclk, output [15:0] sen, output mosi, input miso,
@@ -54,6 +54,8 @@ module u1plus_core
 
    wire [31:0] 	debug_vt;
    wire 	rx_overrun_dsp, rx_overrun_gpmc, tx_underrun_dsp, tx_underrun_gpmc;
+   reg [7:0] 	frames_per_packet;
+   
    assign rx_overrun = rx_overrun_gpmc | rx_overrun_dsp;
    assign tx_underrun = tx_underrun_gpmc | tx_underrun_dsp;
    
@@ -109,7 +111,7 @@ module u1plus_core
 	 
 	 .tx_underrun(tx_underrun_gpmc), .rx_overrun(rx_overrun_gpmc),
 
-	 .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl),
+	 .frames_per_packet(frames_per_packet), .test_len(test_len), .test_rate(test_rate), .test_ctrl(test_ctrl),
 	 .debug0(debug0), .debug1(debug1));
 
    // /////////////////////////////////////////////////////////////////////////
@@ -243,6 +245,7 @@ module u1plus_core
 	  reg_cgen_ctrl <= 2'b11;
 	  reg_test <= 0;
 	  xfer_rate <= 0;
+	  frames_per_packet <= 0;
        end
      else
        if(s0_cyc & s0_stb & s0_we) 
@@ -253,6 +256,8 @@ module u1plus_core
 	     reg_cgen_ctrl <= s0_dat_mosi;
 	   REG_TEST :
 	     reg_test <= s0_dat_mosi;
+	   REG_RX_FRAMELEN :
+	     frames_per_packet <= s0_dat_mosi[7:0];
 	   REG_XFER_RATE :
 	     xfer_rate <= s0_dat_mosi;
 	 endcase // case (s0_adr[6:0])