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authorMatt Ettus <matt@ettus.com>2010-04-14 18:02:29 -0700
committerMatt Ettus <matt@ettus.com>2010-04-14 18:02:29 -0700
commit17fc80cb82309879dd2b1dc03681058dd432327b (patch)
treeb2406f9f8c5c41e6a55c768b930f53f195c7be4f
parent8cef80c8ebb9b59f1fe65971c9066fd832ab2504 (diff)
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added in a loopback fifo
-rw-r--r--usrp2/top/u1e/u1e_core.v15
1 files changed, 11 insertions, 4 deletions
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index e5e5285bd..7df7b0a48 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -32,6 +32,9 @@ module u1e_core
wire [31:0] debug_gpmc;
+ wire [35:0] tx_data, rx_data;
+ wire tx_src_rdy, tx_dst_rdy, rx_src_rdy, rx_dst_rdy;
+
gpmc gpmc (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
.EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), .EM_NWE(EM_NWE),
.EM_NOE(EM_NOE),
@@ -44,12 +47,16 @@ module u1e_core
.wb_ack_i(m0_ack),
.fifo_clk(wb_clk), .fifo_rst(wb_rst),
- .tx_data_o(), .tx_src_rdy_o(), .tx_dst_rdy_i(0),
- .rx_data_i(0), .rx_src_rdy_i(0), .rx_dst_rdy_o(),
+ .tx_data_o(tx_data), .tx_src_rdy_o(tx_src_rdy), .tx_dst_rdy_i(tx_dst_rdy),
+ .rx_data_i(rx_data), .rx_src_rdy_i(rx_src_rdy), .rx_dst_rdy_o(rx_dst_rdy),
.debug(debug_gpmc));
-
-
+
+ fifo_cascade #(.WIDTH(36), .SIZE(9)) loopback_fifo
+ (.clk(wb_clk), .reset(wb_rst), .clear(0),
+ .datain(tx_data), .src_rdy_i(tx_src_rdy), .dst_rdy_o(tx_dst_rdy),
+ .dataout(rx_data), .src_rdy_o(rx_src_rdy), .dst_rdy_i(rx_dst_rdy));
+
// /////////////////////////////////////////////////////////////////////////////////////
// Wishbone Intercon, single master
wire [dw-1:0] s0_dat_mosi, s1_dat_mosi, s0_dat_miso, s1_dat_miso, s2_dat_mosi, s3_dat_mosi, s2_dat_miso, s3_dat_miso,