fifo randomizer for emi

5 files changed, 108 insertions, 4 deletions

diff --git a/usrp2/extramfifo/Makefile.srcs b/usrp2/extramfifo/Makefile.srcs
index 7cd49f4f6..b255ef916 100644
--- a/usrp2/extramfifo/Makefile.srcs
+++ b/usrp2/extramfifo/Makefile.srcs
@@ -13,4 +13,5 @@ icon.v \
 icon.xco \
 ila.v \
 ila.xco \
+refill_randomizer.v \
 ))
diff --git a/usrp2/extramfifo/ext_fifo.v b/usrp2/extramfifo/ext_fifo.v
index daf7140bc..80f82fc63 100644
--- a/usrp2/extramfifo/ext_fifo.v
+++ b/usrp2/extramfifo/ext_fifo.v
@@ -45,7 +45,7 @@ module ext_fifo
    wire [EXT_WIDTH-1:0] write_data;
    wire [EXT_WIDTH-1:0] read_data;
    wire 		full1, empty1;
-   wire 		almost_full2, full2, empty2;
+   wire 		almost_full2, almost_full2_spread, full2, empty2;
    wire [FIFO_DEPTH-1:0] capacity;
    wire 		 space_avail;
    wire 		 data_avail;
@@ -83,7 +83,7 @@ module ext_fifo
 	   .write_strobe(~empty1 ),
 	   .space_avail(space_avail),
 	   .read_data(read_data),
-	   .read_strobe(~almost_full2),
+	   .read_strobe(~almost_full2_spread),
 	   .data_avail(data_avail),
 	   .capacity(capacity)
 	   );
@@ -148,6 +148,13 @@ module ext_fifo
    endgenerate
    
 
+   refill_randomizer #(.BITS(7))
+     refill_randomizer_i1 (
+			   .clk(ext_clk),
+			   .rst(rst),
+			   .full_in(almost_full2),
+			   .full_out(almost_full2_spread)
+			   );
    
 //   always @ (posedge int_clk)
 //     debug[31:28] <= {empty2,full1,dst_rdy_i,src_rdy_i };
diff --git a/usrp2/extramfifo/ext_fifo_tb.sav b/usrp2/extramfifo/ext_fifo_tb.sav
new file mode 100644
index 000000000..a54b40fc5
--- /dev/null
+++ b/usrp2/extramfifo/ext_fifo_tb.sav
@@ -0,0 +1,30 @@
+[timestart] 0
+[size] 1523 832
+[pos] -1 -1
+*-15.000000 66300 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] ext_fifo_tb.
+[treeopen] ext_fifo_tb.ext_fifo_i1.
+[treeopen] ext_fifo_tb.ext_fifo_i1.nobl_fifo_i1.
+@28
+ext_fifo_tb.ext_fifo_i1.src_rdy_i
+ext_fifo_tb.ext_fifo_i1.dst_rdy_o
+@22
+ext_fifo_tb.ext_fifo_i1.datain[35:0]
+@28
+ext_fifo_tb.ext_fifo_i1.src_rdy_o
+ext_fifo_tb.ext_fifo_i1.dst_rdy_i
+@22
+ext_fifo_tb.ext_fifo_i1.dataout[35:0]
+ext_fifo_tb.ext_fifo_i1.RAM_A[17:0]
+@28
+ext_fifo_tb.ext_fifo_i1.RAM_WEn
+ext_fifo_tb.ext_fifo_i1.RAM_CE1n
+@22
+ext_fifo_tb.ext_fifo_i1.RAM_D_pi[35:0]
+ext_fifo_tb.ext_fifo_i1.RAM_D_po[35:0]
+ext_fifo_tb.ext_fifo_i1.write_data[35:0]
+@28
+ext_fifo_tb.ext_fifo_i1.full1
+ext_fifo_tb.ext_fifo_i1.empty1
+@29
+ext_fifo_tb.ext_fifo_i1.space_avail
diff --git a/usrp2/extramfifo/ext_fifo_tb.v b/usrp2/extramfifo/ext_fifo_tb.v
index 5f4e28719..395ad2884 100644
--- a/usrp2/extramfifo/ext_fifo_tb.v
+++ b/usrp2/extramfifo/ext_fifo_tb.v
@@ -1,6 +1,6 @@
 `timescale 1ns / 1ps
-//`define USRP2
-`define USRP2PLUS
+`define USRP2
+//`define USRP2PLUS
 
 `ifdef USRP2
  `define INT_WIDTH 36
diff --git a/usrp2/extramfifo/refill_randomizer.v b/usrp2/extramfifo/refill_randomizer.v
new file mode 100644
index 000000000..0b30f4049
--- /dev/null
+++ b/usrp2/extramfifo/refill_randomizer.v
@@ -0,0 +1,66 @@
+//
+// EMI mitigation.
+// Process FULL flag from FIFO so that de-assertion
+// (FIFO now not FULL) is delayed by a pseudo random
+// value, but assertion is passed straight through.
+// 
+
+
+module refill_randomizer
+  #(parameter BITS=7)
+    (
+     input clk,
+     input rst,
+     input full_in,
+     output full_out
+     );
+   
+   wire 	    feedback;
+   reg 	    full_last;
+   wire     full_deasserts;
+   reg [6:0] shift_reg;
+   reg [6:0] count;
+   reg 	     delayed_fall;
+   
+
+   always @(posedge clk)
+     full_last <= full_in;
+   
+   assign    full_deasserts = full_last & ~full_in;
+
+   // 7 bit LFSR
+   always @(posedge clk)
+     if (rst)
+       shift_reg <= 7'b1;
+     else
+       if (full_deasserts)
+	 shift_reg <= {shift_reg[5:0],feedback};
+
+   assign    feedback = ^(shift_reg & 7'h41);
+
+   always @(posedge clk)
+     if (rst)
+       begin
+	  count <= 1;
+	  delayed_fall  <= 1;
+       end
+     else if (full_deasserts)
+       begin
+	  count <= shift_reg;
+	  delayed_fall <= 1;
+       end
+     else if (count == 1)
+       begin
+	  count <= 1;
+	  delayed_fall <= 0;
+       end
+     else
+       begin
+	  count <= count - 1;
+	  delayed_fall <= 1;
+       end
+   
+   // Full_out goes instantly high if full_in does. However its fall is delayed.
+   assign    full_out = (full_in == 1) || (full_last == 1) || delayed_fall;
+
+endmodule
\ No newline at end of file