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| author | Matt Ettus <matt@ettus.com> | 2010-12-28 15:43:48 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-12-28 15:43:48 -0800 |
| commit | 1154d5bebd2871fe7f92af7490ab4a9874b65a00 (patch) | |
| tree | 512ba8286e4a19a3c83cbd122b2ef3bd950845ca | |
| parent | 8d6e6985f9f8e6e965621ca7ae40b4b89583fd45 (diff) | |
| download | uhd-1154d5bebd2871fe7f92af7490ab4a9874b65a00.tar.gz uhd-1154d5bebd2871fe7f92af7490ab4a9874b65a00.tar.bz2 uhd-1154d5bebd2871fe7f92af7490ab4a9874b65a00.zip | |
reformatting
| -rw-r--r-- | usrp2/fifo/buffer_int2.v | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/usrp2/fifo/buffer_int2.v b/usrp2/fifo/buffer_int2.v index 2ab94f589..fab3ac314 100644 --- a/usrp2/fifo/buffer_int2.v +++ b/usrp2/fifo/buffer_int2.v @@ -6,13 +6,9 @@ module buffer_int2 #(parameter BASE = 0, parameter BUF_SIZE = 9) - (// Control Interface - input clk, - input rst, - + (input clk, input rst, input set_stb, input [7:0] set_addr, input [31:0] set_data, output [31:0] status, - output sys_int_o, // unused // Wishbone interface to RAM input wb_clk_i, |