Merge branch 'reload' into ise12

* reload:
  fix to stop endless error packets
  updated tests to match new features
  error packets are now valid Extension Context packets error packets don't have a trailer any more streamid is now optional on data packets, set by header register trailer now has a bit to indicate successful End-of-burst hard-coded some header bits to correct values to ensure valid packets
  reload bit for vita rx ctrl

4 files changed, 59 insertions, 22 deletions

diff --git a/usrp2/vrt/vita_rx.build b/usrp2/vrt/vita_rx.build
index f6d2d75a3..010d1be6e 100755
--- a/usrp2/vrt/vita_rx.build
+++ b/usrp2/vrt/vita_rx.build
@@ -1 +1 @@
-iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../control_lib/newfifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
+iverilog -Wimplict -Wportbind -y ../models -y . -y ../control_lib/ -y ../fifo -y ../coregen -y /opt/Xilinx/10.1/ISE/verilog/src/XilinxCoreLib -y /opt/Xilinx/10.1/ISE/verilog/src/unisims/ -y ../timing -o vita_rx_tb vita_rx_tb.v
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index 669b8299d..93673d292 100644
--- a/usrp2/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
@@ -31,13 +31,13 @@ module vita_rx_control
    
    wire [63:0] 	  rcvtime_pre;
    reg [63:0] 	  rcvtime;
-   wire [29:0] 	  numlines_pre;
-   wire 	  send_imm_pre, chain_pre;
-   reg 		  send_imm, chain;
+   wire [28:0] 	  numlines_pre;
+   wire 	  send_imm_pre, chain_pre, reload_pre;
+   reg 		  send_imm, chain, reload;
    wire 	  full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
    reg 		  sc_pre2;
    wire [33:0] 	  fifo_line;
-   reg [29:0] 	  lines_left;
+   reg [28:0] 	  lines_left, lines_total;
    reg [2:0] 	  ibs_state;
    wire 	  now, early, late;
    wire 	  sample_fifo_in_rdy;
@@ -67,7 +67,7 @@ module vita_rx_control
    shortfifo #(.WIDTH(96)) commandfifo
      (.clk(clk),.rst(reset),.clear(clear_int),
       .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
-      .dataout({send_imm_pre,chain_pre,numlines_pre,rcvtime_pre}), 
+      .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
       .read(read_ctrl), .empty(empty_ctrl),
       .occupied(command_queue_len), .space() );
    
@@ -111,9 +111,11 @@ module vita_rx_control
        begin
 	  ibs_state 	   <= IBS_IDLE;
 	  lines_left 	   <= 0;
+	  lines_total	   <= 0;
 	  rcvtime 	   <= 0;
 	  send_imm 	   <= 0;
 	  chain 	   <= 0;
+	  reload	   <= 0;
        end
      else
        case(ibs_state)
@@ -121,10 +123,12 @@ module vita_rx_control
 	   if(~empty_ctrl)
 	     begin
 		lines_left <= numlines_pre;
+		lines_total <= numlines_pre;
 		rcvtime <= rcvtime_pre;
 		ibs_state <= IBS_WAITING;
 		send_imm <= send_imm_pre;
 		chain <= chain_pre;
+		reload <= reload_pre;
 	     end
 	 IBS_WAITING :
 	   if(go_now)
@@ -141,14 +145,21 @@ module vita_rx_control
 		  if(lines_left == 1)
 		    if(~chain)
 		      ibs_state      <= IBS_IDLE;
+		    else if(empty_ctrl & reload)
+		      begin
+		        ibs_state      <= IBS_RUNNING;
+		        lines_left     <= lines_total;
+		      end
 		    else if(empty_ctrl)
 		      ibs_state      <= IBS_BROKENCHAIN;
 		    else
 		      begin
 			 lines_left  <= numlines_pre;
+			 lines_total <= numlines_pre;
 			 rcvtime     <= rcvtime_pre;
 			 send_imm    <= send_imm_pre;
 			 chain 	     <= chain_pre;
+			 reload      <= reload_pre;
 			 if(numlines_pre == 0)  // If we are told to stop here
 			   ibs_state <= IBS_IDLE;
 			 else
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index f3a81664a..fd82263d0 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -99,7 +99,7 @@ module vita_rx_framer
    localparam VITA_ERR_TICS 	 = 12;
    localparam VITA_ERR_TICS2 	 = 13;
    localparam VITA_ERR_PAYLOAD 	 = 14;
-   localparam VITA_ERR_TRAILER 	 = 15;
+   localparam VITA_ERR_TRAILER 	 = 15; // Extension context packets have no trailer
       
    always @(posedge clk)
      if(reset | clear_pkt_count)
@@ -107,17 +107,30 @@ module vita_rx_framer
      else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
        pkt_count <= pkt_count + 1;
 
+   wire 	  has_streamid = vita_header[28];
+   wire 	  has_trailer = vita_header[26];
+   reg 		  trl_eob;
+   
    always @*
      case(vita_state)
-       VITA_HEADER, VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,vita_header[31:20],pkt_count,vita_pkt_len};
-       VITA_STREAMID, VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
-       VITA_SECS, VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
-       VITA_TICS, VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
-       VITA_TICS2, VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+       // Data packets are IF Data packets with or w/o streamid, no classid, with trailer
+       VITA_HEADER : pkt_fifo_line <= {2'b01,3'b000,vita_header[28],2'b01,vita_header[25:20],pkt_count,vita_pkt_len};
+       VITA_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+       VITA_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+       VITA_TICS : pkt_fifo_line <= {2'b00,32'd0};
+       VITA_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
        VITA_PAYLOAD : pkt_fifo_line <= {2'b00,data_fifo_o};
-       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b00,28'd0,flags_fifo_o};
-       VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer};
-       VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+       VITA_TRAILER : pkt_fifo_line <= {2'b10,vita_trailer[31:21],1'b1,vita_trailer[19:9],trl_eob,8'd0};
+
+       // Error packets are Extension Context packets, which have no trailer
+       VITA_ERR_HEADER : pkt_fifo_line <= {2'b01,4'b0101,4'b0000,vita_header[23:20],pkt_count,16'd6};
+       VITA_ERR_STREAMID : pkt_fifo_line <= {2'b00,vita_streamid};
+       VITA_ERR_SECS : pkt_fifo_line <= {2'b00,vita_time_fifo_o[63:32]};
+       VITA_ERR_TICS : pkt_fifo_line <= {2'b00,32'd0};
+       VITA_ERR_TICS2 : pkt_fifo_line <= {2'b00,vita_time_fifo_o[31:0]};
+       VITA_ERR_PAYLOAD : pkt_fifo_line <= {2'b11,28'd0,flags_fifo_o};
+       //VITA_ERR_TRAILER : pkt_fifo_line <= {2'b11,vita_trailer};
+       
        default : pkt_fifo_line <= 34'h0_FFFF_FFFF;
        endcase // case (vita_state)
 
@@ -141,6 +154,11 @@ module vita_rx_framer
 	 end
        else if(pkt_fifo_rdy)
 	 case(vita_state)
+	   VITA_HEADER :
+	     if(has_streamid)
+	       vita_state <= VITA_STREAMID;
+	     else
+	       vita_state <= VITA_SECS;
 	   VITA_PAYLOAD :
 	     if(sample_fifo_src_rdy_i)
 	       begin
@@ -148,6 +166,7 @@ module vita_rx_framer
 		    begin
 		       sample_phase <= 0;
 		       sample_ctr   <= sample_ctr + 1;
+		       trl_eob <= flags_fifo_o[0];
 		       if(sample_ctr == samples_per_packet)
 			 vita_state <= VITA_TRAILER;
 		       if(|flags_fifo_o)   // end early if any flag is set
@@ -155,8 +174,10 @@ module vita_rx_framer
 		    end
 		  else
 		    sample_phase <= sample_phase + 1;
-	       end
-	   VITA_TRAILER, VITA_ERR_TRAILER :
+	       end // if (sample_fifo_src_rdy_i)
+	   VITA_ERR_PAYLOAD :
+	     vita_state <= VITA_IDLE;
+	   VITA_TRAILER :
 	     vita_state <= VITA_IDLE;
 	   default :
 	     vita_state 	   <= vita_state + 1;
@@ -172,7 +193,7 @@ module vita_rx_framer
        VITA_PAYLOAD :
 	 // Write if sample ready and no error flags
      	 req_write_pkt_fifo <= (sample_fifo_src_rdy_i & ~|flags_fifo_o[3:1]);
-       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD, VITA_ERR_TRAILER :
+       VITA_ERR_HEADER, VITA_ERR_STREAMID, VITA_ERR_SECS, VITA_ERR_TICS, VITA_ERR_TICS2, VITA_ERR_PAYLOAD :
 	 req_write_pkt_fifo <= 1;
        default :
 	 req_write_pkt_fifo <= 0;
@@ -192,7 +213,7 @@ module vita_rx_framer
 				   ( ((vita_state==VITA_PAYLOAD) & 
 				      (sample_phase == (numchan-4'd1)) & 
 				      ~|flags_fifo_o[3:1]) |
-				     (vita_state==VITA_ERR_TRAILER));
+				     (vita_state==VITA_ERR_PAYLOAD));
    
    assign debug_rx  = vita_state;
    
diff --git a/usrp2/vrt/vita_rx_tb.v b/usrp2/vrt/vita_rx_tb.v
index b4fda9622..3e01e2ee2 100644
--- a/usrp2/vrt/vita_rx_tb.v
+++ b/usrp2/vrt/vita_rx_tb.v
@@ -3,8 +3,8 @@
 module vita_rx_tb;
 
    localparam DECIM  = 8'd4;
-   localparam MAXCHAN=4;
-   localparam NUMCHAN=4;
+   localparam MAXCHAN=1;
+   localparam NUMCHAN=1;
    
    reg clk 	     = 0;
    reg reset 	     = 1;
@@ -94,7 +94,7 @@ module vita_rx_tb;
 	@(posedge clk);
 	write_setting(4,32'hDEADBEEF);  // VITA header
 	write_setting(5,32'hF00D1234);  // VITA streamid
-	write_setting(6,32'h98765432);  // VITA trailer
+	write_setting(6,32'hF0000000);  // VITA trailer
 	write_setting(7,8);  // Samples per VITA packet
 	write_setting(8,NUMCHAN);  // Samples per VITA packet
 	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
@@ -111,8 +111,13 @@ module vita_rx_tb;
 	queue_rx_cmd(0,0,8,32'h0,32'h340);  // send at, on time
 	queue_rx_cmd(0,0,8,32'h0,32'h100);  // send at, but late
 
+	#100000;
+	$display("\nChained, break chain\n");
 	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained, but break chain
 	#100000;
+	$display("\nSingle packet\n");
+	queue_rx_cmd(1,0,8,32'h0,32'h0);  // send imm, single packet
+	#100000;
 	$display("\nEnd chain with zero samples, shouldn't error\n");
 	queue_rx_cmd(1,1,8,32'h0,32'h0);  // chained
 	queue_rx_cmd(0,0,0,32'h0,32'h0);  // end chain with zero samples, should keep us out of error