wishbone bridge now with minimal functionality. Need to check

timing and handle wait states.

8 files changed, 121 insertions, 11 deletions

diff --git a/usrp2/gpmc/gpmc.v b/usrp2/gpmc/gpmc.v
index 96ee139fd..1963af6e6 100644
--- a/usrp2/gpmc/gpmc.v
+++ b/usrp2/gpmc/gpmc.v
@@ -18,8 +18,8 @@ module gpmc
 
    // CS4 is RAM_2PORT for high-speed data
    ram_2port #(.DWIDTH(16), .AWIDTH(10)) ram_2port
-     (.clka(clk_fpga), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram),
-      .clkb(clk_fpga), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
+     (.clka(wb_clk), .ena(~EM_NCS4), .wea(~EM_NWE), .addra(EM_A), .dia(EM_D), .doa(EM_D_ram),
+      .clkb(wb_clk), .enb(0), .web(0), .addrb(0), .dib(0), .dob());
 
    // CS6 is Control, Wishbone bus bridge (wb master)
    // Sync version
diff --git a/usrp2/models/gpmc_model.v b/usrp2/models/gpmc_model.v
new file mode 100644
index 000000000..ce3acaacf
--- /dev/null
+++ b/usrp2/models/gpmc_model.v
@@ -0,0 +1,70 @@
+
+
+module gpmc_model
+  (output EM_CLK, inout [15:0] EM_D, output reg [10:1] EM_A, output reg [1:0] EM_NBE,
+   output reg EM_WAIT0, output reg EM_NCS4, output reg EM_NCS6, 
+   output reg EM_NWE, output reg EM_NOE );
+
+   assign EM_CLK = 0;
+   reg [15:0] EM_D_int;
+   assign EM_D = EM_D_int;
+   
+   initial
+     begin
+	EM_A <= 10'bz;
+	EM_NBE <= 2'b11;
+	EM_NWE <= 1;
+	EM_NOE <= 1;
+	EM_NCS4 <= 1;
+	EM_NCS6 <= 1;
+	EM_D_int <= 16'bz;
+ 	EM_WAIT0 <= 0;  // FIXME this is actually an input
+     end
+   
+   task GPMC_Write;
+      input [10:0] addr;
+      input [15:0] data;
+      begin
+	 #2;
+	 EM_A <= addr[10:1];
+	 EM_D_int <= data;
+	 #4;
+	 EM_NCS6 <= 0;
+	 #5;
+	 EM_NWE <= 0;
+	 #41;
+	 EM_NWE <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 EM_D_int <= 16'bz;
+      end
+   endtask // GPMC_Write
+
+   task GPMC_Read;
+      input [10:0] addr;
+      begin
+	 #2;
+	 EM_A <= addr[10:1];
+	 #4;
+	 EM_NCS6 <= 0;
+	 #5;
+	 EM_NOE <= 0;
+	 #41;
+	 EM_NOE <= 1;
+	 EM_NCS6 <= 1;
+	 EM_A <= 10'bz;
+	 $display("Data Read from GPMC: %X",EM_D);
+      end
+   endtask // GPMC_Read
+   
+   initial
+     begin
+	#1000;
+	GPMC_Write(36,16'hBEEF);
+	#1000;
+	GPMC_Read(36);
+	#1000;
+	$finish;
+     end
+   
+endmodule // gpmc_model
diff --git a/usrp2/top/u1e/.gitignore b/usrp2/top/u1e/.gitignore
index f8b57ea21..8d872713e 100644
--- a/usrp2/top/u1e/.gitignore
+++ b/usrp2/top/u1e/.gitignore
@@ -2,3 +2,5 @@
 build
 *.log
 *.cmd
+tb_u1e
+*.lxt
diff --git a/usrp2/top/u1e/README b/usrp2/top/u1e/README
new file mode 100644
index 000000000..14c7a4955
--- /dev/null
+++ b/usrp2/top/u1e/README
@@ -0,0 +1,4 @@
+
+make clean
+make sim
+./tb_u1e -lxt2
diff --git a/usrp2/top/u1e/cmdfile b/usrp2/top/u1e/cmdfile
new file mode 100644
index 000000000..5e4db5c65
--- /dev/null
+++ b/usrp2/top/u1e/cmdfile
@@ -0,0 +1,19 @@
+
+# My stuff
+-y .
+-y ../../control_lib
+-y ../../control_lib/newfifo
+-y ../../sdr_lib
+-y ../../timing
+-y ../../coregen
+-y ../../gpmc
+
+# Models
+-y ../../models
+
+# Open Cores
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+
diff --git a/usrp2/top/u1e/make.sim b/usrp2/top/u1e/make.sim
new file mode 100644
index 000000000..1c163884c
--- /dev/null
+++ b/usrp2/top/u1e/make.sim
@@ -0,0 +1,7 @@
+all: sim
+
+sim:	
+	iverilog -Wimplicit -Wportbind -c cmdfile tb_u1e.v -o tb_u1e
+
+clean:
+	rm -f tb_u1e *.vcd *.lxt a.out
diff --git a/usrp2/top/u1e/tb_u1e.v b/usrp2/top/u1e/tb_u1e.v
index 6e0c60e17..85d2b49f0 100644
--- a/usrp2/top/u1e/tb_u1e.v
+++ b/usrp2/top/u1e/tb_u1e.v
@@ -6,8 +6,12 @@ module tb_u1e();
    wire [2:0] debug_led;
    wire [31:0] debug;
    wire [1:0] debug_clk;
-   
-   
+
+   initial begin
+      $dumpfile("tb_u1e.lxt");
+      $dumpvars(0,tb_u1e);
+   end
+    
    // GPMC
    wire       EM_CLK, EM_WAIT0, EM_NCS4, EM_NCS6, EM_NWE, EM_NOE;
    wire [15:0] EM_D;
@@ -15,11 +19,16 @@ module tb_u1e();
    wire [1:0]  EM_NBE;
    
    reg  clk_fpga = 0;
-   always #100 clk_fpga = ~clk_fpga;
+   always #15.625 clk_fpga = ~clk_fpga;
    
    u1e_core u1e_core(.clk_fpga(clk_fpga), .debug_led(debug_led), .debug(debug), .debug_clk(debug_clk),
 		     .EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
 		     .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
 		     .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
+
+   gpmc_model gpmc_model
+     (.EM_CLK(EM_CLK), .EM_D(EM_D), .EM_A(EM_A), .EM_NBE(EM_NBE),
+      .EM_WAIT0(EM_WAIT0), .EM_NCS4(EM_NCS4), .EM_NCS6(EM_NCS6), 
+      .EM_NWE(EM_NWE), .EM_NOE(EM_NOE) );
    
-endmodule // u1e
+endmodule // tb_u1e
diff --git a/usrp2/top/u1e/u1e_core.v b/usrp2/top/u1e/u1e_core.v
index 2481549b2..b0edbb9b6 100644
--- a/usrp2/top/u1e/u1e_core.v
+++ b/usrp2/top/u1e/u1e_core.v
@@ -10,7 +10,7 @@ module u1e_core
    );
 
    // Debug circuitry
-   reg [31:0] 	ctr;
+   reg [31:0] 	ctr=0;
    always @(posedge clk_fpga)
      ctr <= ctr + 1;
    
@@ -37,7 +37,7 @@ module u1e_core
    assign wb_clk = clk_fpga;
    reg [15:0] 	reg_fast, reg_slow;
 
-   localparam [10:0] WB_ADR_REG_FAST = 36;
+   localparam [10:0] WB_ADR_REG_FAST = 11'd36;
    localparam [10:0] WB_ADR_REG_SLOW = 38;
    
    always @(posedge wb_clk)
@@ -47,6 +47,5 @@ module u1e_core
    assign wb_dat_miso = (wb_adr == WB_ADR_REG_FAST) ? reg_fast : 16'bx;
 
    assign wb_ack = wb_stb & wb_cyc;
-   
-   
-endmodule // u2plus
+      
+endmodule // u1e_core