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author | Matt Ettus <matt@ettus.com> | 2011-03-23 18:51:36 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-05-26 17:31:21 -0700 |
commit | 88cc06c10e9aaf7db13557a581f0489b226e7e78 (patch) | |
tree | d7670136e124441c296448b5d0561d258de0dc35 | |
parent | d71f8599d0698e951ccd35ee96da9cd2229a9987 (diff) | |
download | uhd-88cc06c10e9aaf7db13557a581f0489b226e7e78.tar.gz uhd-88cc06c10e9aaf7db13557a581f0489b226e7e78.tar.bz2 uhd-88cc06c10e9aaf7db13557a581f0489b226e7e78.zip |
u1p: better way of reframing the packets
-rw-r--r-- | usrp2/gpif/gpif.v | 11 | ||||
-rw-r--r-- | usrp2/gpif/gpif_wr_tb.v | 15 | ||||
-rw-r--r-- | usrp2/gpif/packet_reframer.v | 62 |
3 files changed, 83 insertions, 5 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v index 8cac8b466..4f0ed233b 100644 --- a/usrp2/gpif/gpif.v +++ b/usrp2/gpif/gpif.v @@ -61,9 +61,18 @@ module gpif .ctrl_o(ctrl_data), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy), .debug(debug_wr) ); + // join vita packets which are longer than one frame, drop frame padding + wire [18:0] refr_data; + wire refr_src_rdy, refr_dst_rdy; + + packet_reframer tx_packet_reframer + (.clk(fifo_clk), .reset(fifo_rst), .clear(clear_tx), + .data_i(tx19_data), .src_rdy_i(tx19_src_rdy), .dst_rdy_o(tx19_dst_rdy), + .data_o(refr_data), .src_rdy_o(refr_src_rdy), .dst_rdy_i(refr_dst_rdy)); + fifo19_to_fifo36 #(.LE(1)) f19_to_f36 (.clk(fifo_clk), .reset(fifo_rst), .clear(0), - .f19_datain(tx19_data), .f19_src_rdy_i(tx19_src_rdy), .f19_dst_rdy_o(tx19_dst_rdy), + .f19_datain(refr_data), .f19_src_rdy_i(refr_src_rdy), .f19_dst_rdy_o(refr_dst_rdy), .f36_dataout(tx36_data), .f36_src_rdy_o(tx36_src_rdy), .f36_dst_rdy_i(tx36_dst_rdy)); fifo_cascade #(.WIDTH(36), .SIZE(TXFIFOSIZE)) tx_fifo36 diff --git a/usrp2/gpif/gpif_wr_tb.v b/usrp2/gpif/gpif_wr_tb.v index 6cfa13744..134365c87 100644 --- a/usrp2/gpif/gpif_wr_tb.v +++ b/usrp2/gpif/gpif_wr_tb.v @@ -26,6 +26,9 @@ module gpif_wr_tb(); initial #1000 sys_rst = 0; always #64 gpif_clk <= ~gpif_clk; always #47.9 sys_clk <= ~sys_clk; + + wire [18:0] data_int; + wire src_rdy_int, dst_rdy_int; gpif_wr gpif_write (.gpif_clk(gpif_clk), .gpif_rst(gpif_rst), @@ -33,9 +36,14 @@ module gpif_wr_tb(); .gpif_full_d(DF), .gpif_full_c(CF), .sys_clk(sys_clk), .sys_rst(sys_rst), - .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy), + .data_o(data_int), .src_rdy_o(src_rdy_int), .dst_rdy_i(dst_rdy_int), .ctrl_o(ctrl_o), .ctrl_src_rdy_o(ctrl_src_rdy), .ctrl_dst_rdy_i(ctrl_dst_rdy) ); + packet_reframer tx_packet_reframer + (.clk(sys_clk), .reset(sys_rst), .clear(0), + .data_i(data_int), .src_rdy_i(src_rdy_int), .dst_rdy_o(dst_rdy_int), + .data_o(data_o), .src_rdy_o(src_rdy), .dst_rdy_i(dst_rdy)); + always @(posedge sys_clk) if(ctrl_src_rdy & ctrl_dst_rdy) $display("CTRL: %x",ctrl_o); @@ -56,7 +64,7 @@ module gpif_wr_tb(); repeat (1) begin WR <= 1; - gpif_data <= 150; // Length + gpif_data <= 10; // Length @(posedge gpif_clk); gpif_data <= 16'h00; @(posedge gpif_clk); @@ -69,14 +77,13 @@ module gpif_wr_tb(); repeat (20) @(posedge gpif_clk); WR <= 1; - gpif_data <= 16'hFF; + gpif_data <= 16'h5; @(posedge gpif_clk); repeat(254) begin gpif_data <= gpif_data - 1; @(posedge gpif_clk); end - end end // initial begin diff --git a/usrp2/gpif/packet_reframer.v b/usrp2/gpif/packet_reframer.v new file mode 100644 index 000000000..336c36369 --- /dev/null +++ b/usrp2/gpif/packet_reframer.v @@ -0,0 +1,62 @@ + +// Join vita packets longer than one GPIF frame, drop padding on short frames + +module packet_reframer + (input clk, input reset, input clear, + input [18:0] data_i, + input src_rdy_i, + output dst_rdy_o, + output [18:0] data_o, + output src_rdy_o, + input dst_rdy_i); + + reg [1:0] state; + reg [15:0] length; + + localparam RF_IDLE = 0; + localparam RF_PKT = 1; + localparam RF_DUMP = 2; + + always @(posedge clk) + if(reset | clear) + state <= 0; + else + if(src_rdy_i & dst_rdy_i) + case(state) + RF_IDLE : + begin + length <= {data_i[14:0],1'b0}; + state <= RF_PKT; + end + RF_PKT : + begin + if(length == 2) + if(data_i[17]) + state <= RF_IDLE; + else + state <= RF_DUMP; + else + length <= length - 1; + end + RF_DUMP : + if(data_i[17]) + state <= RF_IDLE; + default : + state<= RF_IDLE; + endcase // case (state) + + assign dst_rdy_o = dst_rdy_i; // this is a little pessimistic but ok + assign src_rdy_o = src_rdy_i & (state != RF_DUMP); + + wire occ_out = 0; + wire eof_out = (state == RF_PKT) & (length == 2); + wire sof_out = (state == RF_IDLE); + wire [15:0] data_out = data_i[15:0]; + assign data_o = {occ_out, eof_out, sof_out, data_out}; + + +endmodule // packet_reframer + + + + |