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authorMatt Ettus <matt@ettus.com>2010-07-06 14:28:18 -0700
committerMatt Ettus <matt@ettus.com>2011-05-26 17:31:19 -0700
commit038ea25032068ea228442dbe86c01f25f51a0d75 (patch)
tree1e017e08923d01938b45265778c9f017ec54c401
parent900f8cd5528bd92e1b00c1cdd2a923234bed8466 (diff)
downloaduhd-038ea25032068ea228442dbe86c01f25f51a0d75.tar.gz
uhd-038ea25032068ea228442dbe86c01f25f51a0d75.tar.bz2
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hook up flow control pins
-rw-r--r--usrp2/gpif/gpif.v12
1 files changed, 10 insertions, 2 deletions
diff --git a/usrp2/gpif/gpif.v b/usrp2/gpif/gpif.v
index 9697a7f8b..789e22e98 100644
--- a/usrp2/gpif/gpif.v
+++ b/usrp2/gpif/gpif.v
@@ -23,9 +23,17 @@ module gpif
wire WR = gpif_ctl[0];
wire RD = gpif_ctl[1];
wire OE = gpif_ctl[2];
-
+ wire have_space, have_pkt_rdy;
wire [15:0] gpif_dat_out;
assign gpif_dat = OE ? gpif_dat_out : 16'bz;
+
+ assign gpif_rdy[0] = have_space;
+ assign gpif_rdy[1] = have_pkt_rdy;
+
+ wire [15:0] gpif_d_copy = gpif_d;
+
+ assign debug0 = {11'd0, WR, RD, OE, have_space, have_pkt_rdy, gpif_d_copy};
+ assign debug1 = 32'd0;
// ////////////////////////////////////////////////////////////////////
// TX Side
@@ -39,7 +47,7 @@ module gpif
gpif_wr gpif_wr
(.gpif_clk(gpif_clk), .gpif_rst(gpif_rst),
- .gpif_data(gpif_d), .gpif_wr(WR), .have_space(gpif_rdy[0]),
+ .gpif_data(gpif_d), .gpif_wr(WR), .have_space(have_space),
.sys_clk(fifo_clk), .sys_rst(fifo_rst),
.data_o(tx19_data), .src_rdy_o(tx19_src_rdy), .dst_rdy_i(tx_19_dst_rdy),
.debug() );