put new setting reg into the address space in the right place

1 files changed, 1 insertions, 1 deletions

diff --git a/vrt/vita_tx_control.v b/vrt/vita_tx_control.v
index 2af68c073..418bd1850 100644
--- a/vrt/vita_tx_control.v
+++ b/vrt/vita_tx_control.v
@@ -42,7 +42,7 @@ module vita_tx_control
    reg [2:0] ibs_state;
 
    wire      clear_state;
-   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+3)) sr_3
+   setting_reg #(.my_addr(BASE+3)) sr
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(),.changed(clear_state));