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| author | Matt Ettus <matt@ettus.com> | 2009-11-18 16:37:23 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2009-11-18 16:37:23 -0800 |
| commit | f31b84fb006ca7614a5fe1885b6e5b1cdc25d2a5 (patch) | |
| tree | 5dcb8c6166f75cabb2f879c0e45240ff077025a3 | |
| parent | 72cc0e23976c03627877f9bdfc26e81b333ae012 (diff) | |
| download | uhd-f31b84fb006ca7614a5fe1885b6e5b1cdc25d2a5.tar.gz uhd-f31b84fb006ca7614a5fe1885b6e5b1cdc25d2a5.tar.bz2 uhd-f31b84fb006ca7614a5fe1885b6e5b1cdc25d2a5.zip | |
be a little more PC about it
| -rw-r--r-- | vrt/vita_rx_framer.v | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/vrt/vita_rx_framer.v b/vrt/vita_rx_framer.v index ebf55d5c2..d3ff98df7 100644 --- a/vrt/vita_rx_framer.v +++ b/vrt/vita_rx_framer.v @@ -30,13 +30,17 @@ module vita_rx_framer wire [63:0] vita_time_fifo_o = sample_fifo_i[SAMP_WIDTH-5:SAMP_WIDTH-68]; reg [31:0] data_fifo_o; - wire [127:0] XILINX_SUCKS = sample_fifo_i; + + // The tools won't synthesize properly without this kludge because of the variable + // parameter length + + wire [127:0] FIXED_WIDTH_KLUDGE = sample_fifo_i; always @* case(sample_phase) - 4'd0 : data_fifo_o = XILINX_SUCKS[31:0]; - 4'd1 : data_fifo_o = XILINX_SUCKS[63:32]; - 4'd2 : data_fifo_o = XILINX_SUCKS[95:64]; - 4'd3 : data_fifo_o = XILINX_SUCKS[127:96]; + 4'd0 : data_fifo_o = FIXED_WIDTH_KLUDGE[31:0]; + 4'd1 : data_fifo_o = FIXED_WIDTH_KLUDGE[63:32]; + 4'd2 : data_fifo_o = FIXED_WIDTH_KLUDGE[95:64]; + 4'd3 : data_fifo_o = FIXED_WIDTH_KLUDGE[127:96]; default : data_fifo_o = 32'hDEADBEEF; endcase // case (sample_phase) |