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| author | Matt Ettus <matt@ettus.com> | 2011-03-16 12:02:12 -0700 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-03-16 12:26:39 -0700 |
| commit | 8f0b80498ecfc16004d3e5dad19c69b20a3b89fb (patch) | |
| tree | 586606a950990129054b73ba3231c065ec3ca442 | |
| parent | 487f693e2c7d19132e56f3d3674bfc6e267b57ab (diff) | |
| download | uhd-8f0b80498ecfc16004d3e5dad19c69b20a3b89fb.tar.gz uhd-8f0b80498ecfc16004d3e5dad19c69b20a3b89fb.tar.bz2 uhd-8f0b80498ecfc16004d3e5dad19c69b20a3b89fb.zip | |
udp: look for checksum in the right place
| -rw-r--r-- | usrp2/udp/prot_eng_tx.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/udp/prot_eng_tx.v b/usrp2/udp/prot_eng_tx.v index 0c3e58892..7d6454c01 100644 --- a/usrp2/udp/prot_eng_tx.v +++ b/usrp2/udp/prot_eng_tx.v @@ -30,10 +30,10 @@ module prot_eng_tx reg [15:0] pre_checksums [0:3]; always @(posedge clk) - if(set_stb & (set_addr == (BASE+6))) + if(set_stb & (set_addr == (BASE+7))) pre_checksums[set_addr[5:4]] <= set_data[15:0]; - wire [15:0] pre_checksum = header_ram[port_sel[1:0]]; + wire [15:0] pre_checksum = pre_checksums[port_sel[1:0]]; // Protocol State Machine reg [15:0] length; |