added ability to truly clear out the entire rx chain. also removed old style fifo in rx.

3 files changed, 27 insertions, 29 deletions

diff --git a/usrp2/top/u2_rev3/u2_core_udp.v b/usrp2/top/u2_rev3/u2_core_udp.v
index ea4dd314f..ec973df8d 100644
--- a/usrp2/top/u2_rev3/u2_core_udp.v
+++ b/usrp2/top/u2_rev3/u2_core_udp.v
@@ -624,9 +624,15 @@ module u2_core
       .debug(debug_rx_dsp) );
 
    wire [31:0] 	 vrc_debug;
+   wire 	 clear_rx;
    
+   setting_reg #(.my_addr(SR_RX_CTRL+3)) sr_clear
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .strobe(set_stb_dsp),.addr(set_addr_dsp),.in(set_data_dsp),
+      .out(),.changed(clear_rx));
+
    vita_rx_control #(.BASE(SR_RX_CTRL), .WIDTH(32)) vita_rx_control
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .vita_time(vita_time), .overrun(overrun),
       .sample(sample_rx), .run(run_rx), .strobe(strobe_rx),
@@ -636,7 +642,7 @@ module u2_core
    wire [3:0] 	 vita_state;
    
    vita_rx_framer #(.BASE(SR_RX_CTRL), .MAXCHAN(1)) vita_rx_framer
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
       .set_stb(set_stb_dsp),.set_addr(set_addr_dsp),.set_data(set_data_dsp),
       .sample_fifo_i(rx_data), .sample_fifo_dst_rdy_o(rx_dst_rdy), .sample_fifo_src_rdy_i(rx_src_rdy),
       .data_o(rx1_data), .dst_rdy_i(rx1_dst_rdy), .src_rdy_o(rx1_src_rdy),
@@ -644,7 +650,7 @@ module u2_core
       .debug_rx(vita_state) );
 
    fifo_cascade #(.WIDTH(36), .SIZE(DSP_RX_FIFOSIZE)) rx_fifo_cascade
-     (.clk(dsp_clk), .reset(dsp_rst), .clear(0),
+     (.clk(dsp_clk), .reset(dsp_rst), .clear(clear_rx),
       .datain(rx1_data), .src_rdy_i(rx1_src_rdy), .dst_rdy_o(rx1_dst_rdy),
       .dataout({wr1_flags,wr1_dat}), .src_rdy_o(wr1_ready_i), .dst_rdy_i(wr1_ready_o));
 
diff --git a/usrp2/vrt/vita_rx_control.v b/usrp2/vrt/vita_rx_control.v
index 93673d292..ba63181f1 100644
--- a/usrp2/vrt/vita_rx_control.v
+++ b/usrp2/vrt/vita_rx_control.v
@@ -25,16 +25,14 @@ module vita_rx_control
    
    wire [63:0] 	  new_time;
    wire [31:0] 	  new_command;
-   wire 	  sc_pre1, clear_int, clear_reg;
+   wire 	  sc_pre1;
 
-   assign clear_int  = clear | clear_reg;
-   
    wire [63:0] 	  rcvtime_pre;
    reg [63:0] 	  rcvtime;
    wire [28:0] 	  numlines_pre;
    wire 	  send_imm_pre, chain_pre, reload_pre;
    reg 		  send_imm, chain, reload;
-   wire 	  full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
+   wire 	  read_ctrl, empty_ctrl, write_ctrl;
    reg 		  sc_pre2;
    wire [33:0] 	  fifo_line;
    reg [28:0] 	  lines_left, lines_total;
@@ -54,21 +52,22 @@ module vita_rx_control
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(new_time[31:0]),.changed(sc_pre1));
    
-   setting_reg #(.my_addr(BASE+3)) sr_clear
-     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_reg));
-
    // FIFO to store commands sent from the settings bus
    always @(posedge clk)
-     sc_pre2 		  <= sc_pre1;
+     if(reset | clear)
+       sc_pre2 <= 0;
+     else
+       sc_pre2 <= sc_pre1;
+   
    assign      write_ctrl  = sc_pre1 & ~sc_pre2;
 
    wire [4:0]  command_queue_len;
-   shortfifo #(.WIDTH(96)) commandfifo
-     (.clk(clk),.rst(reset),.clear(clear_int),
-      .datain({new_command,new_time}), .write(write_ctrl&~full_ctrl), .full(full_ctrl),
+   
+   fifo_short #(.WIDTH(96)) commandfifo
+     (.clk(clk),.reset(reset),.clear(clear),
+      .datain({new_command,new_time}), .src_rdy_i(write_ctrl), .dst_rdy_o(),
       .dataout({send_imm_pre,chain_pre,reload_pre,numlines_pre,rcvtime_pre}),
-      .read(read_ctrl), .empty(empty_ctrl),
+      .src_rdy_o(empty_ctrl), .dst_rdy_i(read_ctrl),
       .occupied(command_queue_len), .space() );
    
    reg [33:0]  pkt_fifo_line;
@@ -92,7 +91,7 @@ module vita_rx_control
 				       (ibs_state==IBS_BROKENCHAIN) | (ibs_state==IBS_LATECMD));
    
    fifo_short #(.WIDTH(4+64+WIDTH)) rx_sample_fifo
-     (.clk(clk),.reset(reset),.clear(clear_int),
+     (.clk(clk),.reset(reset),.clear(clear),
       .datain({flags,vita_time,sample}), .src_rdy_i(attempt_sample_write), .dst_rdy_o(sample_fifo_in_rdy),
       .dataout(sample_fifo_o), 
       .src_rdy_o(sample_fifo_src_rdy_o), .dst_rdy_i(sample_fifo_dst_rdy_i),
@@ -107,7 +106,7 @@ module vita_rx_control
    wire full 		    = ~sample_fifo_in_rdy;
    
    always @(posedge clk)
-     if(reset | clear_int)
+     if(reset | clear)
        begin
 	  ibs_state 	   <= IBS_IDLE;
 	  lines_left 	   <= 0;
@@ -185,7 +184,7 @@ module vita_rx_control
    
    assign debug_rx = { { ibs_state[2:0], command_queue_len },
 		       { 8'd0 },
-		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, full_ctrl, empty_ctrl },
+		       { go_now, too_late, run, strobe, read_ctrl, write_ctrl, 1'b0, empty_ctrl },
 		       { 2'b0, overrun, chain_pre, sample_fifo_in_rdy, attempt_sample_write, sample_fifo_src_rdy_o,sample_fifo_dst_rdy_i} };
    
 endmodule // rx_control
diff --git a/usrp2/vrt/vita_rx_framer.v b/usrp2/vrt/vita_rx_framer.v
index 235817941..1065ce637 100644
--- a/usrp2/vrt/vita_rx_framer.v
+++ b/usrp2/vrt/vita_rx_framer.v
@@ -57,13 +57,6 @@ module vita_rx_framer
    wire [15:0] 	  vita_pkt_len = samples_per_packet + 6;
    //wire [3:0] flags = {signal_overrun,signal_brokenchain,signal_latecmd,signal_cmd_done};
 
-   wire 	  clear_reg;
-   wire 	  clear_int  = clear | clear_reg;
-
-   setting_reg #(.my_addr(BASE+3)) sr_clear
-     (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
-      .in(set_data),.out(),.changed(clear_reg));
-
    setting_reg #(.my_addr(BASE+4)) sr_header
      (.clk(clk),.rst(reset),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out(vita_header),.changed());
@@ -102,7 +95,7 @@ module vita_rx_framer
    localparam VITA_ERR_TRAILER 	 = 15; // Extension context packets have no trailer
       
    always @(posedge clk)
-     if(reset | clear_pkt_count)
+     if(reset | clear | clear_pkt_count)
        pkt_count <= 0;
      else if((vita_state == VITA_TRAILER) & pkt_fifo_rdy)
        pkt_count <= pkt_count + 1;
@@ -135,7 +128,7 @@ module vita_rx_framer
        endcase // case (vita_state)
 
    always @(posedge clk)
-     if(reset)
+     if(reset | clear)
        begin
 	  vita_state   <= VITA_IDLE;
 	  sample_ctr   <= 0;
@@ -203,7 +196,7 @@ module vita_rx_framer
    
    // Short FIFO to buffer between us and the FIFOs outside
    fifo_short #(.WIDTH(34)) rx_pkt_fifo 
-     (.clk(clk), .reset(reset), .clear(clear_int),
+     (.clk(clk), .reset(reset), .clear(clear),
       .datain(pkt_fifo_line), .src_rdy_i(req_write_pkt_fifo), .dst_rdy_o(pkt_fifo_rdy),
       .dataout(data_o[33:0]), .src_rdy_o(src_rdy_o), .dst_rdy_i(dst_rdy_i),
       .space(),.occupied(fifo_occupied[4:0]) );