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author | Matt Ettus <matt@ettus.com> | 2011-10-07 12:36:54 -0700 |
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committer | Matt Ettus <matt@ettus.com> | 2011-10-26 15:57:22 -0700 |
commit | 550e32bd1ef550a7b90e9aec4baa6a10fb247176 (patch) | |
tree | 7b5c7e52d24b2b2d2fc90e4a12af570158a89af6 | |
parent | 80ec54d3f39536461c09c960c296e7c02c418310 (diff) | |
download | uhd-550e32bd1ef550a7b90e9aec4baa6a10fb247176.tar.gz uhd-550e32bd1ef550a7b90e9aec4baa6a10fb247176.tar.bz2 uhd-550e32bd1ef550a7b90e9aec4baa6a10fb247176.zip |
dspengine: move the register to VITA_RX_CTRL + 9 instead of + 3 which is occupied
-rw-r--r-- | usrp2/vrt/vita_rx_chain.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/usrp2/vrt/vita_rx_chain.v b/usrp2/vrt/vita_rx_chain.v index 28b5ea9ff..14c454f8a 100644 --- a/usrp2/vrt/vita_rx_chain.v +++ b/usrp2/vrt/vita_rx_chain.v @@ -65,7 +65,7 @@ module vita_rx_chain .data_i(rx_data_int), .src_rdy_i(rx_src_rdy_int), .dst_rdy_o(rx_dst_rdy_int), .data_o(rx_data_int2), .src_rdy_o(rx_src_rdy_int2), .dst_rdy_i(rx_dst_rdy_int2)); - dspengine_16to8 #(.BASE(BASE+3), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 + dspengine_16to8 #(.BASE(BASE+9), .BUF_SIZE(FIFOSIZE)) dspengine_16to8 (.clk(clk),.reset(rst),.clear(clear), .set_stb(set_stb), .set_addr(set_addr), .set_data(set_data), .access_we(access_we), .access_stb(access_stb), .access_ok(access_ok), .access_done(access_done), |