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| author | Matt Ettus <matt@ettus.com> | 2010-01-15 15:32:23 -0800 |
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-01-15 15:32:23 -0800 |
| commit | ffad1ae6b2a81e205ef53a871a848face9089ad4 (patch) | |
| tree | 1ec135b30556ca9545f56b97c2657ecc584d2e8f | |
| parent | e60bffc646a8fa7b3466da70f3d71a15abb0d3f1 (diff) | |
| download | uhd-ffad1ae6b2a81e205ef53a871a848face9089ad4.tar.gz uhd-ffad1ae6b2a81e205ef53a871a848face9089ad4.tar.bz2 uhd-ffad1ae6b2a81e205ef53a871a848face9089ad4.zip | |
yet more debug lines
| -rw-r--r-- | control_lib/newfifo/fifo19_to_fifo36.v | 7 | ||||
| -rw-r--r-- | udp/udp_wrapper.v | 6 |
2 files changed, 9 insertions, 4 deletions
diff --git a/control_lib/newfifo/fifo19_to_fifo36.v b/control_lib/newfifo/fifo19_to_fifo36.v index e22ca0a49..8a65d5189 100644 --- a/control_lib/newfifo/fifo19_to_fifo36.v +++ b/control_lib/newfifo/fifo19_to_fifo36.v @@ -7,7 +7,8 @@ module fifo19_to_fifo36 output [35:0] f36_dataout, output f36_src_rdy_o, - input f36_dst_rdy_i + input f36_dst_rdy_i, + output [31:0] debug ); reg f36_sof, f36_eof, f36_occ; @@ -67,5 +68,7 @@ module fifo19_to_fifo36 assign f19_dst_rdy_o = xfer_out | (state != 2); assign f36_dataout = {f36_occ,f36_eof,f36_sof,dat0,dat1}; assign f36_src_rdy_o = (state == 2); - + + assign debug = state; + endmodule // fifo19_to_fifo36 diff --git a/udp/udp_wrapper.v b/udp/udp_wrapper.v index c80421903..0bd997274 100644 --- a/udp/udp_wrapper.v +++ b/udp/udp_wrapper.v @@ -17,6 +17,7 @@ module udp_wrapper wire tx_int2_src_rdy, tx_int2_dst_rdy; wire [18:0] tx_int2_data; + wire [31:0] debug_state; // TX side fifo36_to_fifo19 fifo36_to_fifo19 @@ -67,7 +68,8 @@ module udp_wrapper fifo19_to_fifo36 fifo19_to_fifo36 (.clk(clk), .reset(reset), .clear(clear), .f19_datain(rx_int2_data), .f19_src_rdy_i(rx_int2_src_rdy), .f19_dst_rdy_o(rx_int2_dst_rdy), - .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy) ); + .f36_dataout(rx_int3_data), .f36_src_rdy_o(rx_int3_src_rdy), .f36_dst_rdy_i(rx_int3_dst_rdy), + .debug(debug_state); fifo_cascade #(.WIDTH(36),.SIZE(RXFIFOSIZE)) eth0_rxfifo (.clk(clk), .reset(reset), .clear(clear), @@ -78,6 +80,6 @@ module udp_wrapper assign debug = { { 1'b0, rx_f19_data[18:16], rx_f19_src_rdy_i, rx_f19_dst_rdy_o, rx_f36_src_rdy_o, rx_f36_dst_rdy_i }, { 2'b0, rx_int1_src_rdy, rx_int1_dst_rdy, rx_int2_src_rdy, rx_int2_dst_rdy, rx_int3_src_rdy, rx_int3_dst_rdy}, { rx_int3_data[35:32], rx_f36_data[35:32] }, - { 2'b0, rx_int1_data[18:16], rx_int2_data[18:16] } }; + { debug_state[1:0], rx_int1_data[18:16], rx_int2_data[18:16] } }; endmodule // udp_wrapper |