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| author | Matt Ettus <matt@ettus.com> | 2011-11-04 12:47:54 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-11-04 12:47:54 -0700 | 
| commit | 8ae4113fb0666490bf7a0bfce89009012d88b96b (patch) | |
| tree | 7fafa7e1ea7688934fe1d55e3b3b78357d7a0ac4 | |
| parent | 9fcc5fe50299dbc7583fb13bb5385685282a9976 (diff) | |
| download | uhd-8ae4113fb0666490bf7a0bfce89009012d88b96b.tar.gz uhd-8ae4113fb0666490bf7a0bfce89009012d88b96b.tar.bz2 uhd-8ae4113fb0666490bf7a0bfce89009012d88b96b.zip | |
dsp: remove warnings
| -rw-r--r-- | usrp2/sdr_lib/dsp_core_rx.v | 6 | ||||
| -rw-r--r-- | usrp2/sdr_lib/small_hb_int.v | 4 | 
2 files changed, 6 insertions, 4 deletions
| diff --git a/usrp2/sdr_lib/dsp_core_rx.v b/usrp2/sdr_lib/dsp_core_rx.v index 639744de7..d1c7e238a 100644 --- a/usrp2/sdr_lib/dsp_core_rx.v +++ b/usrp2/sdr_lib/dsp_core_rx.v @@ -94,8 +94,10 @@ module dsp_core_rx  	    .xi({adc_i_mux[23],adc_i_mux}),. yi({adc_q_mux[23],adc_q_mux}), .zi(phase[31:8]),  	    .xo(i_cordic),.yo(q_cordic),.zo() ); -   clip_reg #(.bits_in(25), .bits_out(24)) clip_i (.clk(clk), .in(i_cordic), .out(i_cordic_clip)); -   clip_reg #(.bits_in(25), .bits_out(24)) clip_q (.clk(clk), .in(q_cordic), .out(q_cordic_clip)); +   clip_reg #(.bits_in(25), .bits_out(24)) clip_i +     (.clk(clk), .in(i_cordic), .strobe_in(1'b1), .out(i_cordic_clip)); +   clip_reg #(.bits_in(25), .bits_out(24)) clip_q +     (.clk(clk), .in(q_cordic), .strobe_in(1'b1), .out(q_cordic_clip));     // CIC decimator  24 bit I/O     cic_strober cic_strober(.clock(clk),.reset(rst),.enable(run),.rate(cic_decim_rate), diff --git a/usrp2/sdr_lib/small_hb_int.v b/usrp2/sdr_lib/small_hb_int.v index 387f9e1cb..b69c45413 100644 --- a/usrp2/sdr_lib/small_hb_int.v +++ b/usrp2/sdr_lib/small_hb_int.v @@ -73,8 +73,8 @@ module small_hb_int       final_round (.clk(clk),.in(accum),.out(accum_rnd));     wire [WIDTH-1:0] 	 clipped; -   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) -     final_clip (.clk(clk),.in(accum_rnd),.out(clipped)); +   clip_reg #(.bits_in(WIDTH+3),.bits_out(WIDTH)) final_clip +     (.clk(clk),.in(accum_rnd),.strobe_in(1'b1), .out(clipped));     reg [WIDTH-1:0] 	 saved, saved_d3;     always @(posedge clk) | 
