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| author | Matt Ettus <matt@ettus.com> | 2010-06-03 08:44:13 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-06-03 08:44:13 -0700 | 
| commit | 4f1b2441c0250a61f691c038f8bd9cfb229bd103 (patch) | |
| tree | 84dc582b801eaa7141f79fe898a1be7c1f5a934f | |
| parent | d2163a256d55692c19b0a717e382850a6546f80f (diff) | |
| download | uhd-4f1b2441c0250a61f691c038f8bd9cfb229bd103.tar.gz uhd-4f1b2441c0250a61f691c038f8bd9cfb229bd103.tar.bz2 uhd-4f1b2441c0250a61f691c038f8bd9cfb229bd103.zip | |
Phil wants gpio #145
| -rw-r--r-- | usrp2/top/u1e_passthru/passthru.ucf | 4 | ||||
| -rw-r--r-- | usrp2/top/u1e_passthru/passthru.v | 4 | 
2 files changed, 4 insertions, 4 deletions
| diff --git a/usrp2/top/u1e_passthru/passthru.ucf b/usrp2/top/u1e_passthru/passthru.ucf index 3ffe33882..fcfce61b2 100644 --- a/usrp2/top/u1e_passthru/passthru.ucf +++ b/usrp2/top/u1e_passthru/passthru.ucf @@ -54,10 +54,10 @@  #NET "overo_gpio23"  LOC = "B3"  ;  # MISC GPIO for debug  #NET "overo_gpio64"  LOC = "A4"  ;  # MISC GPIO for debug  #NET "overo_gpio65"  LOC = "F8"  ;  # MISC GPIO for debug -NET "overo_gpio127"  LOC = "C8"  ;  # passed through as cgen_sen_b +#NET "overo_gpio127"  LOC = "C8"  ;  # passed through as cgen_sen_b  #NET "overo_gpio128"  LOC = "G8"  ;  # MISC GPIO for debug  #NET "overo_gpio144"  LOC = "A5"  ;  # tx_have_space -#NET "overo_gpio145"  LOC = "C7"  ;  # tx_underrun +NET "overo_gpio145"  LOC = "C7"  ;  # tx_underrun  #NET "overo_gpio146"  LOC = "A6"  ;  # rx_have_data  #NET "overo_gpio147"  LOC = "B6"  ;  # rx_overrun  #NET "overo_gpio163"  LOC = "D7"  ;  # MISC GPIO for debug diff --git a/usrp2/top/u1e_passthru/passthru.v b/usrp2/top/u1e_passthru/passthru.v index d846f2cf6..12e4db017 100644 --- a/usrp2/top/u1e_passthru/passthru.v +++ b/usrp2/top/u1e_passthru/passthru.v @@ -2,7 +2,7 @@  //////////////////////////////////////////////////////////////////////////////////  module passthru -  (input overo_gpio127, +  (input overo_gpio145,     output cgen_sclk,     output cgen_sen_b,     output cgen_mosi, @@ -11,7 +11,7 @@ module passthru     );     assign cgen_sclk = fpga_cfg_cclk; -   assign cgen_sen_b = overo_gpio127; +   assign cgen_sen_b = overo_gpio145;     assign cgen_mosi = fpga_cfg_din; | 
