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authorMatt Ettus <matt@ettus.com>2010-11-10 17:24:29 -0800
committerMatt Ettus <matt@ettus.com>2010-11-10 17:24:29 -0800
commitf64f1b5c86c605b7c769bbedd565e356d08e925d (patch)
tree0c139847d88f6425cd8f95154707210e7160f96d
parent7e20fa3db8e4990b47b346200f3c38bd8fa76f27 (diff)
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reverting part of the reversion of the spi settings.
-rw-r--r--usrp2/opencores/spi/rtl/verilog/spi_defines.v4
1 files changed, 2 insertions, 2 deletions
diff --git a/usrp2/opencores/spi/rtl/verilog/spi_defines.v b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
index 86c301886..3e4dd0e3c 100644
--- a/usrp2/opencores/spi/rtl/verilog/spi_defines.v
+++ b/usrp2/opencores/spi/rtl/verilog/spi_defines.v
@@ -43,8 +43,8 @@
// low frequency of system clock this can be reduced.
// Use SPI_DIVIDER_LEN for fine tuning theexact number.
//
-//`define SPI_DIVIDER_LEN_8
-`define SPI_DIVIDER_LEN_16
+`define SPI_DIVIDER_LEN_8
+//`define SPI_DIVIDER_LEN_16
//`define SPI_DIVIDER_LEN_24
//`define SPI_DIVIDER_LEN_32