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authoreb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2008-10-15 00:42:58 +0000
committereb <eb@221aa14e-8319-0410-a670-987f0aec2ac5>2008-10-15 00:42:58 +0000
commiteeed4fa3413e930b45caa96329c7ab6eed46434e (patch)
tree70c8c78600a53fe189c5a9265634158b0bc1c448
parent5fa9cd632b0d889256985b61ec67184c3a98909c (diff)
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Added firmware support for adc_mux to handle swapping I/Q, etc. Modified dsp_core_rx.v to swap A and B mapping so that the software thinks that the TVRX is connected to A/D A.
ISE 10.1 SP3 is required to compile the FPGA successfully. SP2 is insufficient. It compiles with SP2, but the firmware doesn't load. Only the F led is one in that case. git-svn-id: http://gnuradio.org/svn/gnuradio/trunk@9795 221aa14e-8319-0410-a670-987f0aec2ac5
-rw-r--r--sdr_lib/dsp_core_rx.v19
1 files changed, 14 insertions, 5 deletions
diff --git a/sdr_lib/dsp_core_rx.v b/sdr_lib/dsp_core_rx.v
index a2569a1dc..0e4af37fb 100644
--- a/sdr_lib/dsp_core_rx.v
+++ b/sdr_lib/dsp_core_rx.v
@@ -56,17 +56,26 @@ module dsp_core_rx
(.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
.in(set_data),.out(muxctrl),.changed());
+ // The TVRX connects to what is called adc_b, thus A and B are
+ // swapped throughout the design.
+ //
+ // In the interest of expediency and keeping the s/w sane, we just remap them here.
+ // The I & Q fields are mapped the same:
+ // 0 -> "the real A" (as determined by the TVRX)
+ // 1 -> "the real B"
+ // 2 -> const zero
+
always @(posedge clk)
- case(muxctrl[1:0])
- 0: adc_i <= adc_a_ofs;
- 1: adc_i <= adc_b_ofs;
+ case(muxctrl[1:0]) // The I mapping
+ 0: adc_i <= adc_b_ofs; // "the real A"
+ 1: adc_i <= adc_a_ofs;
2: adc_i <= 0;
default: adc_i <= 0;
endcase // case(muxctrl[1:0])
always @(posedge clk)
- case(muxctrl[3:2])
- 0: adc_q <= adc_b_ofs;
+ case(muxctrl[3:2]) // The Q mapping
+ 0: adc_q <= adc_b_ofs; // "the real A"
1: adc_q <= adc_a_ofs;
2: adc_q <= 0;
default: adc_q <= 0;