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| author | Matt Ettus <matt@ettus.com> | 2010-05-18 12:36:19 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2010-05-18 12:36:19 -0700 | 
| commit | 8214a30d10bbe30d04f74acca4bd683dc084f5df (patch) | |
| tree | 8307258790fbfb002f90b5d31481ea50277839ed | |
| parent | b9257e64be63429099186cdb1a3eaff0a325ffb7 (diff) | |
| download | uhd-8214a30d10bbe30d04f74acca4bd683dc084f5df.tar.gz uhd-8214a30d10bbe30d04f74acca4bd683dc084f5df.tar.bz2 uhd-8214a30d10bbe30d04f74acca4bd683dc084f5df.zip | |
added width parameter to avoid warnings (thanks IJB) and default value parameter
| -rw-r--r-- | usrp2/control_lib/setting_reg.v | 8 | 
1 files changed, 5 insertions, 3 deletions
| diff --git a/usrp2/control_lib/setting_reg.v b/usrp2/control_lib/setting_reg.v index ccbaa3d2e..3d3bb65e5 100644 --- a/usrp2/control_lib/setting_reg.v +++ b/usrp2/control_lib/setting_reg.v @@ -1,14 +1,16 @@  module setting_reg -  #(parameter my_addr = 0) +  #(parameter my_addr = 0,  +    parameter width = 32, +    parameter at_reset=32'd0)      (input clk, input rst, input strobe, input wire [7:0] addr, -     input wire [31:0] in, output reg [31:0] out, output reg changed); +     input wire [31:0] in, output reg [width-1:0] out, output reg changed);     always @(posedge clk)       if(rst)         begin -	  out <= 32'd0; +	  out <= at_reset;  	  changed <= 1'b0;         end       else | 
