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| author | Josh Blum <josh@joshknows.com> | 2011-05-23 10:40:42 -0700 |
|---|---|---|
| committer | Josh Blum <josh@joshknows.com> | 2011-05-23 10:40:42 -0700 |
| commit | 7437b27a15cb7022b8303c6bc2e7ea1bb5a900dc (patch) | |
| tree | 961ddcab7f03b2bba4e6dd4d4ee1b374e9f492e3 | |
| parent | 7dbd83533974713a4d170f01cd2421378cf96ec7 (diff) | |
| parent | 9b4fa86af2d0ed59d0881a3d153b309c94c7e4e5 (diff) | |
| download | uhd-7437b27a15cb7022b8303c6bc2e7ea1bb5a900dc.tar.gz uhd-7437b27a15cb7022b8303c6bc2e7ea1bb5a900dc.tar.bz2 uhd-7437b27a15cb7022b8303c6bc2e7ea1bb5a900dc.zip | |
Merge branch 'fpga_next' into uhd_master
| -rw-r--r-- | fpga/usrp2/top/u2plus/u2plus.v | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/fpga/usrp2/top/u2plus/u2plus.v b/fpga/usrp2/top/u2plus/u2plus.v index c0140e989..7c2270df6 100644 --- a/fpga/usrp2/top/u2plus/u2plus.v +++ b/fpga/usrp2/top/u2plus/u2plus.v @@ -348,12 +348,15 @@ module u2plus // DAC A is also inverted in schematic to facilitate clean layout always @(negedge dsp_clk) DACA <= ~dac_b_int; always @(negedge dsp_clk) DACB <= dac_a_int; + + wire pps; + assign pps = PPS_IN ^ PPS2_IN; u2plus_core u2p_c(.dsp_clk (dsp_clk), .wb_clk (wb_clk), .clock_ready (clock_ready), .clk_to_mac (CLK_TO_MAC_int2), - .pps_in (PPS_IN), + .pps_in (pps), .leds (leds_int), .debug (debug[31:0]), .debug_clk (debug_clk[1:0]), |