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| author | Matt Ettus <matt@ettus.com> | 2011-04-04 09:07:06 -0700 | 
|---|---|---|
| committer | Matt Ettus <matt@ettus.com> | 2011-06-08 10:52:51 -0700 | 
| commit | b97319808eb9108d7f1ac63b085b4557ce6b5acb (patch) | |
| tree | 0128c72298dc7305e2be615b3d4ef1bcf40f6440 | |
| parent | 47967a432248cacf6b17add35263308ecc0526f4 (diff) | |
| download | uhd-b97319808eb9108d7f1ac63b085b4557ce6b5acb.tar.gz uhd-b97319808eb9108d7f1ac63b085b4557ce6b5acb.tar.bz2 uhd-b97319808eb9108d7f1ac63b085b4557ce6b5acb.zip | |
dsp: first cut at sigma-delta rounding
| -rw-r--r-- | usrp2/sdr_lib/round_sd.v | 43 | ||||
| -rw-r--r-- | usrp2/sdr_lib/round_sd_tb.v | 49 | 
2 files changed, 92 insertions, 0 deletions
| diff --git a/usrp2/sdr_lib/round_sd.v b/usrp2/sdr_lib/round_sd.v new file mode 100644 index 000000000..9c2a69615 --- /dev/null +++ b/usrp2/sdr_lib/round_sd.v @@ -0,0 +1,43 @@ + + +module round_sd +  #(parameter WIDTH_IN=18, +    parameter WIDTH_OUT=16) +   (input clk, input reset, +    input [WIDTH_IN-1:0] in, output [WIDTH_OUT-1:0] out); + +   localparam SUM_WIDTH = WIDTH_IN+1; +   localparam ERR_WIDTH = SUM_WIDTH - (WIDTH_OUT + 1) + 1; +   localparam ACC_WIDTH = ERR_WIDTH + 1; +    +   reg [ACC_WIDTH-1:0] 	 acc; +   wire [SUM_WIDTH-1:0] acc_ext, in_ext; + +   sign_extend #(.bits_in(WIDTH_IN),.bits_out(SUM_WIDTH)) ext_in (.in(in), .out(in_ext)); +   sign_extend #(.bits_in(ACC_WIDTH),.bits_out(SUM_WIDTH)) ext_acc (.in(acc), .out(acc_ext)); +    +   wire [SUM_WIDTH-1:0] sum = in_ext + acc_ext; +   wire [WIDTH_OUT:0] 	sum_round; +   wire [ERR_WIDTH-1:0] err; +   wire [ACC_WIDTH-1:0] err_ext; +    +   //round_reg #(.bits_in(SUM_WIDTH),.bits_out(WIDTH_OUT+1))  round_sum (.clk(clk), .in(sum), .out(sum_round)); +   round #(.bits_in(SUM_WIDTH),.bits_out(WIDTH_OUT+1))  round_sum ( .in(sum), .out(sum_round)); + +   reg [WIDTH_IN-1:0] 	in_del; +   always @(posedge clk) +     in_del <= in; +    +   assign err = in_del - {sum_round,{SUM_WIDTH-WIDTH_OUT-1{1'b0}}}; +    +   clip #(.bits_in(WIDTH_OUT+1),.bits_out(WIDTH_OUT)) clip (.in(sum_round), .out(out)); + +   sign_extend #(.bits_in(ERR_WIDTH),.bits_out(ACC_WIDTH)) ext_err (.in(err), .out(err_ext)); +    +   always @(posedge clk) +     if(reset) +       acc <= 0; +     else +       acc <= acc + err_ext; +    +endmodule // rx_dcoffset diff --git a/usrp2/sdr_lib/round_sd_tb.v b/usrp2/sdr_lib/round_sd_tb.v new file mode 100644 index 000000000..df9f58421 --- /dev/null +++ b/usrp2/sdr_lib/round_sd_tb.v @@ -0,0 +1,49 @@ + +module round_sd_tb(); +    +   reg clk, rst; + +   initial rst = 1; +   initial #1000 rst = 0; +   initial clk = 0; +   always #5 clk = ~clk; +    +   initial $dumpfile("round_sd_tb.vcd"); +   initial $dumpvars(0,round_sd_tb); + +   localparam WIDTH_IN = 14; +   localparam WIDTH_OUT = 10; +    +   reg [WIDTH_IN-1:0] adc_in, adc_in_del; +   wire [WIDTH_OUT-1:0] adc_out; + +   integer 		factor = 1<<(WIDTH_IN-WIDTH_OUT); +    +   always @(posedge clk) +     if(~rst) +	begin   +	   if(adc_in_del[WIDTH_IN-1]) +	     $write("-%d\t",-adc_in_del); +	   else +	     $write("%d\t",adc_in_del); +	   if(adc_out[WIDTH_OUT-1]) +	     $write("-%d\t",-adc_out); +	   else +	     $write("%d\t",adc_out); +	   $write("%f\t",adc_in_del/factor); +	   $write("%f\n",adc_in_del/factor-adc_out); +	end	 +    +   round_sd #(.WIDTH_IN(WIDTH_IN),.WIDTH_OUT(WIDTH_OUT))  +   round_sd(.clk(clk),.reset(rst), .in(adc_in),.out(adc_out)); + +   always @(posedge clk) +     adc_in <= 4734; +     //adc_in <= $random % 4739; + +   always @(posedge clk) +     adc_in_del <= adc_in; + +   initial #10000 $finish; +    +endmodule // longfifo_tb | 
